x86/exceptions: Disconnect IST index and stack order

The entry order of the TSS.IST array and the order of the stack
storage/mapping are not required to be the same.

With the upcoming split of the debug stack this is going to fall apart as
the number of TSS.IST array entries stays the same while the actual stacks
are increasing.

Make them separate so that code like dumpstack can just utilize the mapping
order. The IST index is solely required for the actual TSS.IST array
initialization.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Baoquan He <bhe@redhat.com>
Cc: "Chang S. Bae" <chang.seok.bae@intel.com>
Cc: Dominik Brodowski <linux@dominikbrodowski.net>
Cc: Dou Liyang <douly.fnst@cn.fujitsu.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jann Horn <jannh@google.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Nicolai Stange <nstange@suse.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Qian Cai <cai@lca.pw>
Cc: Sean Christopherson <sean.j.christopherson@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20190414160145.241588113@linutronix.de

diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index fd0a50452cb3564643036d5e15669ab8e121081d..5c0348504a4bc0d10610124a960f2f7ede60aa78 100644 (file)
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -1129,7 +1129,7 @@ apicinterrupt3 HYPERV_STIMER0_VECTOR \
        hv_stimer0_callback_vector hv_stimer0_vector_handler
 #endif /* CONFIG_HYPERV */
 
-idtentry debug                 do_debug                has_error_code=0        paranoid=1 shift_ist=ESTACK_DB
+idtentry debug                 do_debug                has_error_code=0        paranoid=1 shift_ist=IST_INDEX_DB
 idtentry int3                  do_int3                 has_error_code=0
 idtentry stack_segment         do_stack_segment        has_error_code=1
 

diff --git a/arch/x86/include/asm/cpu_entry_area.h b/arch/x86/include/asm/cpu_entry_area.h
index 9b406f067ecf460e0a0665fc19cf1430e2fcf685..310eeb62d4184a83ebe606bf909501a10661aa69 100644 (file)
--- a/arch/x86/include/asm/cpu_entry_area.h
+++ b/arch/x86/include/asm/cpu_entry_area.h
@@ -35,6 +35,17 @@ struct cea_exception_stacks {
        ESTACKS_MEMBERS(0)
 };
 
+/*
+ * The exception stack ordering in [cea_]exception_stacks
+ */
+enum exception_stack_ordering {
+       ESTACK_DF,
+       ESTACK_NMI,
+       ESTACK_DB,
+       ESTACK_MCE,
+       N_EXCEPTION_STACKS
+};
+
 #define CEA_ESTACK_SIZE(st)                                    \
        sizeof(((struct cea_exception_stacks *)0)->st## _stack)
 

diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h
index 6ab2c54c1bf9702442ea2478c360309aa47196c8..056de887b2208ae4d448f010d7034adc7af224dd 100644 (file)
--- a/arch/x86/include/asm/page_64_types.h
+++ b/arch/x86/include/asm/page_64_types.h
@@ -27,11 +27,10 @@
 /*
  * The index for the tss.ist[] array. The hardware limit is 7 entries.
  */
-#define        ESTACK_DF               0
-#define        ESTACK_NMI              1
-#define        ESTACK_DB               2
-#define        ESTACK_MCE              3
-#define        N_EXCEPTION_STACKS      4
+#define        IST_INDEX_DF            0
+#define        IST_INDEX_NMI           1
+#define        IST_INDEX_DB            2
+#define        IST_INDEX_MCE           3
 
 /*
  * Set __PAGE_OFFSET to the most negative possible address +

diff --git a/arch/x86/include/asm/stacktrace.h b/arch/x86/include/asm/stacktrace.h
index f335aad404a479e98e4a5d38dc41ee5e5aa419ec..d6d758a187b6c5cc3559f7a9a49dceb6e011d871 100644 (file)
--- a/arch/x86/include/asm/stacktrace.h
+++ b/arch/x86/include/asm/stacktrace.h
@@ -9,6 +9,8 @@
 
 #include <linux/uaccess.h>
 #include <linux/ptrace.h>
+
+#include <asm/cpu_entry_area.h>
 #include <asm/switch_to.h>
 
 enum stack_type {

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 8243f198fb7fc38f2ac2858ce78f82ed8bfc5286..143aceaf9a9a597b094950994372359c904e5cbd 100644 (file)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1731,11 +1731,11 @@ void cpu_init(void)
         * set up and load the per-CPU TSS
         */
        if (!t->x86_tss.ist[0]) {
-               t->x86_tss.ist[ESTACK_DF] = __this_cpu_ist_top_va(DF);
-               t->x86_tss.ist[ESTACK_NMI] = __this_cpu_ist_top_va(NMI);
-               t->x86_tss.ist[ESTACK_DB] = __this_cpu_ist_top_va(DB);
-               t->x86_tss.ist[ESTACK_MCE] = __this_cpu_ist_top_va(MCE);
-               per_cpu(debug_stack_addr, cpu) = t->x86_tss.ist[ESTACK_DB];
+               t->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
+               t->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
+               t->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
+               t->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
+               per_cpu(debug_stack_addr, cpu) = t->x86_tss.ist[IST_INDEX_DB];
        }
 
        t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;

diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c
index 2188f734ec61341047ae31e31e6a94bfc1cb79c1..6d8917875f44a844e1f1eb20a35fc73a65655984 100644 (file)
--- a/arch/x86/kernel/idt.c
+++ b/arch/x86/kernel/idt.c
@@ -183,11 +183,11 @@ gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
  * cpu_init() when the TSS has been initialized.
  */
 static const __initconst struct idt_data ist_idts[] = {
-       ISTG(X86_TRAP_DB,       debug,          ESTACK_DB),
-       ISTG(X86_TRAP_NMI,      nmi,            ESTACK_NMI),
-       ISTG(X86_TRAP_DF,       double_fault,   ESTACK_DF),
+       ISTG(X86_TRAP_DB,       debug,          IST_INDEX_DB),
+       ISTG(X86_TRAP_NMI,      nmi,            IST_INDEX_NMI),
+       ISTG(X86_TRAP_DF,       double_fault,   IST_INDEX_DF),
 #ifdef CONFIG_X86_MCE
-       ISTG(X86_TRAP_MC,       &machine_check, ESTACK_MCE),
+       ISTG(X86_TRAP_MC,       &machine_check, IST_INDEX_MCE),
 #endif
 };