flush more register writings

SVN-Revision: 16415

diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
index 797e6f81a5bd6fa138bc341675dd36638854a619..7d204fd668433c52a3c1ab2454220374e8aa80a1 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
@@ -113,6 +113,9 @@ static void ar71xx_gpio_irq_unmask(unsigned int irq)
        irq -= AR71XX_GPIO_IRQ_BASE;
        ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
                        ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
+
+       /* flush write */
+       ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 }
 
 static void ar71xx_gpio_irq_mask(unsigned int irq)
@@ -120,6 +123,9 @@ static void ar71xx_gpio_irq_mask(unsigned int irq)
        irq -= AR71XX_GPIO_IRQ_BASE;
        ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
                        ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
+
+       /* flush write */
+       ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 }
 
 #if 0
@@ -211,6 +217,9 @@ static void ar71xx_misc_irq_unmask(unsigned int irq)
        irq -= AR71XX_MISC_IRQ_BASE;
        ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
                ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
+
+       /* flush write */
+       ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 }
 
 static void ar71xx_misc_irq_mask(unsigned int irq)
@@ -218,6 +227,9 @@ static void ar71xx_misc_irq_mask(unsigned int irq)
        irq -= AR71XX_MISC_IRQ_BASE;
        ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
                ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
+
+       /* flush write */
+       ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 }
 
 struct irq_chip ar71xx_misc_irq_chip = {