drm/i915: invalidate render cache on gen2

It looks like we also need to flush the render cache when we just
invalidate it. This fixes a regression in i-g-t/gem_tiled_blits on my
i855gm. I guess the render cache there is virtually indexed, so we
need to clean it when changing gtt mappings.

This regression has been introduce in

commit 46f0f8d120c4afae53a5670bf3ac80a928340ff3
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Apr 18 11:12:11 2012 +0100

    drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6f610f28b1be2d7488cf3e83abceb9442c4183b0..12d9bc789dfbe0ef3b269f548c66efc68a3140bf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -61,7 +61,7 @@ gen2_render_ring_flush(struct intel_ring_buffer *ring,
        int ret;
 
        cmd = MI_FLUSH;
-       if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
+       if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
                cmd |= MI_NO_WRITE_FLUSH;
 
        if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)