struct rockchip_spi_dma_data dma_tx;
};
-static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
+static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
{
- writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
+ writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
}
static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
{
struct rockchip_spi *rs = spi_master_get_devdata(master);
- spi_enable_chip(rs, 0);
+ spi_enable_chip(rs, false);
return 0;
}
{
int remain = 0;
- spi_enable_chip(rs, 1);
+ spi_enable_chip(rs, true);
do {
if (rs->tx) {
if (rs->tx)
wait_for_idle(rs);
- spi_enable_chip(rs, 0);
+ spi_enable_chip(rs, false);
return 0;
}
rs->state &= ~RXBUSY;
if (!(rs->state & TXBUSY)) {
- spi_enable_chip(rs, 0);
+ spi_enable_chip(rs, false);
spi_finalize_current_transfer(rs->master);
}
rs->state &= ~TXBUSY;
if (!(rs->state & RXBUSY)) {
- spi_enable_chip(rs, 0);
+ spi_enable_chip(rs, false);
spi_finalize_current_transfer(rs->master);
}
dma_async_issue_pending(rs->dma_rx.ch);
}
- spi_enable_chip(rs, 1);
+ spi_enable_chip(rs, true);
if (txdesc) {
spin_lock_irqsave(&rs->lock, flags);
goto err_disable_apbclk;
}
- spi_enable_chip(rs, 0);
+ spi_enable_chip(rs, false);
rs->type = SSI_MOTO_SPI;
rs->master = master;