drm/amd/powerplay: added soc15 support for new se_cac_idx APIs

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index ca9fa3fe788df3c3c8b04f99d8f2f96ef42ef03a..0d9a3dd302a77db0f4754c3c018c308a8428a91a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -218,6 +218,28 @@ static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
        spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 }
 
+static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
+{
+       unsigned long flags;
+       u32 r;
+
+       spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
+       WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
+       r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
+       spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
+       return r;
+}
+
+static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
+       WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
+       WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
+       spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
+}
+
 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 {
        if (adev->flags & AMD_IS_APU)
@@ -579,6 +601,8 @@ static int soc15_common_early_init(void *handle)
        adev->didt_wreg = &soc15_didt_wreg;
        adev->gc_cac_rreg = &soc15_gc_cac_rreg;
        adev->gc_cac_wreg = &soc15_gc_cac_wreg;
+       adev->se_cac_rreg = &soc15_se_cac_rreg;
+       adev->se_cac_wreg = &soc15_se_cac_wreg;
 
        adev->asic_funcs = &soc15_asic_funcs;