KVM: x86: Add Intel PT context switch for each vcpu

Load/Store Intel Processor Trace register in context switch.
MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS.
In Host-Guest mode, we need load/resore PT MSRs only when PT
is enabled in guest.

Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index f5b88b578bbee07f92431c933baafc30d27aeaff..462c716d46ac8c88a74f8bd5453f77f8d383b3c5 100644 (file)
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -936,6 +936,69 @@ static unsigned long segment_base(u16 selector)
 }
 #endif
 
+static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
+{
+       u32 i;
+
+       wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
+       wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
+       wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
+       wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
+       for (i = 0; i < addr_range; i++) {
+               wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
+               wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
+       }
+}
+
+static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
+{
+       u32 i;
+
+       rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
+       rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
+       rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
+       rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
+       for (i = 0; i < addr_range; i++) {
+               rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
+               rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
+       }
+}
+
+static void pt_guest_enter(struct vcpu_vmx *vmx)
+{
+       if (pt_mode == PT_MODE_SYSTEM)
+               return;
+
+       /* Save host state before VM entry */
+       rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
+
+       /*
+        * Set guest state of MSR_IA32_RTIT_CTL MSR (PT will be disabled
+        * on VM entry when it has been disabled in guest before).
+        */
+       vmcs_write64(GUEST_IA32_RTIT_CTL, vmx->pt_desc.guest.ctl);
+
+       if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
+               wrmsrl(MSR_IA32_RTIT_CTL, 0);
+               pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
+               pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
+       }
+}
+
+static void pt_guest_exit(struct vcpu_vmx *vmx)
+{
+       if (pt_mode == PT_MODE_SYSTEM)
+               return;
+
+       if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
+               pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
+               pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
+       }
+
+       /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
+       wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
+}
+
 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
 {
        struct vcpu_vmx *vmx = to_vmx(vcpu);
@@ -3814,6 +3877,13 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
 
        if (cpu_has_vmx_encls_vmexit())
                vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
+
+       if (pt_mode == PT_MODE_HOST_GUEST) {
+               memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
+               /* Bit[6~0] are forced to 1, writes are ignored. */
+               vmx->pt_desc.guest.output_mask = 0x7F;
+               vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
+       }
 }
 
 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
@@ -6115,6 +6185,8 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
            vcpu->arch.pkru != vmx->host_pkru)
                __write_pkru(vcpu->arch.pkru);
 
+       pt_guest_enter(vmx);
+
        atomic_switch_perf_msrs(vmx);
 
        vmx_update_hv_timer(vcpu);
@@ -6314,6 +6386,8 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
                                  | (1 << VCPU_EXREG_CR3));
        vcpu->arch.regs_dirty = 0;
 
+       pt_guest_exit(vmx);
+
        /*
         * eager fpu is enabled if PKEY is supported and CR4 is switched
         * back on host, so it is safe to read guest PKRU from current

diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 86eb9c8873869703dd6176e9cf86226c661bed19..dd3b9ab90556bfe843f3366685f0fd45eacbd2c7 100644 (file)
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -66,6 +66,25 @@ struct pi_desc {
        u32 rsvd[6];
 } __aligned(64);
 
+#define RTIT_ADDR_RANGE                4
+
+struct pt_ctx {
+       u64 ctl;
+       u64 status;
+       u64 output_base;
+       u64 output_mask;
+       u64 cr3_match;
+       u64 addr_a[RTIT_ADDR_RANGE];
+       u64 addr_b[RTIT_ADDR_RANGE];
+};
+
+struct pt_desc {
+       u64 ctl_bitmask;
+       u32 addr_range;
+       u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
+       struct pt_ctx host;
+       struct pt_ctx guest;
+};
 
 /*
  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
@@ -249,6 +268,8 @@ struct vcpu_vmx {
        u64 msr_ia32_feature_control;
        u64 msr_ia32_feature_control_valid_bits;
        u64 ept_pointer;
+
+       struct pt_desc pt_desc;
 };
 
 enum ept_pointers_status {