This should align opp table with what it was before converting to OPP v2.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
- 1 file changed, 26 insertions(+), 8 deletions(-)
+ 1 file changed, 30 insertions(+), 8 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
};
L2: l2-cache {
-@@ -94,6 +90,28 @@
+@@ -94,6 +90,32 @@
};
};
+ opp-48000000 {
+ opp-hz = /bits/ 64 <48000000>;
+ clock-latency-ns = <256000>;
++ opp-microvolt = <1100000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ clock-latency-ns = <256000>;
++ opp-microvolt = <1100000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <256000>;
++ opp-microvolt = <1100000>;
+ };
+ opp-716000000 {
+ opp-hz = /bits/ 64 <716000000>;
+ clock-latency-ns = <256000>;
++ opp-microvolt = <1100000>;
+ };
+ };
+
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -262,7 +262,7 @@
+@@ -266,7 +266,7 @@
saw0: regulator@b089000 {
compatible = "qcom,saw2";
};
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -410,5 +410,79 @@
+@@ -414,5 +414,79 @@
"legacy";
status = "disabled";
};
};
cpus {
-@@ -132,6 +134,12 @@
+@@ -136,6 +138,12 @@
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
-@@ -177,13 +185,13 @@
+@@ -181,13 +189,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
-@@ -191,7 +199,7 @@
+@@ -195,7 +203,7 @@
status = "disabled";
};
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-@@ -200,10 +208,26 @@
+@@ -204,10 +212,26 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-@@ -212,14 +236,29 @@
+@@ -216,14 +240,29 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
-@@ -293,7 +332,7 @@
+@@ -297,7 +336,7 @@
serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
-@@ -305,7 +344,7 @@
+@@ -309,7 +348,7 @@
serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
-@@ -327,6 +366,101 @@
+@@ -331,6 +370,101 @@
reg = <0x4ab000 0x4>;
};
wifi0: wifi@a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
-@@ -360,7 +494,7 @@
+@@ -364,7 +498,7 @@
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
-@@ -402,7 +536,7 @@
+@@ -406,7 +540,7 @@
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -381,7 +381,7 @@
+@@ -385,7 +385,7 @@
#size-cells = <2>;
ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -182,6 +182,7 @@
+@@ -186,6 +186,7 @@
compatible = "qcom,ipq4019-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
status = "ok";
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -346,7 +346,7 @@
+@@ -350,7 +350,7 @@
regulator;
};
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -397,8 +397,8 @@
+@@ -401,8 +401,8 @@
#address-cells = <3>;
#size-cells = <2>;
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -400,7 +400,7 @@
+@@ -404,7 +404,7 @@
ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
<0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -562,6 +562,34 @@
+@@ -566,6 +566,34 @@
status = "disabled";
};
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -590,6 +590,29 @@
+@@ -594,6 +594,29 @@
};
};
};
cpus {
-@@ -613,6 +615,64 @@
+@@ -617,6 +619,64 @@
status = "disabled";
};
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
---
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 54 ++++++++++++++---------------
- 1 file changed, 26 insertions(+), 28 deletions(-)
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 58 ++++++++++++++---------------
+ 1 file changed, 30 insertions(+), 28 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
};
L2: l2-cache {
-@@ -136,6 +112,28 @@
+@@ -136,6 +112,32 @@
};
};
+
+ opp-48000000 {
+ opp-hz = /bits/ 64 <48000000>;
++ opp-microvolt = <1100000>;
+ clock-latency-ns = <256000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
++ opp-microvolt = <1100000>;
+ clock-latency-ns = <256000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
++ opp-microvolt = <1100000>;
+ clock-latency-ns = <256000>;
+ };
+ opp-716000000 {
+ opp-hz = /bits/ 64 <716000000>;
++ opp-microvolt = <1100000>;
+ clock-latency-ns = <256000>;
+ };
+ };
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -321,7 +321,7 @@
+@@ -325,7 +325,7 @@
saw0: regulator@b089000 {
compatible = "qcom,saw2";
};
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -564,5 +564,79 @@
+@@ -568,5 +568,79 @@
"legacy";
status = "disabled";
};
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -401,7 +401,7 @@
+@@ -405,7 +405,7 @@
#size-cells = <2>;
ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -202,6 +202,7 @@
+@@ -206,6 +206,7 @@
compatible = "qcom,ipq4019-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -401,8 +401,8 @@
+@@ -405,8 +405,8 @@
#address-cells = <3>;
#size-cells = <2>;
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -404,7 +404,7 @@
+@@ -408,7 +408,7 @@
ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
<0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -566,6 +566,34 @@
+@@ -570,6 +570,34 @@
status = "disabled";
};
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -594,6 +594,29 @@
+@@ -598,6 +598,29 @@
};
};
};
cpus {
-@@ -617,6 +619,64 @@
+@@ -621,6 +623,64 @@
status = "disabled";
};