The device is booting and Ethernet is working, but nothing more was tested.
SVN-Revision: 18589
Build firmware images for Infineon Amazon boards
endef
+ifeq ($(KERNEL_PATCHVER),2.6.30)
+ define Kernel/Prepare
+ $(call Kernel/Prepare/Default)
+ mv $(LINUX_DIR)/include/asm-mips/mach-amazon $(LINUX_DIR)/arch/mips/include/asm/mach-amazon
+ mv $(LINUX_DIR)/drivers/char/watchdog/amazon_wdt.c $(LINUX_DIR)/drivers/watchdog/amazon_wdt.c
+ endef
+endif
+
$(eval $(call BuildTarget))
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_ADM6996_SUPPORT=y
+CONFIG_AMAZON=y
+CONFIG_AMAZON_ASC_UART=y
+CONFIG_AMAZON_MTD=y
+CONFIG_AMAZON_NET_SW=y
+CONFIG_AMAZON_PCI=y
+CONFIG_AMAZON_WDT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_BCM47XX is not set
+# CONFIG_BINARY_PRINTF is not set
+CONFIG_BITREVERSE=y
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/bin/sh"
+CONFIG_CPU_BIG_ENDIAN=y
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+# CONFIG_CPU_LOONGSON2 is not set
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR2=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CSRC_R4K=y
+CONFIG_CSRC_R4K_LIB=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DEVPORT=y
+# CONFIG_DM9000 is not set
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQ_CPU=y
+CONFIG_KALLSYMS=y
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MIPS_FPU_EMU is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MTD_AMAZON_BUS_WIDTH_16=y
+# CONFIG_MTD_AMAZON_BUS_WIDTH_32 is not set
+# CONFIG_MTD_AMAZON_BUS_WIDTH_8 is not set
+# CONFIG_MTD_AMAZON_FLASH_SIZE_16 is not set
+# CONFIG_MTD_AMAZON_FLASH_SIZE_2 is not set
+CONFIG_MTD_AMAZON_FLASH_SIZE_4=y
+# CONFIG_MTD_AMAZON_FLASH_SIZE_8 is not set
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
+CONFIG_MTD_REDBOOT_PARTS=y
+# CONFIG_NET_PCI is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PROBE_INITRD_HEADER is not set
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_TRAD_SIGNALS=y
+CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef __ASM_MIPS_MACH_AMAZON_WAR_H
+#define __ASM_MIPS_MACH_AMAZON_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif
--- /dev/null
+--- a/arch/mips/kernel/traps.c
++++ b/arch/mips/kernel/traps.c
+@@ -1542,7 +1542,16 @@ void __cpuinit per_cpu_trap_init(void)
+ */
+ if (cpu_has_mips_r2) {
+ cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
++ if (!cp0_compare_irq)
++ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
++
+ cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
++ if (!cp0_perfcount_irq)
++ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
++
++ if (arch_fixup_c0_irqs)
++ arch_fixup_c0_irqs();
++
+ if (cp0_perfcount_irq == cp0_compare_irq)
+ cp0_perfcount_irq = -1;
+ } else {
+--- a/arch/mips/include/asm/irq.h
++++ b/arch/mips/include/asm/irq.h
+@@ -157,8 +157,10 @@ extern void free_irqno(unsigned int irq)
+ * IE7. Since R2 their number has to be read from the c0_intctl register.
+ */
+ #define CP0_LEGACY_COMPARE_IRQ 7
++#define CP0_LEGACY_PERFCNT_IRQ 7
+
+ extern int cp0_compare_irq;
+ extern int cp0_perfcount_irq;
++extern void __weak arch_fixup_c0_irqs(void);
+
+ #endif /* _ASM_IRQ_H */
--- /dev/null
+--- a/arch/mips/kernel/cevt-r4k.c
++++ b/arch/mips/kernel/cevt-r4k.c
+@@ -21,6 +21,22 @@
+
+ #ifndef CONFIG_MIPS_MT_SMTC
+
++/*
++ * Compare interrupt can be routed and latched outside the core,
++ * so a single execution hazard barrier may not be enough to give
++ * it time to clear as seen in the Cause register. 4 time the
++ * pipeline depth seems reasonably conservative, and empirically
++ * works better in configurations with high CPU/bus clock ratios.
++ */
++
++#define compare_change_hazard() \
++ do { \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ } while (0)
++
+ static int mips_next_event(unsigned long delta,
+ struct clock_event_device *evt)
+ {
+@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long
+ cnt = read_c0_count();
+ cnt += delta;
+ write_c0_compare(cnt);
++ compare_change_hazard();
+ res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
+ return res;
+ }
--- /dev/null
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -105,6 +105,7 @@ obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
+ obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
+ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
+ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
++obj-$(CONFIG_AMAZON_WDT) += amazon_wdt.o
+
+ # PARISC Architecture
+
--- /dev/null
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -60,6 +60,21 @@ config BCM47XX
+ help
+ Support for BCM47XX based boards
+
++config AMAZON
++ bool "Amazon support (EXPERIMENTAL)"
++ depends on EXPERIMENTAL
++ select DMA_NONCOHERENT
++ select IRQ_CPU
++ select CEVT_R4K
++ select CSRC_R4K
++ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_HAS_CPU_MIPS32_R2
++ select HAVE_STD_PC_SERIAL_PORT
++ select SYS_SUPPORTS_BIG_ENDIAN
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_HAS_EARLY_PRINTK
++ select HW_HAS_PCI
++
+ config MIPS_COBALT
+ bool "Cobalt Server"
+ select CEVT_R4K
+@@ -633,6 +648,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
+
+ endchoice
+
++source "arch/mips/amazon/Kconfig"
+ source "arch/mips/alchemy/Kconfig"
+ source "arch/mips/basler/excite/Kconfig"
+ source "arch/mips/jazz/Kconfig"
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -283,6 +283,13 @@ libs-$(CONFIG_MIPS_XXS1500) += arch/mips
+ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
+
+ #
++# Infineon AMAZON
++#
++core-$(CONFIG_AMAZON) += arch/mips/amazon/
++cflags-$(CONFIG_AMAZON) += -I$(srctree)/arch/mips/include/asm/mach-amazon
++load-$(CONFIG_AMAZON) += 0xffffffff80002000
++
++#
+ # Cobalt Server
+ #
+ core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
--- /dev/null
+--- a/drivers/mtd/maps/Makefile
++++ b/drivers/mtd/maps/Makefile
+@@ -62,3 +62,4 @@ obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_
+ obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-async-flash.o
+ obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o
+ obj-$(CONFIG_MTD_VMU) += vmu-flash.o
++obj-$(CONFIG_AMAZON_MTD) += amazon.o
--- /dev/null
+--- a/drivers/net/Makefile
++++ b/drivers/net/Makefile
+@@ -272,3 +272,6 @@ obj-$(CONFIG_VIRTIO_NET) += virtio_net.o
+ obj-$(CONFIG_SFC) += sfc/
+
+ obj-$(CONFIG_WIMAX) += wimax/
++
++obj-$(CONFIG_AMAZON_NET_SW) += amazon_sw.o
++obj-$(CONFIG_ADM6996_SUPPORT) += admmod.o
--- /dev/null
+--- a/drivers/serial/Makefile
++++ b/drivers/serial/Makefile
+@@ -3,6 +3,7 @@
+ #
+
+ obj-$(CONFIG_SERIAL_CORE) += serial_core.o
++obj-$(CONFIG_AMAZON_ASC_UART) += amazon_asc.o
+ obj-$(CONFIG_SERIAL_21285) += 21285.o
+
+ # These Sparc drivers have to appear before others such as 8250
--- /dev/null
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -1090,6 +1090,9 @@ static int __xipram do_write_oneword(str
+ int retry_cnt = 0;
+
+ adr += chip->start;
++#ifdef CONFIG_AMAZON
++ adr ^= 2;
++#endif
+
+ spin_lock(chip->mutex);
+ ret = get_chip(map, chip, adr, FL_WRITING);
+@@ -1372,7 +1375,11 @@ static int __xipram do_write_buffer(stru
+ z = 0;
+ while(z < words * map_bankwidth(map)) {
+ datum = map_word_load(map, buf);
++#ifdef CONFIG_AMAZON
++ map_write(map, datum, (adr + z) ^ 0x2);
++#else
+ map_write(map, datum, adr + z);
++#endif
+
+ z += map_bankwidth(map);
+ buf += map_bankwidth(map);
+@@ -1617,6 +1624,9 @@ static int __xipram do_erase_oneblock(st
+ int ret = 0;
+
+ adr += chip->start;
++#ifdef CONFIG_AMAZON
++ adr ^= 2;
++#endif
+
+ spin_lock(chip->mutex);
+ ret = get_chip(map, chip, adr, FL_ERASING);
+@@ -1745,6 +1755,10 @@ static int do_atmel_lock(struct map_info
+ struct cfi_private *cfi = map->fldrv_priv;
+ int ret;
+
++#ifdef CONFIG_AMAZON
++ adr ^= 2;
++#endif
++
+ spin_lock(chip->mutex);
+ ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
+ if (ret)
+@@ -1781,6 +1795,10 @@ static int do_atmel_unlock(struct map_in
+ struct cfi_private *cfi = map->fldrv_priv;
+ int ret;
+
++#ifdef CONFIG_AMAZON
++ adr ^= 2;
++#endif
++
+ spin_lock(chip->mutex);
+ ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
+ if (ret)
--- /dev/null
+--- a/arch/mips/amazon/dma-core.c
++++ b/arch/mips/amazon/dma-core.c
+@@ -1387,7 +1387,7 @@ static int dma_init(void)
+ AMAZON_DMA_EMSG("cannot register device dma-core!\n");
+ return result;
+ }
+- result = request_irq(AMAZON_DMA_INT, dma_interrupt, SA_INTERRUPT, "dma-core", (void *) &dma_interrupt);
++ result = request_irq(AMAZON_DMA_INT, dma_interrupt, IRQF_DISABLED, "dma-core", (void *) &dma_interrupt);
+ if (result) {
+ AMAZON_DMA_EMSG("error, cannot get dma_irq!\n");
+ free_irq(AMAZON_DMA_INT, (void *) &dma_interrupt);
+--- a/arch/mips/amazon/interrupt.c
++++ b/arch/mips/amazon/interrupt.c
+@@ -157,7 +157,7 @@ out:
+
+ static struct irqaction cascade = {
+ .handler = no_action,
+- .flags = SA_INTERRUPT,
++ .flags = IRQF_DISABLED,
+ .name = "cascade",
+ };
+
+--- a/arch/mips/amazon/setup.c
++++ b/arch/mips/amazon/setup.c
+@@ -107,7 +107,7 @@ static void amazon_timer6_interrupt(int
+
+ static struct irqaction hrt_irqaction = {
+ .handler = amazon_timer6_interrupt,
+- .flags = SA_INTERRUPT,
++ .flags = IRQF_DISABLED,
+ .name = "hrt",
+ };
+
+--- a/drivers/atm/amazon_tpe.c
++++ b/drivers/atm/amazon_tpe.c
+@@ -2404,13 +2404,13 @@ amazon_atm_dev_t * amazon_atm_create(voi
+
+
+ // Register interrupts for insertion and extraction
+- request_irq(AMAZON_SWIE_INT, amazon_atm_swie_isr, SA_INTERRUPT, "tpe_swie", NULL);
+- request_irq(AMAZON_CBM_INT, amazon_atm_cbm_isr, SA_INTERRUPT, "tpe_cbm", NULL);
++ request_irq(AMAZON_SWIE_INT, amazon_atm_swie_isr, IRQF_DISABLED, "tpe_swie", NULL);
++ request_irq(AMAZON_CBM_INT, amazon_atm_cbm_isr, IRQF_DISABLED, "tpe_cbm", NULL);
+ #ifdef AMAZON_ATM_DEBUG
+- request_irq(AMAZON_HTU_INT , amazon_atm_htu_isr, SA_INTERRUPT, "tpe_htu", NULL);
++ request_irq(AMAZON_HTU_INT , amazon_atm_htu_isr, IRQF_DISABLED, "tpe_htu", NULL);
+ #endif
+ #ifdef AMAZON_TPE_TEST_AAL5_INT
+- request_irq(AMAZON_AAL5_INT, amazon_atm_aal5_isr, SA_INTERRUPT, "tpe_aal5", NULL);
++ request_irq(AMAZON_AAL5_INT, amazon_atm_aal5_isr, IRQF_DISABLED, "tpe_aal5", NULL);
+ #endif
+ return &g_atm_dev;
+ }
--- /dev/null
+--- a/arch/mips/amazon/prom.c
++++ b/arch/mips/amazon/prom.c
+@@ -59,9 +59,6 @@ void prom_printf(const char * fmt, ...)
+
+ void __init prom_init(void)
+ {
+- mips_machgroup = MACH_GROUP_INFINEON;
+- mips_machtype = MACH_INFINEON_AMAZON;
+-
+ strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2");
+
+ add_memory_region(0x00000000, 0x1000000, BOOT_MEM_RAM);
--- /dev/null
+--- a/arch/mips/amazon/setup.c
++++ b/arch/mips/amazon/setup.c
+@@ -36,6 +36,12 @@
+ #include <asm/amazon/irq.h>
+ #include <asm/amazon/model.h>
+
++static unsigned int r4k_offset;
++static unsigned int r4k_cur;
++
++/* required in arch/mips/kernel/kspd.c */
++unsigned long cpu_khz;
++
+ extern void prom_printf(const char * fmt, ...);
+ static void amazon_reboot_setup(void);
+
+@@ -91,35 +97,32 @@ unsigned int amazon_get_cpu_ver(void)
+ return cpu_ver;
+ }
+
+-void amazon_time_init(void)
++static inline u32 amazon_get_counter_resolution(void)
+ {
+- mips_hpt_frequency = amazon_get_cpu_hz()/2;
+- printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
++ u32 res;
++ __asm__ __volatile__(
++ ".set push\n"
++ ".set mips32r2\n"
++ ".set noreorder\n"
++ "rdhwr %0, $3\n"
++ "ehb\n"
++ ".set pop\n"
++ : "=&r" (res)
++ : /* no input */
++ : "memory");
++ instruction_hazard();
++ return res;
+ }
+
+-extern int hr_time_resolution;
+-
+-/* ISR GPTU Timer 6 for high resolution timer */
+-static void amazon_timer6_interrupt(int irq, void *dev_id)
++void __init plat_time_init(void)
+ {
+- timer_interrupt(AMAZON_TIMER6_INT, NULL);
+-}
+-
+-static struct irqaction hrt_irqaction = {
+- .handler = amazon_timer6_interrupt,
+- .flags = IRQF_DISABLED,
+- .name = "hrt",
+-};
++ mips_hpt_frequency = amazon_get_cpu_hz() / amazon_get_counter_resolution();
++ r4k_offset = mips_hpt_frequency / HZ;
++ printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
++ printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset);
+
+-/*
+- * THe CPU counter for System timer, set to HZ
+- * GPTU Timer 6 for high resolution timer, set to hr_time_resolution
+- * Also misuse this routine to print out the CPU type and clock.
+- */
+-void __init plat_timer_setup(struct irqaction *irq)
+-{
+- /* cpu counter for timer interrupts */
+- setup_irq(MIPS_CPU_TIMER_IRQ, irq);
++ r4k_cur = (read_c0_count() + r4k_offset);
++ write_c0_compare(r4k_cur);
+
+ /* enable the timer in the PMU */
+ amazon_writel(amazon_readl(AMAZON_PMU_PWDCR)| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI, AMAZON_PMU_PWDCR);
+@@ -147,7 +150,6 @@ void __init plat_mem_setup(void)
+ }
+
+ amazon_reboot_setup();
+- board_time_init = amazon_time_init;
+
+ //stop reset TPE and DFE
+ amazon_writel(0, AMAZON_RST_REQ);
+--- a/arch/mips/amazon/interrupt.c
++++ b/arch/mips/amazon/interrupt.c
+@@ -184,3 +184,10 @@ void __init arch_init_irq(void)
+ set_irq_chip(i, &amazon_irq_type);
+ }
+ }
++
++void __cpuinit arch_fixup_c0_irqs(void)
++{
++ /* FIXME: check for CPUID and only do fix for specific chips/versions */
++ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
++ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
++}
--- /dev/null
+--- a/arch/mips/amazon/pci.c
++++ b/arch/mips/amazon/pci.c
+@@ -182,7 +182,7 @@ static struct pci_controller amazon_pci_
+ .io_resource = &pci_io_resource
+ };
+
+-int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ {
+ switch (slot) {
+ case 13:
+@@ -240,7 +240,7 @@ int pcibios_plat_dev_init(struct pci_dev
+ return 0;
+ }
+
+-int amazon_pci_init(void)
++int __init amazon_pci_init(void)
+ {
+ u32 temp_buffer;
+
--- /dev/null
+--- a/arch/mips/amazon/interrupt.c
++++ b/arch/mips/amazon/interrupt.c
+@@ -177,12 +177,11 @@ void __init arch_init_irq(void)
+ setup_irq(i, &cascade);
+ }
+
+- for (i = INT_NUM_IRQ0; i <= INT_NUM_IM4_IRL31; i++) {
+- irq_desc[i].status = IRQ_DISABLED;
+- irq_desc[i].action = 0;
+- irq_desc[i].depth = 1;
+- set_irq_chip(i, &amazon_irq_type);
+- }
++ for (i = INT_NUM_IRQ0; i <= INT_NUM_IM4_IRL31; i++)
++ set_irq_chip_and_handler(i, &amazon_irq_type,
++ handle_level_irq);
++
++ set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+ }
+
+ void __cpuinit arch_fixup_c0_irqs(void)
projects / openwrt / staging / lynxis.git / commitdiff