--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "prpl Foundation Haze";
+ compatible = "prpl,haze", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ /* Aliases are required by U-Boot to patch MAC addresses */
+ ethernet0 = &dp6_syn;
+ ethernet1 = &dp4;
+ ethernet2 = &dp3;
+ ethernet3 = &dp2;
+ label-mac-device = &dp6_syn;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ wps-button {
+ label = "wps";
+ gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ reset-button {
+ label = "reset";
+ gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-state {
+ mdc-pins {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ button_pins: button-state {
+ wps-pins {
+ pins = "gpio42";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ rst-pins {
+ pins = "gpio44";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&ssphy_1 {
+ status = "okay";
+};
+
+&qusb_phy_1 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&blsp1_spi1 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <0>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "qcom,smem-part";
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
+
+ qca8075_1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_2: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_3: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_4: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ aqr113c: ethernet-phy@5 {
+ compatible ="ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ vqmmc-supply = <&l11>;
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_lan_bmp = <0x1e>; /* lan port bitmap */
+ switch_wan_bmp = <0x60>; /* wan port bitmap */
+ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
+ switch_mac_mode1 = <0xe>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+ port@1 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+ port@2 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+ port@3 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+ port@4 {
+ port_id = <6>;
+ phy_address = <8>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ ethernet-phy-ieee802.3-c45;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+/* Dummy LAN port */
+&dp1 {
+ status = "disabled";
+ phy-handle = <&qca8075_1>;
+ label = "lan4";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan3";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan2";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_4>;
+ label = "lan1";
+};
+
+&dp6_syn {
+ status = "okay";
+ qcom,mactype = <1>;
+ phy-handle = <&aqr113c>;
+ label = "wan";
+};
+
+&pcie_qmp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00020000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+};
+
+&pcie_qmp1 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
+
+ bridge@1,0 {
+ reg = <0x00010000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi@1,0 {
+ status = "okay";
+
+ /* ath11k has no DT compatible for PCI cards */
+ compatible = "pci17cb,1104";
+ reg = <0x00010000 0 0 0 0>;
+
+ qcom,ath11k-calibration-variant = "prpl-Haze";
+ };
+ };
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "prpl-Haze";
+};
projects / openwrt / staging / stintel.git / commitdiff