#define TIMER1_IRQ_IDX 0
#define TIMER10_IRQ_IDX 10
+#define TIMER_1MHz 1000000
+
static u32 usec_config;
static void __iomem *timer_reg_base;
static struct delay_timer tegra_delay_timer = {
.read_current_timer = tegra_delay_timer_read_counter_long,
- .freq = 1000000,
+ .freq = TIMER_1MHz,
};
#endif
* parent clock.
*/
if (tegra20)
- return 1000000;
+ return TIMER_1MHz;
return timer_of_rate(to);
}
}
}
- sched_clock_register(tegra_read_sched_clock, 32, 1000000);
+ sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz);
ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
- "timer_us", 1000000,
- 300, 32, clocksource_mmio_readl_up);
+ "timer_us", TIMER_1MHz, 300, 32,
+ clocksource_mmio_readl_up);
if (ret)
pr_err("failed to register clocksource: %d\n", ret);