ARM: rmobile: Add R8A7796 support

Add Kconfig entry for the R8A7796 RCar M3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index e0c27ed9c66d1bcb1d8869be9dc069bc060c2cce..4ffc40edc6ebeaf1c745df8ba728a34bf3721c49 100644 (file)
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -6,6 +6,9 @@ choice
 config R8A7795
        bool "Renesas SoC R8A7795"
 
+config R8A7796
+       bool "Renesas SoC R8A7796"
+
 endchoice
 
 choice

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 3b56fcf96f8a1772fe34a401f03cea9924947c57..2aea527bae27373b0fb247fb2d6ea4f6d5672e37 100644 (file)
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -17,5 +17,6 @@ obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
 obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
 obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
 obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o
+obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7796.o memmap-r8a7796.o
 obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
 obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o

diff --git a/arch/arm/mach-rmobile/include/mach/r8a7796.h b/arch/arm/mach-rmobile/include/mach/r8a7796.h
new file mode 100644 (file)
index 0000000..a7d1ba2
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/r8a7796.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/include/asm/arch-rcar_gen3/r8a7796.h
+ *     This file defines registers and value for r8a7796.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_R8A7796_H
+#define __ASM_ARCH_R8A7796_H
+
+#include "rcar-gen3-base.h"
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS     0x00200000
+#define MSTP1_BITS     0xFFFFFFFF
+#define MSTP2_BITS     0x340E2FDC
+#define MSTP3_BITS     0xFFFFFFDF
+#define MSTP4_BITS     0x80000184
+#define MSTP5_BITS     0xC3FFFFFF
+#define MSTP6_BITS     0xFFFFFFFF
+#define MSTP7_BITS     0xFFFFFFFF
+#define MSTP8_BITS     0x01F1FFF7
+#define MSTP9_BITS     0xFFFFFFFE
+#define MSTP10_BITS    0xFFFEFFE0
+#define MSTP11_BITS    0x000000B7
+
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000    /* either MMC0 */
+#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000    /* either MMC1 */
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
+
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE0        0xE60B0000
+
+#endif /* __ASM_ARCH_R8A7796_H */

diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index 22d97b19ab97355ac9b18044419276ee3c92659f..654349b0b3d2e8a87f6a4bedd28f4a4eba028cda 100644 (file)
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -18,6 +18,8 @@
 #include <asm/arch/r8a7794.h>
 #elif defined(CONFIG_R8A7795)
 #include <asm/arch/r8a7795.h>
+#elif defined(CONFIG_R8A7796)
+#include <asm/arch/r8a7796.h>
 #else
 #error "SOC Name not defined"
 #endif

diff --git a/arch/arm/mach-rmobile/memmap-r8a7796.c b/arch/arm/mach-rmobile/memmap-r8a7796.c
new file mode 100644 (file)
index 0000000..648743d
--- /dev/null
+++ b/arch/arm/mach-rmobile/memmap-r8a7796.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region r8a7796_mem_map[] = {
+       {
+               .virt = 0x0UL,
+               .phys = 0x0UL,
+               .size = 0xe0000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0xe0000000UL,
+               .phys = 0xe0000000UL,
+               .size = 0xe0000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* List terminator */
+               0,
+       }
+};
+
+struct mm_region *mem_map = r8a7796_mem_map;

diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index c87d31950fdf73a73960166e3eda3abd81a0dd09..304478af073269cbdb107f22a88e8fdc91eac252 100644 (file)
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -2,7 +2,7 @@
  * include/configs/rcar-gen3-common.h
  *     This file is R-Car Gen3 common configuration file.
  *
- * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -55,10 +55,31 @@
 #define CONFIG_SYS_TEXT_BASE           0x50000000
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_TEXT_BASE + 0x7fff0)
 
-#define CONFIG_SYS_SDRAM_BASE          (0x48000000)
-#define CONFIG_SYS_SDRAM_SIZE          (1024u * 1024 * 1024 - 0x08000000)
-#define CONFIG_SYS_LOAD_ADDR           (0x48080000)
-#define CONFIG_NR_DRAM_BANKS           1
+#define DRAM_RSV_SIZE                  0x08000000
+#if defined(CONFIG_R8A7795)
+#define CONFIG_NR_DRAM_BANKS           4
+#define PHYS_SDRAM_1                   (0x40000000 + DRAM_RSV_SIZE)
+#define PHYS_SDRAM_1_SIZE              (0x40000000u - DRAM_RSV_SIZE)
+#define PHYS_SDRAM_2                   0x500000000
+#define PHYS_SDRAM_2_SIZE              0x40000000u
+#define PHYS_SDRAM_3                   0x600000000
+#define PHYS_SDRAM_3_SIZE              0x40000000u
+#define PHYS_SDRAM_4                   0x700000000
+#define PHYS_SDRAM_4_SIZE              0x40000000u
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE          PHYS_SDRAM_1_SIZE
+#elif defined(CONFIG_R8A7796)
+#define CONFIG_NR_DRAM_BANKS           2
+#define PHYS_SDRAM_1                   (0x40000000 + DRAM_RSV_SIZE)
+#define PHYS_SDRAM_1_SIZE              (0x80000000u - DRAM_RSV_SIZE)
+#define PHYS_SDRAM_2                   0x0600000000
+#define PHYS_SDRAM_2_SIZE              0x80000000u
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE          PHYS_SDRAM_1_SIZE
+#endif
+#define CONFIG_SYS_LOAD_ADDR           0x48080000
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_SDRAM_SIZE
 
 #define CONFIG_SYS_MONITOR_BASE                0x00000000
 #define CONFIG_SYS_MONITOR_LEN         (256 * 1024)