fdts: stm32mp1: move FDCAN to PLL4_R

LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.

This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.

Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58

diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts
index 9df72b44446a965e02a7ffe33b060fcf9407fcb2..907940c785429fe218ffbc155eb08c7d852e431e 100644 (file)
--- a/fdts/stm32mp157a-avenger96.dts
+++ b/fdts/stm32mp157a-avenger96.dts
@@ -246,7 +246,7 @@
                CLK_UART6_HSI
                CLK_UART78_HSI
                CLK_SPDIF_PLL4P
-               CLK_FDCAN_PLL4Q
+               CLK_FDCAN_PLL4R
                CLK_SAI1_PLL3Q
                CLK_SAI2_PLL3Q
                CLK_SAI3_PLL3Q

diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts
index b17d50194e203081749d7813be2e4210b18d89c8..4ea83f7cde68dc5f4cdf9d12db0fcae1565ba624 100644 (file)
--- a/fdts/stm32mp157a-dk1.dts
+++ b/fdts/stm32mp157a-dk1.dts
@@ -266,7 +266,7 @@
                CLK_UART6_HSI
                CLK_UART78_HSI
                CLK_SPDIF_PLL4P
-               CLK_FDCAN_PLL4Q
+               CLK_FDCAN_PLL4R
                CLK_SAI1_PLL3Q
                CLK_SAI2_PLL3Q
                CLK_SAI3_PLL3Q

diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index ed55725b02b4bfa5eafc8f3f5b153dd908345937..7794925523aec7c99454ca968e534310fae41b59 100644 (file)
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -272,7 +272,7 @@
                CLK_UART6_HSI
                CLK_UART78_HSI
                CLK_SPDIF_PLL4P
-               CLK_FDCAN_PLL4Q
+               CLK_FDCAN_PLL4R
                CLK_SAI1_PLL3Q
                CLK_SAI2_PLL3Q
                CLK_SAI3_PLL3Q