bpf: interpreter support BPF_ALU | BPF_ARSH

This patch implements interpreting BPF_ALU | BPF_ARSH. Do arithmetic right
shift on low 32-bit sub-register, and zero the high 32 bits.

Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>

diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c
index 628b3970a49b3f86ae87b37e85cabef43d35c15d..a5b223ef71310ba34243ea2ba70ed0d5b7987e67 100644 (file)
--- a/kernel/bpf/core.c
+++ b/kernel/bpf/core.c
@@ -933,32 +933,34 @@ EXPORT_SYMBOL_GPL(__bpf_call_base);
 #define BPF_INSN_MAP(INSN_2, INSN_3)           \
        /* 32 bit ALU operations. */            \
        /*   Register based. */                 \
-       INSN_3(ALU, ADD, X),                    \
-       INSN_3(ALU, SUB, X),                    \
-       INSN_3(ALU, AND, X),                    \
-       INSN_3(ALU, OR,  X),                    \
-       INSN_3(ALU, LSH, X),                    \
-       INSN_3(ALU, RSH, X),                    \
-       INSN_3(ALU, XOR, X),                    \
-       INSN_3(ALU, MUL, X),                    \
-       INSN_3(ALU, MOV, X),                    \
-       INSN_3(ALU, DIV, X),                    \
-       INSN_3(ALU, MOD, X),                    \
+       INSN_3(ALU, ADD,  X),                   \
+       INSN_3(ALU, SUB,  X),                   \
+       INSN_3(ALU, AND,  X),                   \
+       INSN_3(ALU, OR,   X),                   \
+       INSN_3(ALU, LSH,  X),                   \
+       INSN_3(ALU, RSH,  X),                   \
+       INSN_3(ALU, XOR,  X),                   \
+       INSN_3(ALU, MUL,  X),                   \
+       INSN_3(ALU, MOV,  X),                   \
+       INSN_3(ALU, ARSH, X),                   \
+       INSN_3(ALU, DIV,  X),                   \
+       INSN_3(ALU, MOD,  X),                   \
        INSN_2(ALU, NEG),                       \
        INSN_3(ALU, END, TO_BE),                \
        INSN_3(ALU, END, TO_LE),                \
        /*   Immediate based. */                \
-       INSN_3(ALU, ADD, K),                    \
-       INSN_3(ALU, SUB, K),                    \
-       INSN_3(ALU, AND, K),                    \
-       INSN_3(ALU, OR,  K),                    \
-       INSN_3(ALU, LSH, K),                    \
-       INSN_3(ALU, RSH, K),                    \
-       INSN_3(ALU, XOR, K),                    \
-       INSN_3(ALU, MUL, K),                    \
-       INSN_3(ALU, MOV, K),                    \
-       INSN_3(ALU, DIV, K),                    \
-       INSN_3(ALU, MOD, K),                    \
+       INSN_3(ALU, ADD,  K),                   \
+       INSN_3(ALU, SUB,  K),                   \
+       INSN_3(ALU, AND,  K),                   \
+       INSN_3(ALU, OR,   K),                   \
+       INSN_3(ALU, LSH,  K),                   \
+       INSN_3(ALU, RSH,  K),                   \
+       INSN_3(ALU, XOR,  K),                   \
+       INSN_3(ALU, MUL,  K),                   \
+       INSN_3(ALU, MOV,  K),                   \
+       INSN_3(ALU, ARSH, K),                   \
+       INSN_3(ALU, DIV,  K),                   \
+       INSN_3(ALU, MOD,  K),                   \
        /* 64 bit ALU operations. */            \
        /*   Register based. */                 \
        INSN_3(ALU64, ADD,  X),                 \
@@ -1137,6 +1139,12 @@ select_insn:
                DST = (u64) (u32) insn[0].imm | ((u64) (u32) insn[1].imm) << 32;
                insn++;
                CONT;
+       ALU_ARSH_X:
+               DST = (u64) (u32) ((*(s32 *) &DST) >> SRC);
+               CONT;
+       ALU_ARSH_K:
+               DST = (u64) (u32) ((*(s32 *) &DST) >> IMM);
+               CONT;
        ALU64_ARSH_X:
                (*(s64 *) &DST) >>= SRC;
                CONT;