kernel: backports: mt7530: fix TRGMII mode after reset

Backport upstream patch that fixes TRGMII mode now that mt7530 is
actually resetting the switch on ramips devices.

Patches apply to both Linux 5.4 and 5.10, since TRGMII is broken on both.

Fixes: 69551a244292 ("ramips: manage low reset lines")
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
(cherry picked from commit 680f91d0e5444d58815af03bf41c12592438f9d8)

diff --git a/target/linux/generic/backport-5.4/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch b/target/linux/generic/backport-5.4/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch
new file mode 100644 (file)
index 0000000..d48d797
--- /dev/null
+++ b/target/linux/generic/backport-5.4/780-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch
@@ -0,0 +1,84 @@
+From c3b8e07909dbe67b0d580416c1a5257643a73be7 Mon Sep 17 00:00:00 2001
+From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
+Date: Fri, 12 Mar 2021 00:07:03 -0800
+Subject: [PATCH] net: dsa: mt7530: setup core clock even in TRGMII mode
+
+A recent change to MIPS ralink reset logic made it so mt7530 actually
+resets the switch on platforms such as mt7621 (where bit 2 is the reset
+line for the switch). That exposed an issue where the switch would not
+function properly in TRGMII mode after a reset.
+
+Reconfigure core clock in TRGMII mode to fix the issue.
+
+Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.
+
+Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
+Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++---------------------
+ 1 file changed, 25 insertions(+), 27 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -427,34 +427,32 @@ mt7530_pad_clk_setup(struct dsa_switch *
+                            TD_DM_DRVP(8) | TD_DM_DRVN(8));
+ 
+       /* Setup core clock for MT7530 */
+-      if (!trgint) {
+-              /* Disable MT7530 core clock */
+-              core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
+-
+-              /* Disable PLL, since phy_device has not yet been created
+-               * provided for phy_[read,write]_mmd_indirect is called, we
+-               * provide our own core_write_mmd_indirect to complete this
+-               * function.
+-               */
+-              core_write_mmd_indirect(priv,
+-                                      CORE_GSWPLL_GRP1,
+-                                      MDIO_MMD_VEND2,
+-                                      0);
+-
+-              /* Set core clock into 500Mhz */
+-              core_write(priv, CORE_GSWPLL_GRP2,
+-                         RG_GSWPLL_POSDIV_500M(1) |
+-                         RG_GSWPLL_FBKDIV_500M(25));
+-
+-              /* Enable PLL */
+-              core_write(priv, CORE_GSWPLL_GRP1,
+-                         RG_GSWPLL_EN_PRE |
+-                         RG_GSWPLL_POSDIV_200M(2) |
+-                         RG_GSWPLL_FBKDIV_200M(32));
+-
+-              /* Enable MT7530 core clock */
+-              core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
+-      }
++      /* Disable MT7530 core clock */
++      core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
++
++      /* Disable PLL, since phy_device has not yet been created
++       * provided for phy_[read,write]_mmd_indirect is called, we
++       * provide our own core_write_mmd_indirect to complete this
++       * function.
++       */
++      core_write_mmd_indirect(priv,
++                              CORE_GSWPLL_GRP1,
++                              MDIO_MMD_VEND2,
++                              0);
++
++      /* Set core clock into 500Mhz */
++      core_write(priv, CORE_GSWPLL_GRP2,
++                 RG_GSWPLL_POSDIV_500M(1) |
++                 RG_GSWPLL_FBKDIV_500M(25));
++
++      /* Enable PLL */
++      core_write(priv, CORE_GSWPLL_GRP1,
++                 RG_GSWPLL_EN_PRE |
++                 RG_GSWPLL_POSDIV_200M(2) |
++                 RG_GSWPLL_FBKDIV_200M(32));
++
++      /* Enable MT7530 core clock */
++      core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
+ 
+       /* Setup the MT7530 TRGMII Tx Clock */
+       core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);

diff --git a/target/linux/generic/pending-5.4/761-net-dsa-mt7530-Support-EEE-features.patch b/target/linux/generic/pending-5.4/761-net-dsa-mt7530-Support-EEE-features.patch
index 1822647ff17b6cd6ad16b59293f20e3acc7baad2..b9ca691f6f1170d4ff909365c13531982d6c8e69 100644 (file)
--- a/target/linux/generic/pending-5.4/761-net-dsa-mt7530-Support-EEE-features.patch
+++ b/target/linux/generic/pending-5.4/761-net-dsa-mt7530-Support-EEE-features.patch
@@ -9,7 +9,7 @@ Content-Transfer-Encoding: 8bit
 Signed-off-by: René van Dorst <opensource@vdorst.com>
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -1419,9 +1419,13 @@ static void mt7530_phylink_mac_config(st
+@@ -1417,9 +1417,13 @@ static void mt7530_phylink_mac_config(st
        switch (state->speed) {
        case SPEED_1000:
                mcr_new |= PMCR_FORCE_SPEED_1000;
@@ -23,7 +23,7 @@ Signed-off-by: René van Dorst <opensource@vdorst.com>
                break;
        }
        if (state->duplex == DUPLEX_FULL) {
-@@ -1557,6 +1561,54 @@ mt7530_phylink_mac_link_state(struct dsa
+@@ -1555,6 +1559,54 @@ mt7530_phylink_mac_link_state(struct dsa
        return 1;
  }
  
@@ -78,7 +78,7 @@ Signed-off-by: René van Dorst <opensource@vdorst.com>
  static const struct dsa_switch_ops mt7530_switch_ops = {
        .get_tag_protocol       = mtk_get_tag_protocol,
        .setup                  = mt7530_setup,
-@@ -1584,6 +1636,8 @@ static const struct dsa_switch_ops mt753
+@@ -1582,6 +1634,8 @@ static const struct dsa_switch_ops mt753
        .phylink_mac_config     = mt7530_phylink_mac_config,
        .phylink_mac_link_down  = mt7530_phylink_mac_link_down,
        .phylink_mac_link_up    = mt7530_phylink_mac_link_up,