drm/amd/display: Use DCN functions instead of DCE

[WHY]
DCN code should make as few references to DCE as possible

[HOW]
Copy DCE110 implementation of find_first_free_match_stream_enc_for_link
into DCN10

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 749fb44cfc4bfb8e4390aaa7b9b97f08fb354dec..bfddd51294a267971f8e1bb1372191205b9d431d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1231,6 +1231,38 @@ static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plan
        return result;
 }
 
+struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
+               struct resource_context *res_ctx,
+               const struct resource_pool *pool,
+               struct dc_stream_state *stream)
+{
+       int i;
+       int j = -1;
+       struct dc_link *link = stream->link;
+
+       for (i = 0; i < pool->stream_enc_count; i++) {
+               if (!res_ctx->is_stream_enc_acquired[i] &&
+                               pool->stream_enc[i]) {
+                       /* Store first available for MST second display
+                        * in daisy chain use case
+                        */
+                       j = i;
+                       if (pool->stream_enc[i]->id ==
+                                       link->link_enc->preferred_engine)
+                               return pool->stream_enc[i];
+               }
+       }
+
+       /*
+        * For CZ and later, we can allow DIG FE and BE to differ for all display types
+        */
+
+       if (j >= 0)
+               return pool->stream_enc[j];
+
+       return NULL;
+}
+
 static const struct dc_cap_funcs cap_funcs = {
        .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
 };
@@ -1244,7 +1276,7 @@ static const struct resource_funcs dcn10_res_pool_funcs = {
        .validate_global = dcn10_validate_global,
        .add_stream_to_ctx = dcn10_add_stream_to_ctx,
        .get_default_swizzle_mode = dcn10_get_default_swizzle_mode,
-       .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
+       .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
 };
 
 static uint32_t read_pipe_fuses(struct dc_context *ctx)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
index 999c684a0b3671b3049bb4b117c02834b2a72d5f..633025ccb87007aefbcdcb0a7ba9524c4dc3760f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
@@ -42,6 +42,11 @@ struct resource_pool *dcn10_create_resource_pool(
                const struct dc_init_data *init_data,
                struct dc *dc);
 
+struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
+               struct resource_context *res_ctx,
+               const struct resource_pool *pool,
+               struct dc_stream_state *stream);
+
 
 #endif /* __DC_RESOURCE_DCN10_H__ */