--- /dev/null
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -1423,6 +1423,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7623a-unielec-u7623-02-emmc.dtb \
+ mt7622-bananapi-bpi-r64.dtb \
+ mt7622-linksys-e8450-ubi.dtb \
++ mt7622-tplink-tl-xdr3230-v1.dtb \
+ mt7622-ubnt-unifi-6-lr.dtb \
+ mt7622-ubnt-unifi-6-lr-v3.dtb \
+ mt7623n-bananapi-bpi-r2.dtb \
+--- /dev/null
++++ b/arch/arm/dts/mt7622-tplink-tl-xdr3230-v1.dts
+@@ -0,0 +1,165 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2019 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ */
++
++/dts-v1/;
++#include "mt7622.dtsi"
++#include "mt7622-u-boot.dtsi"
++
++/ {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ model = "TP-Link TL-XDR3230 v1";
++ compatible = "tplink,tl-xdr3230-v1", "mediatek,mt7622";
++
++ chosen {
++ stdout-path = &uart0;
++ tick-timer = &timer0;
++ };
++
++ aliases {
++ spi0 = &snor;
++ };
++
++ gpio-leds {
++ compatible = "gpio-leds";
++ led_status: green_status {
++ label = "green:status";
++ gpios = <&gpio 89 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ };
++
++ red_status {
++ label = "red:status";
++ gpios = <&gpio 90 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ memory@40000000 {
++ device_type = "memory";
++ reg = <0x40000000 0x10000000>;
++ };
++
++ reg_1p8v: regulator-1p8v {
++ compatible = "regulator-fixed";
++ regulator-name = "fixed-1.8V";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ reg_3p3v: regulator-3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "fixed-3.3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ reg_5v: regulator-5v {
++ compatible = "regulator-fixed";
++ regulator-name = "fixed-5V";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
++ status = "okay";
++
++ pcie@0,0 {
++ status = "okay";
++ };
++
++ pcie@1,0 {
++ status = "okay";
++ };
++};
++
++&pinctrl {
++ eth_pins: eth-pins {
++ mux {
++ function = "eth";
++ groups = "mdc_mdio", "rgmii_via_gmac2";
++ };
++ };
++
++ pcie0_pins: pcie0-pins {
++ mux {
++ function = "pcie";
++ groups = "pcie0_pad_perst",
++ "pcie0_1_waken",
++ "pcie0_1_clkreq";
++ };
++ };
++
++ pcie1_pins: pcie1-pins {
++ mux {
++ function = "pcie";
++ groups = "pcie1_pad_perst",
++ "pcie1_0_waken",
++ "pcie1_0_clkreq";
++ };
++ };
++
++ snor_pins: snor-pins {
++ mux {
++ function = "flash";
++ groups = "spi_nor";
++ };
++ };
++
++ snfi_pins: snfi-pins {
++ mux {
++ function = "flash";
++ groups = "snfi";
++ };
++ };
++
++ uart0_pins: uart0 {
++ mux {
++ function = "uart";
++ groups = "uart0_0_tx_rx" ;
++ };
++ };
++
++ watchdog_pins: watchdog-default {
++ mux {
++ function = "watchdog";
++ groups = "watchdog";
++ };
++ };
++};
++
++&snor {
++ pinctrl-names = "default";
++ pinctrl-0 = <&snor_pins>;
++ status = "okay";
++
++ spi-flash@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-tx-bus-width = <4>;
++ spi-rx-bus-width = <4>;
++ };
++};
++
++&uart0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0_pins>;
++ status = "okay";
++};
++
++&watchdog {
++ pinctrl-names = "default";
++ pinctrl-0 = <&watchdog_pins>;
++ status = "okay";
++};
+--- /dev/null
++++ b/configs/mt7622_tplink_tl-xdr3230-v1_defconfig
+@@ -0,0 +1,89 @@
++CONFIG_ARM=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_ENV_SIZE=0x4000
++CONFIG_ENV_OFFSET=0xc0000
++CONFIG_DM_GPIO=y
++CONFIG_DEFAULT_DEVICE_TREE="mt7622-tplink-tl-xdr3230-v1"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_RESET_BUTTON_SETTLE_DELAY=400
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_DEBUG_UART_BASE=0x11002000
++CONFIG_DEBUG_UART_CLOCK=25000000
++CONFIG_SYS_LOAD_ADDR=0x40080000
++CONFIG_DEBUG_UART=y
++CONFIG_FIT=y
++# CONFIG_LEGACY_IMAGE_FORMAT is not set
++CONFIG_BOOTDELAY=0
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_DEFAULT_FDT_FILE="mt7622-tplink-tl-xdr3230-v1"
++CONFIG_LOGLEVEL=7
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_LOG=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_PROMPT="MT7622> "
++# CONFIG_BOOTM_PLAN9 is not set
++# CONFIG_BOOTM_RTEMS is not set
++# CONFIG_BOOTM_VXWORKS is not set
++CONFIG_CMD_BOOTMENU=y
++# CONFIG_CMD_ELF is not set
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_ENV_FLAGS=y
++# CONFIG_CMD_UNLZ4 is not set
++CONFIG_CMD_GPIO=y
++CONFIG_RANDOM_UUID=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_UUID=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_SMC=y
++CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),256k(fip),64k(u-boot-env),64k(factory),-(firmware)"
++CONFIG_ENV_IS_IN_MTD=y
++CONFIG_ENV_MTD_NAME="nor0"
++CONFIG_ENV_SIZE_REDUND=0x4000
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_DEFAULT_ENV_FILE="tplink_tl-xdr3230-v1_env"
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_VERSION_VARIABLE=y
++# CONFIG_NET is not set
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_CLK=y
++CONFIG_GPIO_HOG=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++# CONFIG_MMC is not set
++CONFIG_MTD=y
++CONFIG_DM_MTD=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_SFDP_SUPPORT=y
++CONFIG_SPI_FLASH_EON=y
++CONFIG_SPI_FLASH_GIGADEVICE=y
++CONFIG_SPI_FLASH_MACRONIX=y
++CONFIG_SPI_FLASH_SPANSION=y
++CONFIG_SPI_FLASH_XMC=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_DM_ETH_PHY=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7622=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SNOR=y
++CONFIG_REGEX=y
++CONFIG_HEXDUMP=y
+--- /dev/null
++++ b/tplink_tl-xdr3230-v1_env
+@@ -0,0 +1,5 @@
++loadaddr=0x48000000
++bootcmd=led green:status on; run nor_read_production && bootm $loadaddr
++bootdelay=1
++recovery=led red:status on ; loady $loadaddr && bootm $loadaddr
++nor_read_production=mtd read firmware $loadaddr 0 0x1000 && imsz $loadaddr image_size && mtd read firmware $loadaddr 0 $image_size