rockchip: Migrate to new interfaces

- Migrate to new GIC interfaces.
- Migrate to bl31_early_platform_setup2().
- Use bl31_warm_entrypoint() instead of psci_entrypoint().
- Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE.
- Update Makefile paths.
- Remove references to removed build options.
- Use private definition of bl31_params_t.

Change-Id: I860341594b5c868b2fcaa59d23957ee718472ef1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

diff --git a/plat/rockchip/common/aarch64/platform_common.c b/plat/rockchip/common/aarch64/platform_common.c
index 25eab43469841b979d7c022c61c227d52326813e..9a74314c94de0a0ec46e8f558e593531c308938b 100644 (file)
--- a/plat/rockchip/common/aarch64/platform_common.c
+++ b/plat/rockchip/common/aarch64/platform_common.c
@@ -5,7 +5,6 @@
  */
 
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <bl_common.h>
 #include <cci.h>
 #include <debug.h>

diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index e5ee68f141aff54514cdb480d11e28446218bea7..b8ec8c1cb2d0ab119fe5af64266b6a5749ca072e 100644 (file)
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <arm_gic.h>
 #include <assert.h>
 #include <bl_common.h>
 #include <console.h>
@@ -61,10 +60,12 @@ void params_early_setup(void *plat_param_from_bl2)
  * BL2 has flushed this information to memory, so we are guaranteed to pick up
  * good data.
  ******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
-                              void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+                               u_register_t arg2, u_register_t arg3)
 {
        static console_16550_t console;
+       struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
+       void *plat_params_from_bl2 = (void *) arg1;
 
        params_early_setup(plat_params_from_bl2);
 
@@ -82,13 +83,13 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
        VERBOSE("bl31_setup\n");
 
        /* Passing a NULL context is a critical programming error */
-       assert(from_bl2);
+       assert(arg_from_bl2);
 
-       assert(from_bl2->h.type == PARAM_BL31);
-       assert(from_bl2->h.version >= VERSION_1);
+       assert(arg_from_bl2->h.type == PARAM_BL31);
+       assert(arg_from_bl2->h.version >= VERSION_1);
 
-       bl32_ep_info = *from_bl2->bl32_ep_info;
-       bl33_ep_info = *from_bl2->bl33_ep_info;
+       bl32_ep_info = *arg_from_bl2->bl32_ep_info;
+       bl33_ep_info = *arg_from_bl2->bl33_ep_info;
 }
 
 /*******************************************************************************

diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 545677352f099ba64417bcb6ae2f03d84aeab7c2..e1e4f33c51a13e3447bff2d1fd8d5b25251420d9 100644 (file)
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -28,6 +28,14 @@ extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end;
 extern uint32_t __sram_incbin_start, __sram_incbin_end;
 extern uint32_t __sram_incbin_real_end;
 
+struct rockchip_bl31_params {
+       param_header_t h;
+       image_info_t *bl31_image_info;
+       entry_point_info_t *bl32_ep_info;
+       image_info_t *bl32_image_info;
+       entry_point_info_t *bl33_ep_info;
+       image_info_t *bl33_image_info;
+};
 
 /******************************************************************************
  * The register have write-mask bits, it is mean, if you want to set the bits,

diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
index 3dac01328c956a60d48e21361d41f23db8ab5489..a7ba83e5ac512218b7c574eaf391e4181dc0d280 100644 (file)
--- a/plat/rockchip/common/params_setup.c
+++ b/plat/rockchip/common/params_setup.c
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <arm_gic.h>
 #include <assert.h>
 #include <bl_common.h>
 #include <console.h>

diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
index 991fe6cf866144fd5a4b723762462e14c0f27b32..d91ee0e2fa86bb85f5bbe74c3dc40fdfa80149fd 100644 (file)
--- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
+++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
@@ -48,5 +48,5 @@ ddr_resume:
 #endif
        bl      sram_restore
 sys_resume:
-       bl      psci_entrypoint
+       bl      bl31_warm_entrypoint
 endfunc pmu_cpuson_entrypoint

diff --git a/plat/rockchip/common/rockchip_gicv2.c b/plat/rockchip/common/rockchip_gicv2.c
index afdc6aa7d72126d4ae48ae644b4b9b0f18aeca60..4705042baac7d1555b8b8f3553d30d8e0802bbee 100644 (file)
--- a/plat/rockchip/common/rockchip_gicv2.c
+++ b/plat/rockchip/common/rockchip_gicv2.c
@@ -6,6 +6,7 @@
 
 #include <bl_common.h>
 #include <gicv2.h>
+#include <interrupt_props.h>
 #include <platform_def.h>
 #include <utils.h>
 
@@ -23,8 +24,8 @@
  * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
  * interrupts.
  *****************************************************************************/
-const unsigned int g0_interrupt_array[] = {
-       PLAT_RK_G1S_IRQS,
+static const interrupt_prop_t g0_interrupt_props[] = {
+       PLAT_RK_GICV2_G1S_IRQS
 };
 
 /*
@@ -35,8 +36,8 @@ const unsigned int g0_interrupt_array[] = {
 gicv2_driver_data_t rockchip_gic_data = {
        .gicd_base = PLAT_RK_GICD_BASE,
        .gicc_base = PLAT_RK_GICC_BASE,
-       .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
-       .g0_interrupt_array = g0_interrupt_array,
+       .interrupt_props = g0_interrupt_props,
+       .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
 };
 
 /******************************************************************************

diff --git a/plat/rockchip/common/rockchip_gicv3.c b/plat/rockchip/common/rockchip_gicv3.c
index 0500da60fb652b93f1d78d2c78bb705bb168df16..efbf1d167c133cd2ceb222e857ccf3949ec934e5 100644 (file)
--- a/plat/rockchip/common/rockchip_gicv3.c
+++ b/plat/rockchip/common/rockchip_gicv3.c
@@ -6,6 +6,7 @@
 
 #include <bl_common.h>
 #include <gicv3.h>
+#include <interrupt_props.h>
 #include <platform.h>
 #include <platform_def.h>
 #include <utils.h>
@@ -23,14 +24,9 @@
 /* The GICv3 driver only needs to be initialized in EL3 */
 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
 
-/* Array of Group1 secure interrupts to be configured by the gic driver */
-const unsigned int g1s_interrupt_array[] = {
-       PLAT_RK_G1S_IRQS
-};
-
-/* Array of Group0 interrupts to be configured by the gic driver */
-const unsigned int g0_interrupt_array[] = {
-       PLAT_RK_G0_IRQS
+static const interrupt_prop_t g01s_interrupt_props[] = {
+       PLAT_RK_GICV3_G0_IRQS,
+       PLAT_RK_GICV3_G1S_IRQS
 };
 
 static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr)
@@ -41,10 +37,8 @@ static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr)
 const gicv3_driver_data_t rockchip_gic_data = {
        .gicd_base = PLAT_RK_GICD_BASE,
        .gicr_base = PLAT_RK_GICR_BASE,
-       .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
-       .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
-       .g0_interrupt_array = g0_interrupt_array,
-       .g1s_interrupt_array = g1s_interrupt_array,
+       .interrupt_props = g01s_interrupt_props,
+       .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
        .rdistif_num = PLATFORM_CORE_COUNT,
        .rdistif_base_addrs = rdistif_base_addrs,
        .mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos,

diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h
index 56d51ee303ffc0df1cd1ba220c765e82577800b2..9b20b41d3fafbaa632a7e9de4449a01b59bba2fb 100644 (file)
--- a/plat/rockchip/rk3328/include/platform_def.h
+++ b/plat/rockchip/rk3328/include/platform_def.h
@@ -11,8 +11,6 @@
 #include <common_def.h>
 #include <rk3328_def.h>
 
-#define DEBUG_XLAT_TABLE 0
-
 /*******************************************************************************
  * Platform binary types for linking
  ******************************************************************************/
@@ -24,9 +22,7 @@
  ******************************************************************************/
 
 /* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif defined(IMAGE_BL1)
+#if defined(IMAGE_BL1)
 #define PLATFORM_STACK_SIZE 0x440
 #elif defined(IMAGE_BL2)
 #define PLATFORM_STACK_SIZE 0x400
@@ -85,7 +81,8 @@
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
-#define ADDR_SPACE_SIZE                (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE   (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE    (1ULL << 32)
 #define MAX_XLAT_TABLES                9
 #define MAX_MMAP_REGIONS       33
 
@@ -107,13 +104,6 @@
 #define PLAT_RK_GICD_BASE      RK3328_GICD_BASE
 #define PLAT_RK_GICC_BASE      RK3328_GICC_BASE
 
-/*
- * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define PLAT_RK_G1S_IRQS       RK_G1S_IRQS
-
 #define PLAT_RK_UART_BASE      RK3328_UART2_BASE
 #define PLAT_RK_UART_CLOCK     RK3328_UART_CLOCK
 #define PLAT_RK_UART_BAUDRATE  RK3328_BAUDRATE

diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index f0fd36f9b47a70dcac74c9732bd58c2ee8157025..560cccae67b8849741d0aba891e32de1065f2bb6 100644 (file)
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -27,13 +27,14 @@ RK_GIC_SOURCES              :=      drivers/arm/gic/common/gic_common.c             \
                                plat/common/plat_gicv2.c                        \
                                ${RK_PLAT}/common/rockchip_gicv2.c
 
-PLAT_BL_COMMON_SOURCES :=      lib/aarch64/xlat_tables.c                       \
-                               plat/common/aarch64/plat_psci_common.c
+PLAT_BL_COMMON_SOURCES :=      lib/xlat_tables/aarch64/xlat_tables.c           \
+                               lib/xlat_tables/xlat_tables_common.c            \
+                               plat/common/plat_psci_common.c
 
 BL31_SOURCES           +=      ${RK_GIC_SOURCES}                               \
                                drivers/arm/cci/cci.c                           \
-                               drivers/console/console.S                       \
-                               drivers/ti/uart/16550_console.S                 \
+                               drivers/console/aarch64/console.S               \
+                               drivers/ti/uart/aarch64/16550_console.S         \
                                drivers/delay_timer/delay_timer.c               \
                                drivers/delay_timer/generic_delay_timer.c       \
                                lib/cpus/aarch64/aem_generic.S                  \
@@ -48,7 +49,6 @@ BL31_SOURCES          +=      ${RK_GIC_SOURCES}                               \
                                ${RK_PLAT_SOC}/drivers/pmu/pmu.c                \
                                ${RK_PLAT_SOC}/drivers/soc/soc.c
 
-ENABLE_PLAT_COMPAT     :=      0
 MULTI_CONSOLE_API      :=      1
 
 include lib/coreboot/coreboot.mk

diff --git a/plat/rockchip/rk3328/rk3328_def.h b/plat/rockchip/rk3328/rk3328_def.h
index 062c9cc424437b414f3c7152427eb0274a021e98..035fcb64f4be1d6d66acc1d2b6ea42bc7a4fcc3c 100644 (file)
--- a/plat/rockchip/rk3328/rk3328_def.h
+++ b/plat/rockchip/rk3328/rk3328_def.h
@@ -135,7 +135,11 @@
  * terminology. On a GICv2 system or mode, the lists will be merged and treated
  * as Group 0 interrupts.
  */
-#define RK_G1S_IRQS            RK_IRQ_SEC_PHY_TIMER, RK_IRQ_SEC_SGI_6
+#define PLAT_RK_GICV2_G1S_IRQS                                         \
+       INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,  \
+                      GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL),          \
+       INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,      \
+                      GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL)
 
 #define SHARE_MEM_BASE          0x100000/* [1MB, 1MB+60K]*/
 #define SHARE_MEM_PAGE_NUM      15

diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h
index d9a80a7af020b11cf5c0d76ff1d15753539a06dc..4083938ef1d6a4a158c0568c35680d1d71c2b362 100644 (file)
--- a/plat/rockchip/rk3368/include/platform_def.h
+++ b/plat/rockchip/rk3368/include/platform_def.h
@@ -12,8 +12,6 @@
 #include <rk3368_def.h>
 #include <utils_def.h>
 
-#define DEBUG_XLAT_TABLE 0
-
 /*******************************************************************************
  * Platform binary types for linking
  ******************************************************************************/
@@ -25,9 +23,7 @@
  ******************************************************************************/
 
 /* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif defined(IMAGE_BL1)
+#if defined(IMAGE_BL1)
 #define PLATFORM_STACK_SIZE 0x440
 #elif defined(IMAGE_BL2)
 #define PLATFORM_STACK_SIZE 0x400
@@ -86,7 +82,8 @@
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
-#define ADDR_SPACE_SIZE                (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE   (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE    (1ULL << 32)
 #define MAX_XLAT_TABLES                8
 #define MAX_MMAP_REGIONS       16
 
@@ -108,13 +105,6 @@
 #define PLAT_RK_GICD_BASE      RK3368_GICD_BASE
 #define PLAT_RK_GICC_BASE      RK3368_GICC_BASE
 
-/*
- * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define PLAT_RK_G1S_IRQS       RK_G1S_IRQS
-
 #define PLAT_RK_UART_BASE      RK3368_UART2_BASE
 #define PLAT_RK_UART_CLOCK     RK3368_UART_CLOCK
 #define PLAT_RK_UART_BAUDRATE  RK3368_BAUDRATE

diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk
index 7ecb21ad5ed6070145e3ddc0c604e785595bd6a2..050a2c423ce390ca9ef544ff5664932e71af1459 100644 (file)
--- a/plat/rockchip/rk3368/platform.mk
+++ b/plat/rockchip/rk3368/platform.mk
@@ -48,7 +48,6 @@ BL31_SOURCES          +=      ${RK_GIC_SOURCES}                               \
                                ${RK_PLAT_SOC}/drivers/soc/soc.c                \
                                ${RK_PLAT_SOC}/drivers/ddr/ddr_rk3368.c         \
 
-ENABLE_PLAT_COMPAT     :=      0
 MULTI_CONSOLE_API      :=      1
 
 include lib/coreboot/coreboot.mk

diff --git a/plat/rockchip/rk3368/rk3368_def.h b/plat/rockchip/rk3368/rk3368_def.h
index 7cb82da212138e0c62b21ecb490549447def847e..9ebe3be06f8f8aa7301e30002ba25cb6ef8e205e 100644 (file)
--- a/plat/rockchip/rk3368/rk3368_def.h
+++ b/plat/rockchip/rk3368/rk3368_def.h
@@ -100,6 +100,8 @@
  * terminology. On a GICv2 system or mode, the lists will be merged and treated
  * as Group 0 interrupts.
  */
-#define RK_G1S_IRQS            (RK_IRQ_SEC_PHY_TIMER)
+#define PLAT_RK_GICV2_G1S_IRQS                                         \
+       INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,  \
+                      GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL)
 
 #endif /* __PLAT_DEF_H__ */

diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h
index 26204a11634cb3ae87adad1c5bf2a1823f301a95..cb798fbcbf05d07043076ce9eb68e167c1b9a836 100644 (file)
--- a/plat/rockchip/rk3399/include/platform_def.h
+++ b/plat/rockchip/rk3399/include/platform_def.h
@@ -13,8 +13,6 @@
 #include <rk3399_def.h>
 #include <utils_def.h>
 
-#define DEBUG_XLAT_TABLE 0
-
 /*******************************************************************************
  * Platform binary types for linking
  ******************************************************************************/
@@ -26,9 +24,7 @@
  ******************************************************************************/
 
 /* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif defined(IMAGE_BL1)
+#if defined(IMAGE_BL1)
 #define PLATFORM_STACK_SIZE 0x440
 #elif defined(IMAGE_BL2)
 #define PLATFORM_STACK_SIZE 0x400
@@ -69,7 +65,8 @@
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
-#define ADDR_SPACE_SIZE                (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE   (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE    (1ULL << 32)
 #define MAX_XLAT_TABLES                20
 #define MAX_MMAP_REGIONS       25
 
@@ -92,14 +89,6 @@
 #define PLAT_RK_GICR_BASE      BASE_GICR_BASE
 #define PLAT_RK_GICC_BASE      0
 
-/*
- * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define PLAT_RK_G1S_IRQS               RK3399_G1S_IRQS
-#define PLAT_RK_G0_IRQS                        RK3399_G0_IRQS
-
 #define PLAT_RK_UART_BASE              UART2_BASE
 #define PLAT_RK_UART_CLOCK             RK3399_UART_CLOCK
 #define PLAT_RK_UART_BAUDRATE          RK3399_BAUDRATE

diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index fc386f05a3a844021383612e26dea0800e707572..91204192886c36d740e5189e34d162b031d0b4ba 100644 (file)
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -65,7 +65,6 @@ BL31_SOURCES  +=      ${RK_GIC_SOURCES}                               \
                        ${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c  \
                        ${RK_PLAT_SOC}/drivers/dram/suspend.c
 
-ENABLE_PLAT_COMPAT     :=      0
 MULTI_CONSOLE_API      :=      1
 
 include lib/coreboot/coreboot.mk

diff --git a/plat/rockchip/rk3399/rk3399_def.h b/plat/rockchip/rk3399/rk3399_def.h
index 9fc0809d2552a4186713a4d7292d6759fc909a79..32e439eb981900f2a84c4d14d5736528c5960251 100644 (file)
--- a/plat/rockchip/rk3399/rk3399_def.h
+++ b/plat/rockchip/rk3399/rk3399_def.h
@@ -54,7 +54,12 @@
  * terminology. On a GICv2 system or mode, the lists will be merged and treated
  * as Group 0 interrupts.
  */
-#define RK3399_G1S_IRQS                        ARM_IRQ_SEC_PHY_TIMER
-#define RK3399_G0_IRQS                 ARM_IRQ_SEC_SGI_6
+#define PLAT_RK_GICV3_G1S_IRQS                                         \
+       INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+                      INTR_GROUP1S, GIC_INTR_CFG_LEVEL)
+
+#define PLAT_RK_GICV3_G0_IRQS                                          \
+       INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,     \
+                      INTR_GROUP0, GIC_INTR_CFG_LEVEL)
 
 #endif /* __PLAT_DEF_H__ */