drm/i915: Embedded struct drm_crtc_state in intel_crtc_state

And get rid of the duplicate mode structures. This patch was generated
with the following semantic patch:

@@ @@
struct intel_crtc_state {
+struct drm_crtc_state base;
+
...
-struct drm_display_mode requested_mode;
-struct drm_display_mode adjusted_mode;
...
}
@@ struct intel_crtc_state *state; @@
-state->adjusted_mode
+state->base.adjusted_mode
@@ struct intel_crtc_state *state; @@
-state->requested_mode
+state->base.mode
@@ struct intel_crtc_state state; @@
-state.adjusted_mode
+state.base.adjusted_mode
@@ struct intel_crtc_state state; @@
-state.requested_mode
+state.base.mode
@@ struct drm_crtc *crtc; @@
-to_intel_crtc(crtc)->config.adjusted_mode
+to_intel_crtc(crtc)->config.base.adjusted_mode
@@ identifier member; expression E; @@
-PIPE_CONF_CHECK_FLAGS(adjusted_mode.member, E);
+PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.member, E);
@@ identifier member; @@
-PIPE_CONF_CHECK_I(adjusted_mode.member);
+PIPE_CONF_CHECK_I(base.adjusted_mode.member);
@@ identifier member; @@
-PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.member);
+PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.member);

v2: Completely generate the patch with cocci. (Ander)

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8fe5a87705f7c607fd4e75df39124a42d4f3cb55..d6a15e5c1f2f2fb0a13f2c3ea0ce60c3602d97dd 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -593,7 +593,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
                struct intel_crtc *intel_crtc =
                        to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
                const struct drm_display_mode *mode =
-                       &intel_crtc->config.adjusted_mode;
+                       &intel_crtc->config.base.adjusted_mode;
 
                htotal = mode->crtc_htotal;
                hsync_start = mode->crtc_hsync_start;
@@ -664,7 +664,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 {
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
-       const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+       const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
        enum pipe pipe = crtc->pipe;
        int position, vtotal;
 
@@ -691,7 +691,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
+       const struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;
        int position;
        int vbl_start, vbl_end, hsync_start, htotal, vtotal;
        bool in_vbl = true;
@@ -849,7 +849,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
        return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
                                                     vblank_time, flags,
                                                     crtc,
-                                                    &to_intel_crtc(crtc)->config.adjusted_mode);
+                                                    &to_intel_crtc(crtc)->config.base.adjusted_mode);
 }
 
 static bool intel_hpd_irq_event(struct drm_device *dev,

diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index ee41b882e71aa4126fc9c37fb56228a686b7ec08..2a3f8cb3f35b455169d646ce6c0fe2c99dbdc35b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -400,7 +400,7 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
 {
        struct drm_encoder *encoder = &intel_encoder->base;
        struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
-       struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+       struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
        struct drm_connector *connector;
        struct drm_device *dev = encoder->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 675b85a8ad7dc9eb336ef96637bc7dda9271e4c1..e4f6d4983251482a7dba8a3dfff0dd1f41620e39 100644 (file)
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -115,14 +115,14 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
        struct drm_device *dev = encoder->base.dev;
        int dotclock;
 
-       pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
+       pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 
        dotclock = pipe_config->port_clock;
 
        if (HAS_PCH_SPLIT(dev))
                ironlake_check_encoder_dotclock(pipe_config, dotclock);
 
-       pipe_config->adjusted_mode.crtc_clock = dotclock;
+       pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 }
 
 static void hsw_crt_get_config(struct intel_encoder *encoder,
@@ -130,11 +130,11 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
 {
        intel_ddi_get_config(encoder, pipe_config);
 
-       pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
+       pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
                                              DRM_MODE_FLAG_NHSYNC |
                                              DRM_MODE_FLAG_PVSYNC |
                                              DRM_MODE_FLAG_NVSYNC);
-       pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
+       pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 }
 
 static void hsw_crt_pre_enable(struct intel_encoder *encoder)
@@ -157,7 +157,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crt *crt = intel_encoder_to_crt(encoder);
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-       struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
        u32 adpa;
 
        if (INTEL_INFO(dev)->gen >= 5)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1cc38eb8206c4acd176aa4918d8f48b0c7e8f8c3..7de71ee3b9d1b9e351a2b6a158d815fb3bbb3377 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -768,11 +768,11 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
        pipe_config->port_clock = link_clock;
 
        if (pipe_config->has_dp_encoder)
-               pipe_config->adjusted_mode.crtc_clock =
+               pipe_config->base.adjusted_mode.crtc_clock =
                        intel_dotclock_calculate(pipe_config->port_clock,
                                                 &pipe_config->dp_m_n);
        else
-               pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
+               pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
@@ -820,15 +820,15 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
        pipe_config->port_clock = link_clock * 2;
 
        if (pipe_config->has_pch_encoder)
-               pipe_config->adjusted_mode.crtc_clock =
+               pipe_config->base.adjusted_mode.crtc_clock =
                        intel_dotclock_calculate(pipe_config->port_clock,
                                                 &pipe_config->fdi_m_n);
        else if (pipe_config->has_dp_encoder)
-               pipe_config->adjusted_mode.crtc_clock =
+               pipe_config->base.adjusted_mode.crtc_clock =
                        intel_dotclock_calculate(pipe_config->port_clock,
                                                 &pipe_config->dp_m_n);
        else
-               pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
+               pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
 void intel_ddi_clock_get(struct intel_encoder *encoder,
@@ -1261,9 +1261,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
                BUG();
        }
 
-       if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
+       if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
                temp |= TRANS_DDI_PVSYNC;
-       if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
+       if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
                temp |= TRANS_DDI_PHSYNC;
 
        if (cpu_transcoder == TRANSCODER_EDP) {
@@ -1533,7 +1533,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 
                intel_hdmi->set_infoframes(encoder,
                                           crtc->config.has_hdmi_sink,
-                                          &crtc->config.adjusted_mode);
+                                          &crtc->config.base.adjusted_mode);
        }
 }
 
@@ -2045,7 +2045,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
        else
                flags |= DRM_MODE_FLAG_NVSYNC;
 
-       pipe_config->adjusted_mode.flags |= flags;
+       pipe_config->base.adjusted_mode.flags |= flags;
 
        switch (temp & TRANS_DDI_BPC_MASK) {
        case TRANS_DDI_BPC_6:

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 536a66a9e71ad7db1a0b07d717271cb36029ba53..1a56d50b3c035c2ea7ac718ad067e89e32a6f2d1 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -897,7 +897,7 @@ bool intel_crtc_active(struct drm_crtc *crtc)
         * properly reconstruct framebuffers.
         */
        return intel_crtc->active && crtc->primary->fb &&
-               intel_crtc->config.adjusted_mode.crtc_clock;
+               intel_crtc->config.base.adjusted_mode.crtc_clock;
 }
 
 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
@@ -2941,7 +2941,7 @@ static void intel_update_pipe_size(struct intel_crtc *crtc)
         * then update the pipesrc and pfit state, even on the flip path.
         */
 
-       adjusted_mode = &crtc->config.adjusted_mode;
+       adjusted_mode = &crtc->config.base.adjusted_mode;
 
        I915_WRITE(PIPESRC(crtc->pipe),
                   ((adjusted_mode->crtc_hdisplay - 1) << 16) |
@@ -3577,7 +3577,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
 {
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
-       int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
+       int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
        u32 divsel, phaseinc, auxdiv, phasedir = 0;
        u32 temp;
 
@@ -4908,7 +4908,7 @@ static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
        for_each_intel_crtc(dev, intel_crtc) {
                if (intel_crtc->new_enabled)
                        max_pixclk = max(max_pixclk,
-                                        intel_crtc->new_config->adjusted_mode.crtc_clock);
+                                        intel_crtc->new_config->base.adjusted_mode.crtc_clock);
        }
 
        return max_pixclk;
@@ -5429,7 +5429,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
                                       struct intel_crtc_state *pipe_config)
 {
        struct drm_device *dev = intel_crtc->base.dev;
-       struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
        int lane, link_bw, fdi_dotclock;
        bool setup_ok, needs_recompute = false;
 
@@ -5484,7 +5484,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 {
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
-       struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 
        /* FIXME should check pixel clock limits on all platforms */
        if (INTEL_INFO(dev)->gen < 4) {
@@ -6206,7 +6206,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
        enum pipe pipe = intel_crtc->pipe;
        enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
        struct drm_display_mode *adjusted_mode =
-               &intel_crtc->config.adjusted_mode;
+               &intel_crtc->config.base.adjusted_mode;
        uint32_t crtc_vtotal, crtc_vblank_end;
        int vsyncshift = 0;
 
@@ -6277,56 +6277,56 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
        uint32_t tmp;
 
        tmp = I915_READ(HTOTAL(cpu_transcoder));
-       pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
-       pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
        tmp = I915_READ(HBLANK(cpu_transcoder));
-       pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
-       pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
        tmp = I915_READ(HSYNC(cpu_transcoder));
-       pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
-       pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
 
        tmp = I915_READ(VTOTAL(cpu_transcoder));
-       pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
-       pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
        tmp = I915_READ(VBLANK(cpu_transcoder));
-       pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
-       pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
        tmp = I915_READ(VSYNC(cpu_transcoder));
-       pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
-       pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
+       pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
 
        if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
-               pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
-               pipe_config->adjusted_mode.crtc_vtotal += 1;
-               pipe_config->adjusted_mode.crtc_vblank_end += 1;
+               pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
+               pipe_config->base.adjusted_mode.crtc_vtotal += 1;
+               pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
        }
 
        tmp = I915_READ(PIPESRC(crtc->pipe));
        pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
        pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
 
-       pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
-       pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
+       pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
+       pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
 }
 
 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
                                 struct intel_crtc_state *pipe_config)
 {
-       mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
-       mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
-       mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
-       mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
+       mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
+       mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
+       mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
+       mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
 
-       mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
-       mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
-       mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
-       mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
+       mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
+       mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
+       mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
+       mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
 
-       mode->flags = pipe_config->adjusted_mode.flags;
+       mode->flags = pipe_config->base.adjusted_mode.flags;
 
-       mode->clock = pipe_config->adjusted_mode.crtc_clock;
-       mode->flags |= pipe_config->adjusted_mode.flags;
+       mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
+       mode->flags |= pipe_config->base.adjusted_mode.flags;
 }
 
 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
@@ -6376,7 +6376,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
                }
        }
 
-       if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+       if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
                if (INTEL_INFO(dev)->gen < 4 ||
                    intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
                        pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
@@ -7133,7 +7133,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
        if (intel_crtc->config.dither)
                val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
 
-       if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+       if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
                val |= PIPECONF_INTERLACED_ILK;
        else
                val |= PIPECONF_PROGRESSIVE;
@@ -7223,7 +7223,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
        if (IS_HASWELL(dev) && intel_crtc->config.dither)
                val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
 
-       if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+       if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
                val |= PIPECONF_INTERLACED_ILK;
        else
                val |= PIPECONF_PROGRESSIVE;
@@ -8789,7 +8789,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
         * agree once we know their relationship in the encoder's
         * get_config() function.
         */
-       pipe_config->adjusted_mode.crtc_clock =
+       pipe_config->base.adjusted_mode.crtc_clock =
                intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
                                         &pipe_config->fdi_m_n);
 }
@@ -9981,10 +9981,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
                      pipe_config->has_infoframe);
 
        DRM_DEBUG_KMS("requested mode:\n");
-       drm_mode_debug_printmodeline(&pipe_config->requested_mode);
+       drm_mode_debug_printmodeline(&pipe_config->base.mode);
        DRM_DEBUG_KMS("adjusted mode:\n");
-       drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
-       intel_dump_crtc_timings(&pipe_config->adjusted_mode);
+       drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
+       intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
        DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
        DRM_DEBUG_KMS("pipe src size: %dx%d\n",
                      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
@@ -10108,8 +10108,8 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
        if (!pipe_config)
                return ERR_PTR(-ENOMEM);
 
-       drm_mode_copy(&pipe_config->adjusted_mode, mode);
-       drm_mode_copy(&pipe_config->requested_mode, mode);
+       drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
+       drm_mode_copy(&pipe_config->base.mode, mode);
 
        pipe_config->cpu_transcoder =
                (enum transcoder) to_intel_crtc(crtc)->pipe;
@@ -10120,13 +10120,13 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
         * positive or negative polarity is requested, treat this as meaning
         * negative polarity.
         */
-       if (!(pipe_config->adjusted_mode.flags &
+       if (!(pipe_config->base.adjusted_mode.flags &
              (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
-               pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
+               pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
 
-       if (!(pipe_config->adjusted_mode.flags &
+       if (!(pipe_config->base.adjusted_mode.flags &
              (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
-               pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
+               pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
 
        /* Compute a starting value for pipe_config->pipe_bpp taking the source
         * plane pixel format and any sink constraints into account. Returns the
@@ -10145,7 +10145,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
         * computation to clearly distinguish it from the adjusted mode, which
         * can be changed by the connectors in the below retry loop.
         */
-       drm_crtc_get_hv_timing(&pipe_config->requested_mode,
+       drm_crtc_get_hv_timing(&pipe_config->base.mode,
                               &pipe_config->pipe_src_w,
                               &pipe_config->pipe_src_h);
 
@@ -10155,7 +10155,8 @@ encoder_retry:
        pipe_config->pixel_multiplier = 1;
 
        /* Fill in default crtc timings, allow encoders to overwrite them. */
-       drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
+       drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
+                             CRTC_STEREO_DOUBLE);
 
        /* Pass our mode to the connectors and the CRTC to give them a chance to
         * adjust it according to limitations or connector properties, and also
@@ -10175,7 +10176,7 @@ encoder_retry:
        /* Set default port clock if not overwritten by the encoder. Needs to be
         * done afterwards in case the encoder adjusts the mode. */
        if (!pipe_config->port_clock)
-               pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
+               pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
                        * pipe_config->pixel_multiplier;
 
        ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
@@ -10476,19 +10477,19 @@ intel_pipe_config_compare(struct drm_device *dev,
                PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
        }
 
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
 
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
-       PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
+       PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
 
        PIPE_CONF_CHECK_I(pixel_multiplier);
        PIPE_CONF_CHECK_I(has_hdmi_sink);
@@ -10499,17 +10500,17 @@ intel_pipe_config_compare(struct drm_device *dev,
 
        PIPE_CONF_CHECK_I(has_audio);
 
-       PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+       PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
                              DRM_MODE_FLAG_INTERLACE);
 
        if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
-               PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+               PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
                                      DRM_MODE_FLAG_PHSYNC);
-               PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+               PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
                                      DRM_MODE_FLAG_NHSYNC);
-               PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+               PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
                                      DRM_MODE_FLAG_PVSYNC);
-               PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
+               PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
                                      DRM_MODE_FLAG_NVSYNC);
        }
 
@@ -10559,7 +10560,7 @@ intel_pipe_config_compare(struct drm_device *dev,
        if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
                PIPE_CONF_CHECK_I(pipe_bpp);
 
-       PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
+       PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
        PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
 
 #undef PIPE_CONF_CHECK_X
@@ -10835,9 +10836,9 @@ void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
         * FDI already provided one idea for the dotclock.
         * Yell if the encoder disagrees.
         */
-       WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
+       WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
             "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
-            pipe_config->adjusted_mode.crtc_clock, dotclock);
+            pipe_config->base.adjusted_mode.crtc_clock, dotclock);
 }
 
 static void update_scanline_offset(struct intel_crtc *crtc)
@@ -10863,7 +10864,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
         * one to the value.
         */
        if (IS_GEN2(dev)) {
-               const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+               const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
                int vtotal;
 
                vtotal = mode->crtc_vtotal;
@@ -10992,7 +10993,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
                 * timestamping. They are derived from true hwmode.
                 */
                drm_calc_timestamping_constants(crtc,
-                                               &pipe_config->adjusted_mode);
+                                               &pipe_config->base.adjusted_mode);
        }
 
        /* Only after disabling all output pipelines that will be changed can we

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 28ba283888d33898cb58806adc7f8436979f9c37..737ea1681d10c756ea4998efaeb0eb459fdffb52 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1155,7 +1155,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 {
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
-       struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        enum port port = dp_to_dig_port(intel_dp)->port;
        struct intel_crtc *intel_crtc = encoder->new_crtc;
@@ -1324,7 +1324,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        enum port port = dp_to_dig_port(intel_dp)->port;
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-       struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
 
        /*
         * There are four kinds of DP registers:
@@ -2050,7 +2050,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
                        flags |= DRM_MODE_FLAG_NVSYNC;
        }
 
-       pipe_config->adjusted_mode.flags |= flags;
+       pipe_config->base.adjusted_mode.flags |= flags;
 
        if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
            tmp & DP_COLOR_RANGE_16_235)
@@ -2073,7 +2073,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
        if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
                ironlake_check_encoder_dotclock(pipe_config, dotclock);
 
-       pipe_config->adjusted_mode.crtc_clock = dotclock;
+       pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 
        if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
            pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 2e8951a20a9b9ea960f4e4e436a038070bebe14e..629a6265eaef00e7e1aa1d445cc26fd7fd54e7b9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -38,7 +38,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
        struct drm_device *dev = encoder->base.dev;
        int bpp;
        int lane_count, slots;
-       struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
        struct intel_connector *found = NULL, *intel_connector;
        int mst_pbn;
 
@@ -254,7 +254,7 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
        default:
                break;
        }
-       pipe_config->adjusted_mode.flags |= flags;
+       pipe_config->base.adjusted_mode.flags |= flags;
        intel_dp_get_m_n(crtc, pipe_config);
 
        intel_ddi_clock_get(&intel_dig_port->base, pipe_config);

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9ecac5544fed18e9709c73b59ba12e64d0fb3692..725acb5e491a7a61cba3866a9e1bf8e7e0c7a33f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -264,6 +264,8 @@ struct intel_plane_config {
 };
 
 struct intel_crtc_state {
+       struct drm_crtc_state base;
+
        /**
         * quirks - bitfield with hw state readout quirks
         *
@@ -276,16 +278,6 @@ struct intel_crtc_state {
 #define PIPE_CONFIG_QUIRK_INHERITED_MODE       (1<<1) /* mode inherited from firmware */
        unsigned long quirks;
 
-       /* User requested mode, only valid as a starting point to
-        * compute adjusted_mode, except in the case of (S)DVO where
-        * it's also for the output timings of the (S)DVO chip.
-        * adjusted_mode will then correspond to the S(DVO) chip's
-        * preferred input timings. */
-       struct drm_display_mode requested_mode;
-       /* Actual pipe timings ie. what we program into the pipe timing
-        * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
-       struct drm_display_mode adjusted_mode;
-
        /* Pipe source size (ie. panel fitter input size)
         * All planes will be positioned inside this space,
         * and get clipped at the edges. */

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index ac49daa11070ae3c6a87ba3d7f677b314f03b7c2..ba1c81b4824f90963acd20c5dfb57688703c51cf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -84,8 +84,8 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
                                                   base);
        struct intel_connector *intel_connector = intel_dsi->attached_connector;
        struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
-       struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
-       struct drm_display_mode *mode = &config->requested_mode;
+       struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
+       struct drm_display_mode *mode = &config->base.mode;
 
        DRM_DEBUG_KMS("\n");
 
@@ -452,7 +452,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
        if (!pclk)
                return;
 
-       pipe_config->adjusted_mode.crtc_clock = pclk;
+       pipe_config->base.adjusted_mode.crtc_clock = pclk;
        pipe_config->port_clock = pclk;
 }
 
@@ -566,7 +566,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
        struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
        struct drm_display_mode *adjusted_mode =
-               &intel_crtc->config.adjusted_mode;
+               &intel_crtc->config.base.adjusted_mode;
        enum port port;
        unsigned int bpp = intel_crtc->config.pipe_bpp;
        u32 val, tmp;

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 34bee56b4b0fc0b071bc5d117c3421f354fe547a..108f0583beba3c14ebfb5b4849388c6d01b57eb5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -160,9 +160,9 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
        else
                flags |= DRM_MODE_FLAG_NVSYNC;
 
-       pipe_config->adjusted_mode.flags |= flags;
+       pipe_config->base.adjusted_mode.flags |= flags;
 
-       pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
+       pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
 static void intel_disable_dvo(struct intel_encoder *encoder)
@@ -186,8 +186,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder)
        u32 temp = I915_READ(dvo_reg);
 
        intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
-                                        &crtc->config.requested_mode,
-                                        &crtc->config.adjusted_mode);
+                                        &crtc->config.base.mode,
+                                        &crtc->config.base.adjusted_mode);
 
        I915_WRITE(dvo_reg, temp | DVO_ENABLE);
        I915_READ(dvo_reg);
@@ -264,7 +264,7 @@ static bool intel_dvo_compute_config(struct intel_encoder *encoder,
                                     struct intel_crtc_state *pipe_config)
 {
        struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
-       struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 
        /* If we have timings from the BIOS for the panel, put them in
         * to the adjusted mode.  The CRTC will be set up for this mode,
@@ -295,7 +295,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder)
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-       struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
        struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
        int pipe = crtc->pipe;
        u32 dvo_val;

diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 4daceaeeb30d091f0661596fff8b0320d07359a9..cbd828eb194b75b6e651a23605cd2b04fb8e7543 100644 (file)
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -542,7 +542,7 @@ void intel_fbc_update(struct drm_device *dev)
        intel_crtc = to_intel_crtc(crtc);
        fb = crtc->primary->fb;
        obj = intel_fb_obj(fb);
-       adjusted_mode = &intel_crtc->config.adjusted_mode;
+       adjusted_mode = &intel_crtc->config.base.adjusted_mode;
 
        if (i915.enable_fbc < 0) {
                if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))

diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 850cf7d6578cef54dd2792852e247322995e5a68..04d582b50364c70e501093f666bde165da29d61e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -581,7 +581,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
                 * pipe.  Note we need to use the selected fb's pitch and bpp
                 * rather than the current pipe's, since they differ.
                 */
-               cur_size = intel_crtc->config.adjusted_mode.crtc_hdisplay;
+               cur_size = intel_crtc->config.base.adjusted_mode.crtc_hdisplay;
                cur_size = cur_size * fb->base.bits_per_pixel / 8;
                if (fb->base.pitches[0] < cur_size) {
                        DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n",
@@ -592,13 +592,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
                        break;
                }
 
-               cur_size = intel_crtc->config.adjusted_mode.crtc_vdisplay;
+               cur_size = intel_crtc->config.base.adjusted_mode.crtc_vdisplay;
                cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1);
                cur_size *= fb->base.pitches[0];
                DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
                              pipe_name(intel_crtc->pipe),
-                             intel_crtc->config.adjusted_mode.crtc_hdisplay,
-                             intel_crtc->config.adjusted_mode.crtc_vdisplay,
+                             intel_crtc->config.base.adjusted_mode.crtc_hdisplay,
+                             intel_crtc->config.base.adjusted_mode.crtc_vdisplay,
                              fb->base.bits_per_pixel,
                              cur_size);
 

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 657452b471ec1b79a03b5f4ac305edfc68954670..02ff3e2de88b81c90e72a2e72e9ef5dd9e906125 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -700,7 +700,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
-       struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;
        u32 hdmi_val;
 
        hdmi_val = SDVO_ENCODING_HDMI;
@@ -792,7 +792,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
            tmp & HDMI_COLOR_RANGE_16_235)
                pipe_config->limited_color_range = true;
 
-       pipe_config->adjusted_mode.flags |= flags;
+       pipe_config->base.adjusted_mode.flags |= flags;
 
        if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
                dotclock = pipe_config->port_clock * 2 / 3;
@@ -802,7 +802,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
        if (HAS_PCH_SPLIT(dev_priv->dev))
                ironlake_check_encoder_dotclock(pipe_config, dotclock);
 
-       pipe_config->adjusted_mode.crtc_clock = dotclock;
+       pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 }
 
 static void intel_enable_hdmi(struct intel_encoder *encoder)
@@ -979,8 +979,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 {
        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
        struct drm_device *dev = encoder->base.dev;
-       struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
-       int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
+       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+       int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2;
        int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
        int desired_bpp;
 
@@ -1252,7 +1252,7 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
        struct drm_display_mode *adjusted_mode =
-               &intel_crtc->config.adjusted_mode;
+               &intel_crtc->config.base.adjusted_mode;
 
        intel_hdmi_prepare(encoder);
 
@@ -1270,7 +1270,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
        struct intel_crtc *intel_crtc =
                to_intel_crtc(encoder->base.crtc);
        struct drm_display_mode *adjusted_mode =
-               &intel_crtc->config.adjusted_mode;
+               &intel_crtc->config.base.adjusted_mode;
        enum dpio_channel port = vlv_dport_to_channel(dport);
        int pipe = intel_crtc->pipe;
        u32 val;
@@ -1467,7 +1467,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
        struct intel_crtc *intel_crtc =
                to_intel_crtc(encoder->base.crtc);
        struct drm_display_mode *adjusted_mode =
-               &intel_crtc->config.adjusted_mode;
+               &intel_crtc->config.base.adjusted_mode;
        enum dpio_channel ch = vlv_dport_to_channel(dport);
        int pipe = intel_crtc->pipe;
        int data, i;

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index f8e2f1309ae98b791f2963e170f4284b89c3097a..9d174cf9c74642510f04ca1b3e85c2f436770aef 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -115,7 +115,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
        else
                flags |= DRM_MODE_FLAG_PVSYNC;
 
-       pipe_config->adjusted_mode.flags |= flags;
+       pipe_config->base.adjusted_mode.flags |= flags;
 
        /* gen2/3 store dither state in pfit control, needs to match */
        if (INTEL_INFO(dev)->gen < 4) {
@@ -129,7 +129,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
        if (HAS_PCH_SPLIT(dev_priv->dev))
                ironlake_check_encoder_dotclock(pipe_config, dotclock);
 
-       pipe_config->adjusted_mode.crtc_clock = dotclock;
+       pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 }
 
 static void intel_pre_enable_lvds(struct intel_encoder *encoder)
@@ -139,7 +139,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
        const struct drm_display_mode *adjusted_mode =
-               &crtc->config.adjusted_mode;
+               &crtc->config.base.adjusted_mode;
        int pipe = crtc->pipe;
        u32 temp;
 
@@ -284,7 +284,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
                to_lvds_encoder(&intel_encoder->base);
        struct intel_connector *intel_connector =
                &lvds_encoder->attached_connector->base;
-       struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
        struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
        unsigned int lvds_bpp;
 

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index c3c5ed416a73033d58eef723720bc7469be77aba..d7be68a7bbda61ee25dc95f392739d0a750df8a9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -104,7 +104,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
        struct drm_display_mode *adjusted_mode;
        int x, y, width, height;
 
-       adjusted_mode = &pipe_config->adjusted_mode;
+       adjusted_mode = &pipe_config->base.adjusted_mode;
 
        x = y = width = height = 0;
 
@@ -226,7 +226,7 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
 static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
                              u32 *pfit_control)
 {
-       struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
        u32 scaled_width = adjusted_mode->hdisplay *
                pipe_config->pipe_src_h;
        u32 scaled_height = pipe_config->pipe_src_w *
@@ -247,7 +247,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
                              u32 *pfit_control, u32 *pfit_pgm_ratios,
                              u32 *border)
 {
-       struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
        u32 scaled_width = adjusted_mode->hdisplay *
                pipe_config->pipe_src_h;
        u32 scaled_height = pipe_config->pipe_src_w *
@@ -308,7 +308,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
        u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
        struct drm_display_mode *adjusted_mode;
 
-       adjusted_mode = &pipe_config->adjusted_mode;
+       adjusted_mode = &pipe_config->base.adjusted_mode;
 
        /* Native modes don't need fitting */
        if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 933b32c5760beff25346352d7f877ca3cd7fe63a..40ce07d2cd55f501bf2852edfe8b974066eeec18 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -539,7 +539,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
                int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
                int clock;
 
-               adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+               adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
                clock = adjusted_mode->crtc_clock;
 
                /* Display SR */
@@ -608,7 +608,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
                return false;
        }
 
-       adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+       adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
        clock = adjusted_mode->crtc_clock;
        htotal = adjusted_mode->crtc_htotal;
        hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
@@ -695,7 +695,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
        }
 
        crtc = intel_get_crtc_for_plane(dev, plane);
-       adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+       adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
        clock = adjusted_mode->crtc_clock;
        htotal = adjusted_mode->crtc_htotal;
        hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
@@ -729,7 +729,7 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
 {
        struct drm_device *dev = crtc->dev;
        int entries;
-       int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
+       int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
 
        if (WARN(clock == 0, "Pixel clock is zero!\n"))
                return false;
@@ -1059,7 +1059,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
                /* self-refresh has much higher latency */
                static const int sr_latency_ns = 12000;
                const struct drm_display_mode *adjusted_mode =
-                       &to_intel_crtc(crtc)->config.adjusted_mode;
+                       &to_intel_crtc(crtc)->config.base.adjusted_mode;
                int clock = adjusted_mode->crtc_clock;
                int htotal = adjusted_mode->crtc_htotal;
                int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
@@ -1144,7 +1144,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
                if (IS_GEN2(dev))
                        cpp = 4;
 
-               adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+               adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
                planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
                                               wm_info, fifo_size, cpp,
                                               pessimal_latency_ns);
@@ -1166,7 +1166,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
                if (IS_GEN2(dev))
                        cpp = 4;
 
-               adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+               adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
                planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
                                               wm_info, fifo_size, cpp,
                                               pessimal_latency_ns);
@@ -1205,7 +1205,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
                /* self-refresh has much higher latency */
                static const int sr_latency_ns = 6000;
                const struct drm_display_mode *adjusted_mode =
-                       &to_intel_crtc(enabled)->config.adjusted_mode;
+                       &to_intel_crtc(enabled)->config.base.adjusted_mode;
                int clock = adjusted_mode->crtc_clock;
                int htotal = adjusted_mode->crtc_htotal;
                int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
@@ -1261,7 +1261,7 @@ static void i845_update_wm(struct drm_crtc *unused_crtc)
        if (crtc == NULL)
                return;
 
-       adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+       adjusted_mode = &to_intel_crtc(crtc)->config.base.adjusted_mode;
        planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
                                       &i845_wm_info,
                                       dev_priv->display.get_fifo_size(dev, 0),
@@ -1280,7 +1280,7 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        uint32_t pixel_rate;
 
-       pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
+       pixel_rate = intel_crtc->config.base.adjusted_mode.crtc_clock;
 
        /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
         * adjust the pixel_rate here. */
@@ -1643,7 +1643,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
+       struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;
        u32 linetime, ips_linetime;
 
        if (!intel_crtc_active(crtc))
@@ -1903,7 +1903,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
                return;
 
        p->active = true;
-       p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
+       p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal;
        p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
        p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
        p->cur.bytes_per_pixel = 4;
@@ -2559,7 +2559,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
 {
        /* TODO: Take into account the scalers once we support them */
-       return config->adjusted_mode.crtc_clock;
+       return config->base.adjusted_mode.crtc_clock;
 }
 
 /*
@@ -2647,7 +2647,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
 
        p->active = intel_crtc_active(crtc);
        if (p->active) {
-               p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
+               p->pipe_htotal = intel_crtc->config.base.adjusted_mode.crtc_htotal;
                p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config);
 
                /*

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5ae193ec464a59d69510b6bf12f2f7af487ba6ed..a97775db2481adb5497fd14c4cb2d76c4ec82001 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -270,7 +270,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
        }
 
        if (IS_HASWELL(dev) &&
-           intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+           intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
                DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
                return false;
        }

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index cced048b630712f7cf0b96bdf4622d8fbcc0d8f2..953abec08a0fc2349fcf3dae6e597d5d84fddfc9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1115,8 +1115,8 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
                                      struct intel_crtc_state *pipe_config)
 {
        struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
-       struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
-       struct drm_display_mode *mode = &pipe_config->requested_mode;
+       struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+       struct drm_display_mode *mode = &pipe_config->base.mode;
 
        DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
        pipe_config->pipe_bpp = 8*3;
@@ -1181,8 +1181,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
        struct drm_display_mode *adjusted_mode =
-               &crtc->config.adjusted_mode;
-       struct drm_display_mode *mode = &crtc->config.requested_mode;
+               &crtc->config.base.adjusted_mode;
+       struct drm_display_mode *mode = &crtc->config.base.mode;
        struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
        u32 sdvox;
        struct intel_sdvo_in_out_map in_out;
@@ -1370,7 +1370,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
                        flags |= DRM_MODE_FLAG_NVSYNC;
        }
 
-       pipe_config->adjusted_mode.flags |= flags;
+       pipe_config->base.adjusted_mode.flags |= flags;
 
        /*
         * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
@@ -1392,7 +1392,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
        if (HAS_PCH_SPLIT(dev))
                ironlake_check_encoder_dotclock(pipe_config, dotclock);
 
-       pipe_config->adjusted_mode.crtc_clock = dotclock;
+       pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 
        /* Cross check the port pixel multiplier with the sdvo encoder state. */
        if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index dca3f70ef1ba02aebd587f7e8163f108a1daedb7..a0a3a060752ca246fe66a60a934c5266ca98ee70 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -80,7 +80,7 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
 bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
 {
        struct drm_device *dev = crtc->base.dev;
-       const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+       const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
        enum pipe pipe = crtc->pipe;
        long timeout = msecs_to_jiffies_timeout(1);
        int scanline, min, max, vblank_start;

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 1a57236badb2ab338e3a99b3103dda955420cc07..10e7ebd79f5a2882b3ed91c43d24cf54677acf79 100644 (file)
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -910,7 +910,7 @@ static void
 intel_tv_get_config(struct intel_encoder *encoder,
                    struct intel_crtc_state *pipe_config)
 {
-       pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
+       pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
 static bool
@@ -923,12 +923,12 @@ intel_tv_compute_config(struct intel_encoder *encoder,
        if (!tv_mode)
                return false;
 
-       pipe_config->adjusted_mode.crtc_clock = tv_mode->clock;
+       pipe_config->base.adjusted_mode.crtc_clock = tv_mode->clock;
        DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
        pipe_config->pipe_bpp = 8*3;
 
        /* TV has it's own notion of sync and other mode flags, so clear them. */
-       pipe_config->adjusted_mode.flags = 0;
+       pipe_config->base.adjusted_mode.flags = 0;
 
        /*
         * FIXME: We don't check whether the input mode is actually what we want