drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS
authorDamien Lespiau <damien.lespiau@intel.com>
Mon, 9 Feb 2015 19:33:20 +0000 (19:33 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 13 Feb 2015 22:28:36 +0000 (23:28 +0100)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c

index 75227009d0bbc3109a97adca8a54b59ce70ac430..ecc14f5587442a3e51dce7f5bd1a3ae7ac467935 100644 (file)
@@ -5236,6 +5236,9 @@ enum skl_disp_power_wells {
 #define HSW_NDE_RSTWRN_OPT     0x46408
 #define  RESET_PCH_HANDSHAKE_ENABLE    (1<<4)
 
+#define FF_SLICE_CS_CHICKEN2                   0x02e4
+#define  GEN9_TSG_BARRIER_ACK_DISABLE          (1<<8)
+
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1             0x7010
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC     ((1<<10) | (1<<26))
index a2b9c3e213f935a9693471a1c51674438661d468..325f640c16c45a6f7dca8dd5532e582f8f4505be 100644 (file)
@@ -66,11 +66,16 @@ static void skl_init_clock_gating(struct drm_device *dev)
                           GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
        }
 
-       if (INTEL_REVID(dev) <= SKL_REVID_D0)
+       if (INTEL_REVID(dev) <= SKL_REVID_D0) {
                /* WaDisableHDCInvalidation:skl */
                I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
                           BDW_DISABLE_HDC_INVALIDATION);
 
+               /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
+               I915_WRITE(FF_SLICE_CS_CHICKEN2,
+                          I915_READ(FF_SLICE_CS_CHICKEN2) |
+                          GEN9_TSG_BARRIER_ACK_DISABLE);
+       }
 
        if (INTEL_REVID(dev) <= SKL_REVID_E0)
                /* WaDisableLSQCROPERFforOCL:skl */