ath9k: Fix initvals for freq 2484

This is missing for AR9300, AR9580 and AR9340.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index 15533953e0a2ac138aaf10f21591ee216bbb14c5..e7cdf1100f56bc1ea52273c6b756779e1a3b2ff2 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -1738,4 +1738,11 @@ static const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = {
        {0x00004044, 0x00000000},
 };
 
+static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = {
+       /* Addr      allmodes  */
+       {0x0000a398, 0x00000000},
+       {0x0000a39c, 0x6f7f0301},
+       {0x0000a3a0, 0xca9228ee},
+};
+
 #endif /* INITVALS_9003_2P2_H */

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index d3eca0cec9cd31725012049e69977abeaf46fb89..d8c1eee8ea53014dfde6536d507ec36862b0062f 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -149,7 +149,9 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
                                ar9340Modes_high_ob_db_tx_gain_table_1p0);
 
                INIT_INI_ARRAY(&ah->iniModesFastClock,
-                               ar9340Modes_fast_clock_1p0);
+                              ar9340Modes_fast_clock_1p0);
+               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+                              ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
 
                if (!ah->is_clk_25mhz)
                        INIT_INI_ARRAY(&ah->iniAdditional,
@@ -335,7 +337,9 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
                                ar9580_1p0_low_ob_db_tx_gain_table);
 
                INIT_INI_ARRAY(&ah->iniModesFastClock,
-                               ar9580_1p0_modes_fast_clock);
+                              ar9580_1p0_modes_fast_clock);
+               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+                              ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
        } else if (AR_SREV_9565_11_OR_LATER(ah)) {
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
                               ar9565_1p1_mac_core);
@@ -451,7 +455,9 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 
                /* Fast clock modal settings */
                INIT_INI_ARRAY(&ah->iniModesFastClock,
-                               ar9300Modes_fast_clock_2p2);
+                              ar9300Modes_fast_clock_2p2);
+               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+                              ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
        }
 }
 

diff --git a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
index d2d789bdb7f87bdfd289a3ce5468fb0d08dd1c3a..7f22cb2a494113f8575c326bcf19405febc6d7d1 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
@@ -28,6 +28,8 @@
 
 #define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
 
+#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
+
 static const u32 ar9340_1p0_radio_postamble[][5] = {
        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
        {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},

diff --git a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
index 2ae380b70c021b7abcd07a94d16b6a32f1f4fc57..75bef1179d0d674f857b61f455f1ba045a44e35a 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
@@ -36,7 +36,7 @@
 
 #define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
 
-#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
+#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
 
 static const u32 ar9580_1p0_radio_postamble[][5] = {
        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */