Until now the SPI driver used the TX bits for the RX FIFO. This seems
uncritical for now since both are equals on my devices (VR9), but this
could cause problems on other SoCs.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 47208
+ /* Read module capabilities */
+ id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
+ hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
-+ hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
++ hw->rxfs = (id >> LTQ_SPI_ID_RXFS_SHIFT) & LTQ_SPI_ID_RXFS_MASK;
+ hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
+
+ ltq_spi_config_mode_set(hw);
+ /* Read module capabilities */
+ id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
+ hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
-+ hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
++ hw->rxfs = (id >> LTQ_SPI_ID_RXFS_SHIFT) & LTQ_SPI_ID_RXFS_MASK;
+ hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
+
+ ltq_spi_config_mode_set(hw);