#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
-#include <asm/mpc85xx_gpio.h>
#include "../common/qixis.h"
#include "t102xqds.h"
#include "t102xqds_qixis.h"
+#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
}
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ return 0;
+}
+
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
}
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg