ppx4xx: remove APC405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>

diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 8f8860163c990189e545e31e0e791608815c440a..53e86606fdc172e2945cce07ca28112ecd08be8b 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -110,9 +110,6 @@ config TARGET_CATCENTER
 config TARGET_PPCHAMELEONEVB
        bool "Support PPChameleonEVB"
 
-config TARGET_APC405
-       bool "Support APC405"
-
 config TARGET_AR405
        bool "Support AR405"
 
@@ -257,7 +254,6 @@ source "board/avnet/v5fx30teval/Kconfig"
 source "board/csb272/Kconfig"
 source "board/csb472/Kconfig"
 source "board/dave/PPChameleonEVB/Kconfig"
-source "board/esd/apc405/Kconfig"
 source "board/esd/ar405/Kconfig"
 source "board/esd/ash405/Kconfig"
 source "board/esd/cms700/Kconfig"

diff --git a/board/esd/apc405/Kconfig b/board/esd/apc405/Kconfig
deleted file mode 100644 (file)
index 6b03460..0000000
--- a/board/esd/apc405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_APC405
-
-config SYS_BOARD
-       default "apc405"
-
-config SYS_VENDOR
-       default "esd"
-
-config SYS_CONFIG_NAME
-       default "APC405"
-
-endif

diff --git a/board/esd/apc405/MAINTAINERS b/board/esd/apc405/MAINTAINERS
deleted file mode 100644 (file)
index 7f2a33f..0000000
--- a/board/esd/apc405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-APC405 BOARD
-M:     Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S:     Maintained
-F:     board/esd/apc405/
-F:     include/configs/APC405.h
-F:     configs/APC405_defconfig

diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile
deleted file mode 100644 (file)
index ada8bfd..0000000
--- a/board/esd/apc405/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = apc405.o \
-       ../common/misc.o \
-       ../common/auto_update.o

diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
deleted file mode 100644 (file)
index 5cc1d0d..0000000
--- a/board/esd/apc405/apc405.c
+++ /dev/null
@@ -1,461 +0,0 @@
-/*
- * (C) Copyright 2005-2008
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-#include <flash.h>
-#include <mtd/cfi_flash.h>
-#include <asm/4xx_pci.h>
-#include <pci.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef FPGA_DEBUG
-
-extern void lxt971_no_sleep(void);
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-#ifdef CONFIG_LCD_USED
-/* logo bitmap data - gzip compressed and generated by bin2c */
-unsigned char logo_bmp[] =
-{
-#include "logo_640_480_24bpp.c"
-};
-
-/*
- * include common lcd code (for esd boards)
- */
-#include "../common/lcd.c"
-#include "../common/s1d13505_640_480_16bpp.h"
-#include "../common/s1d13806_640_480_16bpp.h"
-#endif /* CONFIG_LCD_USED */
-
-/*
- * include common auto-update code (for esd boards)
- */
-#include "../common/auto_update.h"
-
-au_image_t au_image[] = {
-       {"preinst.img", 0, -1, AU_SCRIPT},
-       {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
-       {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
-       {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
-       {"work.img", 0xfe500000, 0x01400000, AU_NOR},
-       {"data.img", 0xff900000, 0x00580000, AU_NOR},
-       {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
-       {"postinst.img", 0, 0, AU_SCRIPT},
-};
-
-int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
-
-int board_revision(void)
-{
-       unsigned long CPC0_CR0Reg;
-       unsigned long value;
-
-       /*
-        * Get version of APC405 board from GPIO's
-        */
-
-       /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
-       CPC0_CR0Reg = mfdcr(CPC0_CR0);
-       mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
-       out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
-       out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
-
-       /* wait some time before reading input */
-       udelay(1000);
-
-       /* get config bits */
-       value = in_be32((void*)GPIO0_IR) & 0x001c0000;
-       /*
-        * Restore GPIO settings
-        */
-       mtdcr(CPC0_CR0, CPC0_CR0Reg);
-
-       switch (value) {
-       case 0x001c0000:
-               /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
-               return 2;
-       case 0x000c0000:
-               /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
-               return 3;
-       case 0x00180000:
-               /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
-               return 6;
-       case 0x00140000:
-               /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
-               return 8;
-       default:
-               /* should not be reached! */
-               return 0;
-       }
-}
-
-int board_early_init_f (void)
-{
-       /*
-        * First pull fpga-prg pin low, to disable fpga logic
-        */
-       out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins */
-       out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output   */
-       out_be32((void*)GPIO0_OR, 0);                  /* pull prg low       */
-
-       /*
-        * IRQ 0-15  405GP internally generated; active high; level sensitive
-        * IRQ 16    405GP internally generated; active low; level sensitive
-        * IRQ 17-24 RESERVED
-        * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-        * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
-        * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
-        * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
-        * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
-        * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
-        * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
-        */
-       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
-       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
-       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
-       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0 */
-       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-
-       /*
-        * EBC Configuration Register: set ready timeout to 512 ebc-clks
-        */
-       mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
-
-       /*
-        * New boards have a single 32MB flash connected to CS0
-        * instead of two 16MB flashes on CS0+1.
-        */
-       if (board_revision() >= 8) {
-               /* disable CS1 */
-               mtebc(PB1AP, 0);
-               mtebc(PB1CR, 0);
-
-               /* resize CS0 to 32MB */
-               mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
-               mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
-       }
-
-       return 0;
-}
-
-int board_early_init_r(void)
-{
-       if (gd->board_type >= 8)
-               cfi_flash_num_flash_banks = 1;
-
-       return 0;
-}
-
-#define FUJI_BASE    0xf0100200
-#define LCDBL_PWM    0xa0
-#define LCDBL_PWMMIN 0xa4
-#define LCDBL_PWMMAX 0xa8
-
-int misc_init_r(void)
-{
-       u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
-       u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
-       u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
-       u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
-       unsigned char *dst;
-       ulong len = sizeof(fpgadata);
-       int status;
-       int index;
-       int i;
-       unsigned long CPC0_CR0Reg;
-       char *str;
-       uchar *logo_addr;
-       ulong logo_size;
-       ushort minb, maxb;
-       int result;
-
-       /*
-        * Setup GPIO pins (CS6+CS7 as GPIO)
-        */
-       CPC0_CR0Reg = mfdcr(CPC0_CR0);
-       mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
-
-       dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
-       if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
-               printf("GUNZIP ERROR - must RESET board to recover\n");
-               do_reset(NULL, 0, 0, NULL);
-       }
-
-       status = fpga_boot(dst, len);
-       if (status != 0) {
-               printf("\nFPGA: Booting failed ");
-               switch (status) {
-               case ERROR_FPGA_PRG_INIT_LOW:
-                       printf("(Timeout: "
-                              "INIT not low after asserting PROGRAM*)\n ");
-                       break;
-               case ERROR_FPGA_PRG_INIT_HIGH:
-                       printf("(Timeout: "
-                              "INIT not high after deasserting PROGRAM*)\n ");
-                       break;
-               case ERROR_FPGA_PRG_DONE:
-                       printf("(Timeout: "
-                              "DONE not high after programming FPGA)\n ");
-                       break;
-               }
-
-               /* display infos on fpgaimage */
-               index = 15;
-               for (i = 0; i < 4; i++) {
-                       len = dst[index];
-                       printf("FPGA: %s\n", &(dst[index+1]));
-                       index += len + 3;
-               }
-               putc('\n');
-               /* delayed reboot */
-               for (i = 20; i > 0; i--) {
-                       printf("Rebooting in %2d seconds \r",i);
-                       for (index = 0; index < 1000; index++)
-                               udelay(1000);
-               }
-               putc('\n');
-               do_reset(NULL, 0, 0, NULL);
-       }
-
-       /* restore gpio/cs settings */
-       mtdcr(CPC0_CR0, CPC0_CR0Reg);
-
-       puts("FPGA:  ");
-
-       /* display infos on fpgaimage */
-       index = 15;
-       for (i = 0; i < 4; i++) {
-               len = dst[index];
-               printf("%s ", &(dst[index + 1]));
-               index += len + 3;
-       }
-       putc('\n');
-
-       free(dst);
-
-       /*
-        * Reset FPGA via FPGA_DATA pin
-        */
-       SET_FPGA(FPGA_PRG | FPGA_CLK);
-       udelay(1000); /* wait 1ms */
-       SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
-       udelay(1000); /* wait 1ms */
-
-       /*
-        * Write board revision in FPGA
-        */
-       out_be16(fpga_ctrl2,
-                (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
-
-       /*
-        * Enable power on PS/2 interface (with reset)
-        */
-       out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
-       for (i=0;i<100;i++)
-               udelay(1000);
-       udelay(1000);
-       out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
-
-       /*
-        * Enable interrupts in exar duart mcr[3]
-        */
-       out_8(duart0_mcr, 0x08);
-       out_8(duart1_mcr, 0x08);
-
-       /*
-        * Init lcd interface and display logo
-        */
-       str = getenv("splashimage");
-       if (str) {
-               logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
-               logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
-       } else {
-               logo_addr = logo_bmp;
-               logo_size = sizeof(logo_bmp);
-       }
-
-       if (gd->board_type >= 6) {
-               result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
-                                 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
-                                 regs_13505_640_480_16bpp,
-                                 sizeof(regs_13505_640_480_16bpp) /
-                                 sizeof(regs_13505_640_480_16bpp[0]),
-                                 logo_addr, logo_size);
-               if (result && str) {
-                       /* retry with internal image */
-                       logo_addr = logo_bmp;
-                       logo_size = sizeof(logo_bmp);
-                       lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
-                                (uchar *)CONFIG_SYS_LCD_BIG_MEM,
-                                regs_13505_640_480_16bpp,
-                                sizeof(regs_13505_640_480_16bpp) /
-                                sizeof(regs_13505_640_480_16bpp[0]),
-                                logo_addr, logo_size);
-               }
-       } else {
-               result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
-                                 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
-                                 regs_13806_640_480_16bpp,
-                                 sizeof(regs_13806_640_480_16bpp) /
-                                 sizeof(regs_13806_640_480_16bpp[0]),
-                                 logo_addr, logo_size);
-               if (result && str) {
-                       /* retry with internal image */
-                       logo_addr = logo_bmp;
-                       logo_size = sizeof(logo_bmp);
-                       lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
-                                (uchar *)CONFIG_SYS_LCD_BIG_MEM,
-                                regs_13806_640_480_16bpp,
-                                sizeof(regs_13806_640_480_16bpp) /
-                                sizeof(regs_13806_640_480_16bpp[0]),
-                                logo_addr, logo_size);
-               }
-       }
-
-       /*
-        * Reset microcontroller and setup backlight PWM controller
-        */
-       out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
-       for (i=0;i<10;i++)
-               udelay(1000);
-       out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
-
-       minb = 0;
-       maxb = 0xff;
-       str = getenv("lcdbl");
-       if (str) {
-               minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
-               if (str && (*str=',')) {
-                       str++;
-                       maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
-               } else
-                       minb = 0;
-
-               out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
-               out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
-
-               printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
-       }
-       out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
-
-       /*
-        * fix environment for field updated units
-        */
-       if (getenv("altbootcmd") == NULL) {
-               setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
-               setenv("usbargs", CONFIG_SYS_USB_ARGS);
-               setenv("bootcmd", CONFIG_BOOTCOMMAND);
-               setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
-               setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
-               setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
-               saveenv();
-       }
-
-       return (0);
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
-       char str[64];
-       int i = getenv_f("serial#", str, sizeof(str));
-
-       puts ("Board: ");
-
-       if (i == -1) {
-               puts ("### No HW ID - assuming APC405");
-       } else {
-               puts(str);
-       }
-
-       gd->board_type = board_revision();
-       printf(", Rev. 1.%ld\n", gd->board_type);
-
-       return 0;
-}
-
-#ifdef CONFIG_IDE_RESET
-void ide_set_reset(int on)
-{
-       u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
-
-       /*
-        * Assert or deassert CompactFlash Reset Pin
-        */
-       if (on) {
-               out_be16(fpga_mode,
-                        in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
-       } else {
-               out_be16(fpga_mode,
-                        in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
-       }
-}
-#endif /* CONFIG_IDE_RESET */
-
-void reset_phy(void)
-{
-       /*
-        * Disable sleep mode in LXT971
-        */
-       lxt971_no_sleep();
-}
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int board_usb_init(int index, enum usb_init_type init)
-{
-       return 0;
-}
-
-int usb_board_stop(void)
-{
-       unsigned short tmp;
-       int i;
-
-       /*
-        * reset PCI bus
-        * This is required to make some very old Linux OHCI driver
-        * work after U-Boot has used the OHCI controller.
-        */
-       pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
-       pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
-
-       for (i = 0; i < 100; i++)
-               udelay(1000);
-
-       pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
-       return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-       return usb_board_stop();
-}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */

diff --git a/board/esd/apc405/fpgadata.c b/board/esd/apc405/fpgadata.c
deleted file mode 100644 (file)
index b68668c..0000000
--- a/board/esd/apc405/fpgadata.c
+++ /dev/null
@@ -1,4008 +0,0 @@
-0x1f, 0x8b, 0x08, 0x08, 0x49, 0xe1, 0xdb, 0x46,
-0x00, 0x03, 0x61, 0x62, 0x67, 0x34, 0x30, 0x35,
-0x5f, 0x31, 0x5f, 0x30, 0x33, 0x2e, 0x62, 0x69,
-0x74, 0x00, 0xed, 0xfd, 0x7d, 0x7c, 0x14, 0xd7,
-0x75, 0x3f, 0x8e, 0x9f, 0xb9, 0x33, 0x12, 0xa3,
-0xdd, 0x95, 0x76, 0xf4, 0xe4, 0xac, 0x6d, 0x20,
-0xa3, 0x95, 0x20, 0x6b, 0xb2, 0x88, 0x45, 0x60,
-0x8c, 0xb1, 0x90, 0x06, 0x49, 0x26, 0x8a, 0x4d,
-0x8c, 0x4c, 0xdd, 0x84, 0xf6, 0x9b, 0xa6, 0x6b,
-0x42, 0x53, 0xda, 0x17, 0x49, 0x65, 0x27, 0x9f,
-0x96, 0xe6, 0x93, 0x26, 0x57, 0x2b, 0x81, 0x85,
-0x21, 0xf6, 0x1a, 0x93, 0x46, 0x4e, 0x69, 0xba,
-0x60, 0xea, 0xc8, 0x09, 0x4d, 0x96, 0x07, 0x9b,
-0x07, 0x53, 0x3c, 0xc2, 0x32, 0x11, 0x18, 0xdb,
-0x0a, 0x71, 0x53, 0xf9, 0x21, 0xf6, 0x9a, 0xc8,
-0x44, 0xb6, 0x89, 0x23, 0xdb, 0xc4, 0x11, 0xcf,
-0xdf, 0x73, 0xee, 0xec, 0x3c, 0xec, 0x4a, 0x24,
-0xe9, 0xe7, 0xf3, 0xf3, 0xef, 0xf7, 0xc7, 0x2f,
-0x9b, 0x3f, 0x72, 0x3c, 0x7b, 0x35, 0xcc, 0x3d,
-0x7b, 0xe7, 0xdc, 0xf7, 0x3d, 0xe7, 0x7d, 0xce,
-0x81, 0xa2, 0xe0, 0xa8, 0xf5, 0x3f, 0x00, 0xe9,
-0x4e, 0xd0, 0xee, 0x5c, 0xf1, 0xd7, 0x73, 0x63,
-0xd7, 0xff, 0xe5, 0xec, 0xbf, 0x8c, 0xcd, 0xa9,
-0xfd, 0xd2, 0xe7, 0x57, 0xc2, 0x0a, 0xf0, 0xd5,
-0x7d, 0xf9, 0xfa, 0xd8, 0x17, 0xfe, 0xba, 0xee,
-0xfa, 0x79, 0xf0, 0x79, 0xf0, 0xd7, 0xc5, 0x62,
-0x37, 0xcc, 0xd2, 0x6f, 0x9c, 0xa5, 0xcf, 0x81,
-0x95, 0x50, 0x34, 0xbb, 0x6e, 0x41, 0x5d, 0xdd,
-0x82, 0x39, 0xd7, 0xc3, 0x5f, 0x81, 0x54, 0x1a,
-0xb8, 0x8c, 0x9f, 0xef, 0x3f, 0xf4, 0xa7, 0x5f,
-0x88, 0x01, 0x97, 0x00, 0x60, 0x52, 0x4c, 0x8a,
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diff --git a/board/esd/apc405/logo_640_480_24bpp.c b/board/esd/apc405/logo_640_480_24bpp.c
deleted file mode 100644 (file)
index a218032..0000000
--- a/board/esd/apc405/logo_640_480_24bpp.c
+++ /dev/null
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-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x4f, 0xc5,
-0xff, 0x02, 0x04, 0xc4, 0x15, 0x0c, 0x36, 0xb4,
-0x04, 0x00,

diff --git a/configs/APC405_defconfig b/configs/APC405_defconfig
deleted file mode 100644 (file)
index d9da49b..0000000
--- a/configs/APC405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_APC405=y

diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 46fefcd4aeaccd3977c58eced0d73d68256840a0..b4477cbb0dc8acd553d50e78b8f80d3b687e5b79 100644 (file)
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+APC405           ppc4xx      405gpr         -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
 TASREG           m68k        mcf52x2        -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
 A3000            powerpc     mpc824x        -           -
 CPC45            powerpc     mpc824x        -           -           Josef Wagner <Wagner@Microsys.de>

diff --git a/include/configs/APC405.h b/include/configs/APC405.h
deleted file mode 100644 (file)
index 2678f50..0000000
--- a/include/configs/APC405.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * (C) Copyright 2005-2008
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_405GP           1       /* This is a PPC405 CPU         */
-#define CONFIG_APCG405         1       /* ...on a APC405 board         */
-
-#define        CONFIG_SYS_TEXT_BASE    0xFFF80000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1    /* call board_early_init_f()    */
-#define CONFIG_BOARD_EARLY_INIT_R 1
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
-
-#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
-
-#define CONFIG_BOARD_TYPES     1       /* support board types          */
-
-#define CONFIG_BAUDRATE                115200
-#define CONFIG_BOOTDELAY       1       /* autoboot after 3 seconds     */
-#define CONFIG_BOOTCOUNT_LIMIT 1
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_SYS_USB_LOAD_COMMAND    "fatload usb 0 200000 pImage;"          \
-                               "fatload usb 0 300000 pImage.initrd"
-#define CONFIG_SYS_USB_SELF_COMMAND    "usb start;run usb_load;usb stop;"      \
-                               "run ramargs addip addcon usbargs;"     \
-                               "bootm 200000 300000"
-#define CONFIG_SYS_USB_ARGS            "setenv bootargs $(bootargs) usbboot=1"
-#define CONFIG_SYS_BOOTLIMIT           "3"
-#define CONFIG_SYS_ALT_BOOTCOMMAND     "run usb_self;reset"
-
-#define CONFIG_EXTRA_ENV_SETTINGS                                       \
-       "hostname=abg405\0"                                             \
-       "bd_type=abg405\0"                                              \
-       "serial#=AA0000\0"                                              \
-       "kernel_addr=fe000000\0"                                        \
-       "ramdisk_addr=fe100000\0"                                       \
-       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
-       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
-       "nfsroot=$(serverip):$(rootpath)\0"                             \
-       "addip=setenv bootargs $(bootargs) "                            \
-               "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
-               ":$(hostname)::off panic=1\0"                           \
-       "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)"  \
-               " $(optargs)\0"                                         \
-       "flash_self=run ramargs addip addcon;"                          \
-               "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
-       "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;"          \
-               "bootm\0"                                               \
-       "rootpath=/tftpboot/abg405/target_root\0"                       \
-       "img=/tftpboot/abg405/pImage\0"                                 \
-       "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0"                \
-       "update=protect off fff80000 ffffffff;era fff80000 ffffffff;"   \
-               "cp.b 100000 fff80000 80000\0"                          \
-       "ipaddr=10.0.111.111\0"                                         \
-       "netmask=255.255.0.0\0"                                         \
-       "serverip=10.0.0.190\0"                                         \
-       "splashimage=ffe80000\0"                                        \
-       "usb_load="CONFIG_SYS_USB_LOAD_COMMAND"\0"                              \
-       "usb_self="CONFIG_SYS_USB_SELF_COMMAND"\0"                              \
-       "usbargs="CONFIG_SYS_USB_ARGS"\0"                                       \
-       "bootlimit="CONFIG_SYS_BOOTLIMIT"\0"                                    \
-       "altbootcmd="CONFIG_SYS_ALT_BOOTCOMMAND"\0"                             \
-       ""
-#define CONFIG_BOOTCOMMAND     "run flash_self;reset"
-
-#define CONFIG_ETHADDR         00:02:27:8e:00:00
-
-#define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
-
-#undef  CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII             1       /* MII PHY management           */
-#define CONFIG_PHY_ADDR                0       /* PHY address                  */
-#define CONFIG_LXT971_NO_SLEEP 1
-#define CONFIG_RESET_PHY_R     1       /* use reset_phy() */
-
-#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_USB
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_AUTO_UPDATE     1       /* autoupdate via CF or USB */
-
-#undef  CONFIG_WATCHDOG                        /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818            /* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0     1       /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING 1       /* add command line history */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS     16              /* max number of command args */
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV      1       /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START       0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX      1       /* Use UART0                    */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-#define CONFIG_SYS_NS16550_CLK         get_serial_clock()
-
-#define CONFIG_SYS_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE      \
-       { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
-        57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR   0x100000        /* default load address */
-#define CONFIG_SYS_EXTBDINFO   1               /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
-
-/* Only interrupt boot if space is pressed */
-/* If a long serial cable is connected but */
-/* other end is dead, garbage will be read */
-#define CONFIG_AUTOBOOT_KEYED  1
-#define CONFIG_AUTOBOOT_PROMPT \
-       "Press SPACE to abort autoboot in %d seconds\n", bootdelay
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#define CONFIG_VERSION_VARIABLE        1       /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
-
-/*
- * PCI stuff
- */
-#define PCI_HOST_ADAPTER       0       /* configure as pci adapter     */
-#define PCI_HOST_FORCE         1       /* configure as pci host        */
-#define PCI_HOST_AUTO          2       /* detected via arbiter enable  */
-
-#define CONFIG_PCI                     /* include pci support          */
-#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function     */
-#define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
-                                       /* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW           /* print pci devices @ startup  */
-#define CONFIG_PCI_SKIP_HOST_BRIDGE 1
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*
- * IDE/ATA stuff
- */
-#undef  CONFIG_IDE_8xx_DIRECT          /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                 /* no led for ide supported */
-#define CONFIG_IDE_RESET       1       /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS          1               /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE       (CONFIG_SYS_IDE_MAXBUS) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR       0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET     0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET      0x0000  /* Offset for normal register access */
-#define CONFIG_SYS_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers */
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE          0x00000000
-#define CONFIG_SYS_MONITOR_BASE        0xFFF80000
-#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN          (2*1024*1024)   /* Reserve 2MB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ           (8 << 20)       /* Init. Memory map for Linux */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_BASE          0xFE000000
-#define CONFIG_SYS_FLASH_CFI           1       /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER        1       /* Use the common driver */
-#define CONFIG_SYS_MAX_FLASH_SECT      256     /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
-#define CONFIG_SYS_FLASH_QUIET_TEST    1
-#define CONFIG_SYS_FLASH_INCREMENT     0x01000000
-#define CONFIG_SYS_FLASH_PROTECTION    1       /* use hardware protection */
-#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { \
-                               {0xfe000000, 0x500000}, \
-                               {0xffe80000, 0x180000} \
-                               }
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_BANKS_LIST    { \
-                               CONFIG_SYS_FLASH_BASE, \
-                               CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT \
-                               }
-#define CONFIG_SYS_FLASH_EMPTY_INFO    /* print 'E' for empty sector on flinfo */
-
-/*
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM        1       /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET              0x000   /* environment starts at the */
-                                       /* beginning of the EEPROM */
-#define CONFIG_ENV_SIZE                0x800   /* 2048 bytes may be used for env vars*/
-#define CONFIG_ENV_OVERWRITE   1       /* allow overwriting vendor vars */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR     0xF0000500      /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE          242             /* NVRAM size */
-
-/*
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0          100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0          0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW    0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has */
-                                       /* 16 byte page write mode using*/
-                                       /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10 /* and takes up to 10 msec */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define FLASH0_BA       (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT) /* FLASH 0 BA */
-#define FLASH1_BA       CONFIG_SYS_FLASH_BASE      /* FLASH 1 Base Address          */
-#define CAN_BA          0xF0000000          /* CAN Base Address              */
-#define DUART0_BA       0xF0000400          /* DUART Base Address            */
-#define DUART1_BA       0xF0000408          /* DUART Base Address            */
-#define RTC_BA          0xF0000500          /* RTC Base Address              */
-#define PS2_BA          0xF0000600          /* PS/2 Base Address             */
-#define CF_BA           0xF0100000          /* CompactFlash Base Address     */
-#define FPGA_BA         0xF0100100          /* FPGA internal Base Address    */
-#define FUJI_BA         0xF0100200          /* Fuji internal Base Address    */
-#define PCMCIA1_BA      0x20000000          /* PCMCIA Slot 1 Base Address    */
-#define PCMCIA2_BA      0x28000000          /* PCMCIA Slot 2 Base Address    */
-#define VGA_BA          0xF1000000          /* Epson VGA Base Address        */
-
-#define CONFIG_SYS_FPGA_BASE_ADDR      FPGA_BA     /* FPGA internal Base Address    */
-
-/* Memory Bank 0 (Flash Bank 0) initialization                               */
-#define CONFIG_SYS_EBC_PB0AP   0x92015480
-#define CONFIG_SYS_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
-#define CONFIG_SYS_EBC_PB0AP_HWREV8 CONFIG_SYS_EBC_PB0AP
-#define CONFIG_SYS_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */
-
-/* Memory Bank 1 (Flash Bank 1) initialization                               */
-#define CONFIG_SYS_EBC_PB1AP   0x92015480
-#define CONFIG_SYS_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization                           */
-#define CONFIG_SYS_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
-
-/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
-#define CONFIG_SYS_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (PCMCIA Slot 1) initialization                                 */
-#define CONFIG_SYS_EBC_PB4AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB4CR   PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 5 (Epson VGA) initialization                                     */
-#define CONFIG_SYS_EBC_PB5AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CONFIG_SYS_EBC_PB5CR   VGA_BA | 0x5A000    /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 6 (PCMCIA Slot 2) initialization                                 */
-#define CONFIG_SYS_EBC_PB6AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB6CR   PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
-
-/*
- * FPGA stuff
- */
-
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_CTRL           0x008
-#define CONFIG_SYS_FPGA_CTRL2          0x00a
-
-/* FPGA Control Reg */
-#define CONFIG_SYS_FPGA_CTRL_CF_RESET  0x0001
-#define CONFIG_SYS_FPGA_CTRL_WDI       0x0002
-#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
-
-#define CONFIG_SYS_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CONFIG_SYS_FPGA_MAX_SIZE       80*1024     /* 80kByte is enough for XC2S50  */
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CONFIG_SYS_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CONFIG_SYS_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CONFIG_SYS_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
-
-/*
- * LCD Setup
- */
-#define CONFIG_SYS_LCD_BIG_MEM         (VGA_BA + 0x200000) /* S1D13806 Mem Base */
-#define CONFIG_SYS_LCD_BIG_REG         VGA_BA /* S1D13806 Reg Base */
-
-#define CONFIG_LCD_BIG         2 /* Epson S1D13806 used */
-
-/* Image information... */
-#define CONFIG_LCD_USED                CONFIG_LCD_BIG
-
-#define CONFIG_SYS_LCD_MEM             CONFIG_SYS_LCD_BIG_MEM
-#define CONFIG_SYS_LCD_REG             CONFIG_SYS_LCD_BIG_REG
-
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM      1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR       0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE       0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* reserve some memory for BOOT limit info */
-#define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - 16)
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
-#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8)
-#endif
-
-/*
- * PCI OHCI controller
- */
-#define CONFIG_USB_OHCI_NEW    1
-#define CONFIG_PCI_OHCI                1
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME  "ohci_pci"
-#define CONFIG_USB_STORAGE     1
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
-
-#endif /* __CONFIG_H */