ath9k: Add support for AR9462 2.1
authorSujith Manoharan <c_manoha@qca.qualcomm.com>
Mon, 24 Jun 2013 12:48:46 +0000 (18:18 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 24 Jun 2013 18:44:28 +0000 (14:44 -0400)
Various parts of the HW code are applicable for
both v2.0 and v2.1.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
drivers/net/wireless/ath/ath9k/ar9003_phy.c
drivers/net/wireless/ath/ath9k/ar9003_phy.h
drivers/net/wireless/ath/ath9k/hw.c

index 1e86977d33220865faa98d25c8aa8619828f3b2a..d105e43d22e165bc632d9fd41f9edabd04afaa8b 100644 (file)
@@ -3606,7 +3606,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
         *   7:4 R/W  SWITCH_TABLE_COM_SPDT_WLAN_IDLE
         * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
         */
-       if (AR_SREV_9462_20(ah) || AR_SREV_9565(ah)) {
+       if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) {
                value = ar9003_switch_com_spdt_get(ah, is2ghz);
                REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
                                AR_SWITCH_TABLE_COM_SPDT_ALL, value);
@@ -4059,8 +4059,9 @@ static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah)
 {
        u32 data, ko, kg;
 
-       if (!AR_SREV_9462_20(ah))
+       if (!AR_SREV_9462_20_OR_LATER(ah))
                return;
+
        ar9300_otp_read_word(ah, 1, &data);
        ko = data & 0xff;
        kg = (data >> 8) & 0xff;
@@ -4752,7 +4753,7 @@ tempslope:
                              AR_PHY_TPC_19_ALPHA_THERM, temp_slope);
        }
 
-       if (AR_SREV_9462_20(ah))
+       if (AR_SREV_9462_20_OR_LATER(ah))
                REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
                              AR_PHY_TPC_19_B1_ALPHA_THERM, temp_slope);
 
index df84d20e109282faf44cd454c473852b5f9bc5b2..1f694ab3cc78ba2ede3f7ca4b192c2e7dded96ab 100644 (file)
@@ -743,7 +743,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
                ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
                ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
-               if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
+               if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
                        ar9003_hw_prog_ini(ah,
                                           &ah->ini_radio_post_sys2ant,
                                           modesIndex);
@@ -754,7 +754,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
         */
        REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 
-       if (AR_SREV_9462_20(ah)) {
+       if (AR_SREV_9462_20_OR_LATER(ah)) {
                /*
                 * CUS217 mix LNA mode.
                 */
@@ -1512,7 +1512,7 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
        ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
        ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
 
-       if (AR_SREV_9462_20(ah))
+       if (AR_SREV_9462_20_OR_LATER(ah))
                ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
                                   modesIndex);
 
index 5013c731f9f6de2bb79a9a4d86f4fd0323ef7a88..d4d39f305a0b0177fbb7289a360f6d75849a58ea 100644 (file)
 #define AR_PHY_TPC_5_B1         (AR_SM1_BASE + 0x208)
 #define AR_PHY_TPC_6_B1         (AR_SM1_BASE + 0x20c)
 #define AR_PHY_TPC_11_B1        (AR_SM1_BASE + 0x220)
-#define AR_PHY_PDADC_TAB_1     (AR_SM1_BASE + (AR_SREV_AR9462(ah) ? \
+#define AR_PHY_PDADC_TAB_1     (AR_SM1_BASE + (AR_SREV_9462_20_OR_LATER(ah) ? \
                                        0x280 : 0x240))
 #define AR_PHY_TPC_19_B1       (AR_SM1_BASE + 0x240)
 #define AR_PHY_TPC_19_B1_ALPHA_THERM           0xff
 #define AR_GLB_GPIO_CONTROL    (AR_GLB_BASE)
 #define AR_PHY_GLB_CONTROL     (AR_GLB_BASE + 0x44)
 #define AR_GLB_SCRATCH(_ah)    (AR_GLB_BASE + \
-                                       (AR_SREV_9462_20(_ah) ? 0x4c : 0x50))
+                                       (AR_SREV_9462_20_OR_LATER(_ah) ? 0x4c : 0x50))
 #define AR_GLB_STATUS          (AR_GLB_BASE + 0x48)
 
 /*
index 5324c3346af8a9dfdc4729843d953f22f8dc56ba..4ca0cb06010609ca490bfe4404883bde2ac85d66 100644 (file)
@@ -2599,7 +2599,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
                        pCap->hw_caps |= ATH9K_HW_CAP_MCI;
 
-               if (AR_SREV_9462_20(ah))
+               if (AR_SREV_9462_20_OR_LATER(ah))
                        pCap->hw_caps |= ATH9K_HW_CAP_RTT;
        }