From: John Crispin <blogic@openwrt.org>
Date: Mon, 4 Aug 2014 20:36:29 +0200
-Subject: [PATCH 2/3] GPIO: MIPS: ralink: add gpio driver for ralink SoC
+Subject: [PATCH 2/2] GPIO: MIPS: ralink: add gpio driver for ralink SoC
Add gpio driver for Ralink SoC. This driver makes the gpio core on
RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
- drivers/gpio/Kconfig | 7 +
+ drivers/gpio/Kconfig | 8 ++
drivers/gpio/Makefile | 1 +
- drivers/gpio/gpio-ralink.c | 273 +++++++++++++++++++++++++++++++++++++
- 3 files changed, 281 insertions(+)
+ drivers/gpio/gpio-ralink.c | 230 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 239 insertions(+)
create mode 100644 drivers/gpio/gpio-ralink.c
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
-@@ -594,6 +594,13 @@ config GPIO_SNPS_CREG
- where only several fields in register belong to GPIO lines and
- each GPIO line owns a field with different length and on/off value.
+@@ -509,6 +509,14 @@ config GPIO_PXA
+ help
+ Say yes here to support the PXA GPIO device.
+config GPIO_RALINK
+ bool "Ralink GPIO Support"
-+ depends on RALINK
++ depends on SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620
+ select GPIO_GENERIC
++ select GPIOLIB_IRQCHIP
+ help
+ Say yes here to support the Ralink SoC GPIO device
+
- config GPIO_SPEAR_SPICS
- bool "ST SPEAr13xx SPI Chip Select as GPIO support"
- depends on PLAT_SPEAR
+ config GPIO_RCAR
+ tristate "Renesas R-Car and RZ/G GPIO support"
+ depends on ARCH_RENESAS || COMPILE_TEST
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -130,6 +130,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisos
obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
--- /dev/null
+++ b/drivers/gpio/gpio-ralink.c
-@@ -0,0 +1,273 @@
+@@ -0,0 +1,230 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
-+#include <linux/module.h>
-+#include <linux/io.h>
++#include <linux/err.h>
+#include <linux/gpio/driver.h>
-+#include <linux/spinlock.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_irq.h>
-+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
+
+enum ralink_gpio_reg {
+ GPIO_REG_INT = 0,
+
+ spinlock_t lock;
+ void __iomem *membase;
-+ struct irq_domain *domain;
-+ int irq;
++ int gpio_irq;
+
+ u32 rising;
+ u32 falling;
+};
+
-+#define MAP_MAX 4
-+static struct irq_domain *irq_map[MAP_MAX];
-+static int irq_map_count;
-+static atomic_t irq_refcount = ATOMIC_INIT(0);
-+
-+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
-+{
-+ struct ralink_gpio_chip *rg;
-+
-+ rg = container_of(chip, struct ralink_gpio_chip, chip);
-+
-+ return rg;
-+}
-+
+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
+{
+ iowrite32(val, rg->membase + rg->regs[reg]);
+ return ioread32(rg->membase + rg->regs[reg]);
+}
+
-+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+ if (rg->irq < 1)
-+ return -1;
-+
-+ return irq_create_mapping(rg->domain, pin);
-+}
-+
-+static void ralink_gpio_irq_handler(struct irq_desc *desc)
-+{
-+ int i;
-+
-+ for (i = 0; i < irq_map_count; i++) {
-+ struct irq_domain *domain = irq_map[i];
-+ struct ralink_gpio_chip *rg;
-+ unsigned long pending;
-+ int bit;
-+
-+ rg = (struct ralink_gpio_chip *) domain->host_data;
-+ pending = rt_gpio_r32(rg, GPIO_REG_INT);
-+
-+ for_each_set_bit(bit, &pending, rg->chip.ngpio) {
-+ u32 map = irq_find_mapping(domain, bit);
-+ generic_handle_irq(map);
-+ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
-+ }
++static irqreturn_t ralink_gpio_irq_handler(int irq, void *data)
++{
++ struct gpio_chip *gc = data;
++ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
++ irqreturn_t ret = IRQ_NONE;
++ unsigned long pending;
++ int bit;
++
++ pending = rt_gpio_r32(rg, GPIO_REG_INT);
++ for_each_set_bit(bit, &pending, rg->chip.ngpio) {
++ generic_handle_domain_irq(gc->irq.domain, bit);
++ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
++ ret |= IRQ_HANDLED;
+ }
++
++ return ret;
+}
+
+static void ralink_gpio_irq_unmask(struct irq_data *d)
+{
-+ struct ralink_gpio_chip *rg;
++ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
++ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
+ unsigned long flags;
+ u32 rise, fall;
+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
+ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
+ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
+
+
+static void ralink_gpio_irq_mask(struct irq_data *d)
+{
-+ struct ralink_gpio_chip *rg;
++ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
++ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
+ unsigned long flags;
+ u32 rise, fall;
+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
+ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
+ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
+
+
+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
+{
-+ struct ralink_gpio_chip *rg;
++ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
++ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
+ u32 mask = BIT(d->hwirq);
+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+
+ if (type == IRQ_TYPE_PROBE) {
+ if ((rg->rising | rg->falling) & mask)
+ return 0;
+}
+
+static struct irq_chip ralink_gpio_irq_chip = {
-+ .name = "GPIO",
++ .name = "gpio-ralink",
+ .irq_unmask = ralink_gpio_irq_unmask,
+ .irq_mask = ralink_gpio_irq_mask,
+ .irq_mask_ack = ralink_gpio_irq_mask,
+ .irq_set_type = ralink_gpio_irq_type,
++ .flags = IRQCHIP_IMMUTABLE,
++ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
-+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
-+ irq_set_handler_data(irq, d);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops irq_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = gpio_map,
-+};
-+
-+static void ralink_gpio_irq_init(struct device_node *np,
-+ struct ralink_gpio_chip *rg)
-+{
-+ if (irq_map_count >= MAP_MAX)
-+ return;
-+
-+ rg->irq = irq_of_parse_and_map(np, 0);
-+ if (!rg->irq)
-+ return;
-+
-+ rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
-+ &irq_domain_ops, rg);
-+ if (!rg->domain) {
-+ dev_err(rg->chip.parent, "irq_domain_add_linear failed\n");
-+ return;
-+ }
-+
-+ irq_map[irq_map_count++] = rg->domain;
-+
-+ rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
-+ rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
-+
-+ if (!atomic_read(&irq_refcount))
-+ irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
-+ atomic_inc(&irq_refcount);
-+
-+ dev_info(rg->chip.parent, "registering %d irq handlers\n", rg->chip.ngpio);
-+}
-+
+static int ralink_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ NULL, 0);
+ if (ret)
+ return dev_err_probe(dev, ret, "bgpio_init() failed\n");
-+ rg->chip.request = gpiochip_generic_request;
-+ rg->chip.to_irq = ralink_gpio_to_irq;
-+ rg->chip.free = gpiochip_generic_free;
+
+ /* set polarity to low for all lines */
+ rt_gpio_w32(rg, GPIO_REG_POL, 0);
+
-+ ralink_gpio_irq_init(np, rg);
++ rg->gpio_irq = platform_get_irq(pdev, 0);
++ if (rg->gpio_irq < 0)
++ return rg->gpio_irq;
++
++ if (rg->gpio_irq) {
++ struct gpio_irq_chip *girq;
++
++ /*
++ * Directly request the irq here instead of passing
++ * a flow-handler because the irq is shared.
++ */
++ ret = devm_request_irq(dev, rg->gpio_irq,
++ ralink_gpio_irq_handler, IRQF_SHARED,
++ NULL, &rg->chip);
++ if (ret) {
++ dev_err(dev, "Error requesting IRQ %d: %d\n",
++ rg->gpio_irq, ret);
++ return ret;
++ }
++
++ girq = &rg->chip.irq;
++ gpio_irq_chip_set_chip(girq, &ralink_gpio_irq_chip);
++ /* This will let us handle the parent IRQ in the driver */
++ girq->parent_handler = NULL;
++ girq->num_parents = 0;
++ girq->parents = NULL;
++ girq->default_type = IRQ_TYPE_NONE;
++ girq->handler = handle_simple_irq;
++
++ rt_gpio_w32(rg, GPIO_REG_RENA, 0);
++ rt_gpio_w32(rg, GPIO_REG_FENA, 0);
++ }
+
+ return devm_gpiochip_add_data(dev, &rg->chip, rg);
+}
+static struct platform_driver ralink_gpio_driver = {
+ .probe = ralink_gpio_probe,
+ .driver = {
-+ .name = "rt2880_gpio",
-+ .owner = THIS_MODULE,
++ .name = "ralink_gpio",
+ .of_match_table = ralink_gpio_match,
+ },
+};
projects / openwrt / openwrt.git / commitdiff