drm/amdgpu/vcn:Update SPG mode VCN memory control

Update Static Power Gate  mode VCN memory control

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 624a255cffa3fad4d932054fad09fd644c7ebf07..73301a9dc37da7171868ff7c215e780d016c4343 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -787,13 +787,12 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
        mdelay(5);
 
        /* initialize VCN memory controller */
-       WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
-               (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
-               UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
-               UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
-               UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
-               UVD_LMI_CTRL__REQ_MODE_MASK |
-               0x00100000L);
+       tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
+       WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp                |
+               UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+               UVD_LMI_CTRL__MASK_MC_URGENT_MASK                       |
+               UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK            |
+               UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 
 #ifdef __BIG_ENDIAN
        /* swap (8 in 32) RB and IB */