mtd: rawnand: Get rid of chip->bits_per_cell

Now that we inherit from nand_device, we can use
nand_device->memorg.bits_per_cell instead of having our own field at
the nand_chip level.

Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 035b9cf327a6f3e8b0ee3d2ebee03ffdcbba96b5..77c0e0ef61b13ab06fff9b2f10136c70781830b1 100644 (file)
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4457,7 +4457,6 @@ void nand_decode_ext_id(struct nand_chip *chip)
 
        /* The 3rd id byte holds MLC / multichip data */
        memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
-       chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
        /* The 4th id byte is the important one */
        extid = id_data[3];
 
@@ -4501,7 +4500,6 @@ static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
 
        /* All legacy ID NAND are small-page, SLC */
        memorg->bits_per_cell = 1;
-       chip->bits_per_cell = 1;
 }
 
 /*
@@ -4544,7 +4542,6 @@ static bool find_full_id_nand(struct nand_chip *chip,
                mtd->oobsize = memorg->oobsize;
 
                memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
-               chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
                chip->chipsize = (uint64_t)type->chipsize << 20;
                memorg->eraseblocks_per_lun =
                        DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
@@ -4584,7 +4581,6 @@ static void nand_manufacturer_detect(struct nand_chip *chip)
 
                /* The 3rd id byte holds MLC / multichip data */
                memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
-               chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
                chip->manufacturer.desc->ops->detect(chip);
        } else {
                nand_decode_ext_id(chip);

diff --git a/drivers/mtd/nand/raw/nand_hynix.c b/drivers/mtd/nand/raw/nand_hynix.c
index 94ea8c593589c83cf2c58ab3a3b32c4215e97888..272b934dffb7649b32a976d2c06608a9b2c41352 100644 (file)
--- a/drivers/mtd/nand/raw/nand_hynix.c
+++ b/drivers/mtd/nand/raw/nand_hynix.c
@@ -592,7 +592,7 @@ static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
        u8 nand_tech;
 
        /* We need scrambling on all TLC NANDs*/
-       if (chip->bits_per_cell > 2)
+       if (nanddev_bits_per_cell(&chip->base) > 2)
                chip->options |= NAND_NEED_SCRAMBLING;
 
        /* And on MLC NANDs with sub-3xnm process */

diff --git a/drivers/mtd/nand/raw/nand_jedec.c b/drivers/mtd/nand/raw/nand_jedec.c
index 61e33ee7ee19b1cb201f2451502f5cc419d38871..030f178c7a978b688a0ee42646d07a0e2b71dc05 100644 (file)
--- a/drivers/mtd/nand/raw/nand_jedec.c
+++ b/drivers/mtd/nand/raw/nand_jedec.c
@@ -104,7 +104,6 @@ int nand_jedec_detect(struct nand_chip *chip)
        chip->chipsize = memorg->eraseblocks_per_lun;
        chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
        memorg->bits_per_cell = p->bits_per_cell;
-       chip->bits_per_cell = p->bits_per_cell;
 
        if (le16_to_cpu(p->features) & JEDEC_FEATURE_16_BIT_BUS)
                chip->options |= NAND_BUSWIDTH_16;

diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c
index b85e1c13b79e0fa9a0a82e5ad8bf9461bd6f8652..98ce6575aa64a74d8307564a988bc5bab604b4e8 100644 (file)
--- a/drivers/mtd/nand/raw/nand_micron.c
+++ b/drivers/mtd/nand/raw/nand_micron.c
@@ -385,7 +385,7 @@ static int micron_supports_on_die_ecc(struct nand_chip *chip)
        if (!chip->parameters.onfi)
                return MICRON_ON_DIE_UNSUPPORTED;
 
-       if (chip->bits_per_cell != 1)
+       if (nanddev_bits_per_cell(&chip->base) != 1)
                return MICRON_ON_DIE_UNSUPPORTED;
 
        /*

diff --git a/drivers/mtd/nand/raw/nand_onfi.c b/drivers/mtd/nand/raw/nand_onfi.c
index 3ca9c8923a309c5e7a4642c23833ec7e11663f34..a6b9fc9a335b7d4ce2572d9b0ec22fe365af7886 100644 (file)
--- a/drivers/mtd/nand/raw/nand_onfi.c
+++ b/drivers/mtd/nand/raw/nand_onfi.c
@@ -249,7 +249,6 @@ int nand_onfi_detect(struct nand_chip *chip)
        chip->chipsize = memorg->eraseblocks_per_lun;
        chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
        memorg->bits_per_cell = p->bits_per_cell;
-       chip->bits_per_cell = p->bits_per_cell;
 
        if (le16_to_cpu(p->features) & ONFI_FEATURE_16_BIT_BUS)
                chip->options |= NAND_BUSWIDTH_16;

diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 9d0cdae4e2040516d710fcf7fd481fdfd650a97f..b2570adab9113a70c3d53b410d2acd5fd268d3f4 100644 (file)
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -992,7 +992,6 @@ struct nand_legacy {
  * @badblockbits:      [INTERN] minimum number of set bits in a good block's
  *                     bad block marker position; i.e., BBM == 11110111b is
  *                     not bad when badblockbits == 7
- * @bits_per_cell:     [INTERN] number of bits per cell. i.e., 1 means SLC.
  * @ecc_strength_ds:   [INTERN] ECC correctability from the datasheet.
  *                     Minimum amount of bit errors per @ecc_step_ds guaranteed
  *                     to be correctable. If unknown, set to zero.
@@ -1064,7 +1063,6 @@ struct nand_chip {
        } pagecache;
 
        int subpagesize;
-       uint8_t bits_per_cell;
        uint16_t ecc_strength_ds;
        uint16_t ecc_step_ds;
        int onfi_timing_mode_default;
@@ -1236,9 +1234,9 @@ int nand_create_bbt(struct nand_chip *chip);
  */
 static inline bool nand_is_slc(struct nand_chip *chip)
 {
-       WARN(chip->bits_per_cell == 0,
+       WARN(nanddev_bits_per_cell(&chip->base) == 0,
             "chip->bits_per_cell is used uninitialized\n");
-       return chip->bits_per_cell == 1;
+       return nanddev_bits_per_cell(&chip->base) == 1;
 }
 
 /**