SUBTARGETS:=generic
KERNEL_PATCHVER:=5.15
+KERNEL_TESTING_PATCHVER:=6.1
define Target/Description
Build firmware images for Broadcom BCM4908 SoC family routers.
--- /dev/null
+CONFIG_64BIT=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_B53=y
+CONFIG_BCM4908_ENET=y
+CONFIG_BCM7038_WDT=y
+CONFIG_BCM7XXX_PHY=y
+CONFIG_BCM_NET_PHYLIB=y
+CONFIG_BCM_PMB=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_PM=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CLK_BCM_63XX=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_REMAP=y
+CONFIG_DTC=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GRO_CELLS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_BRCMSTB=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_BCM63138=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BCM_UNIMAC=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MTD_BRCM_U_BOOT=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_BRCMNAND_BCMBCA=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_OF_PARTS_BCM4908=y
+# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPLIT_CFE_BOOTFS=y
+# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_BCM_SF2=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVMEM_U_BOOT_ENV=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PADATA=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_PHY_BRCM_SATA is not set
+CONFIG_PHY_BRCM_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCM4908=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELOCATABLE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SRCU=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB_SUPPORT=y
+CONFIG_VMAP_STACK=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+From 68064196cffea33f090bd2e8d81cd5e20107ecf1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 3 Nov 2022 11:53:16 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TWD block timer
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 TWD contains block with 4 timers. Add binding for it.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20221103105316.21294-1-zajec5@gmail.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+@@ -283,6 +283,11 @@
+ #address-cells = <1>;
+ #size-cells = <1>;
+
++ timer@0 {
++ compatible = "brcm,bcm63138-timer";
++ reg = <0x0 0x28>;
++ };
++
+ watchdog@28 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x28 0x8>;
--- /dev/null
+From 4f9fb09175e87a233787a2dee1e5dabb14deb022 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 3 Nov 2022 12:00:15 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm6858: add TWD block
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM6858 contains TWD block with timers, watchdog, and reset subblocks.
+Describe it.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20221103110015.21761-1-zajec5@gmail.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+@@ -109,6 +109,25 @@
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x62000>;
+
++ twd: timer-mfd@400 {
++ compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
++ reg = <0x400 0x4c>;
++ ranges = <0x0 0x400 0x4c>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ timer@0 {
++ compatible = "brcm,bcm63138-timer";
++ reg = <0x0 0x28>;
++ };
++
++ watchdog@28 {
++ compatible = "brcm,bcm6345-wdt";
++ reg = <0x28 0x8>;
++ };
++ };
++
+ uart0: serial@640 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x640 0x18>;
--- /dev/null
+From e567e58d6819adc002c57b81e16b88da24d3b4aa Mon Sep 17 00:00:00 2001
+From: Pierre Gondois <pierre.gondois@arm.com>
+Date: Tue, 22 Nov 2022 17:32:07 +0100
+Subject: [PATCH] arm64: dts: Update cache properties for broadcom
+
+The DeviceTree Specification v0.3 specifies that the cache node
+'compatible' and 'cache-level' properties are 'required'. Cf.
+s3.8 Multi-level and Shared Cache Nodes
+The 'cache-unified' property should be present if one of the
+properties for unified cache is present ('cache-size', ...).
+
+Update the Device Trees accordingly.
+
+Acked-by: William Zhang <william.zhang@broadcom.com>
+Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
+Link: https://lore.kernel.org/r/20221122163208.3810985-3-pierre.gondois@arm.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
+ arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
+ arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++
+ 9 files changed, 12 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+@@ -63,6 +63,7 @@
+
+ l2: l2-cache0 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+@@ -51,6 +51,7 @@
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+@@ -35,6 +35,7 @@
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+@@ -51,6 +51,7 @@
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
+@@ -51,6 +51,7 @@
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+@@ -35,6 +35,7 @@
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+@@ -50,6 +50,7 @@
+ };
+ L2_0: l2-cache0 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
++++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
+@@ -79,6 +79,7 @@
+
+ CLUSTER0_L2: l2-cache@0 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
++++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+@@ -108,18 +108,22 @@
+
+ CLUSTER0_L2: l2-cache@0 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+
+ CLUSTER1_L2: l2-cache@100 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+
+ CLUSTER2_L2: l2-cache@200 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+
+ CLUSTER3_L2: l2-cache@300 {
+ compatible = "cache";
++ cache-level = <2>;
+ };
+ };
+
--- /dev/null
+From f5d83b714e304d5f3229da434af2eeea033c4f5d Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Mon, 6 Feb 2023 22:58:15 -0800
+Subject: [PATCH] arm64: dts: broadcom: bcmbca: Add spi controller node
+
+Add support for HSSPI controller in ARMv8 chip dts files.
+
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 18 +++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 20 +++++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 19 ++++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 19 ++++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 20 +++++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 18 +++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 18 +++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm94908.dts | 4 ++++
+ .../boot/dts/broadcom/bcmbca/bcm94912.dts | 4 ++++
+ .../boot/dts/broadcom/bcmbca/bcm963146.dts | 4 ++++
+ .../boot/dts/broadcom/bcmbca/bcm963158.dts | 4 ++++
+ .../boot/dts/broadcom/bcmbca/bcm96813.dts | 4 ++++
+ .../boot/dts/broadcom/bcmbca/bcm96856.dts | 4 ++++
+ .../boot/dts/broadcom/bcmbca/bcm96858.dts | 4 ++++
+ 14 files changed, 160 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+@@ -107,6 +107,12 @@
+ clock-frequency = <50000000>;
+ clock-output-names = "periph";
+ };
++
++ hsspi_pll: hsspi-pll {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <400000000>;
++ };
+ };
+
+ soc {
+@@ -531,6 +537,18 @@
+ #size-cells = <0>;
+ };
+
++ hsspi: spi@1000{
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
++ reg = <0x1000 0x600>;
++ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&hsspi_pll &hsspi_pll>;
++ clock-names = "hsspi", "pll";
++ num-cs = <8>;
++ status = "disabled";
++ };
++
+ nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+@@ -79,6 +79,7 @@
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
++
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+@@ -86,6 +87,12 @@
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
++
++ hsspi_pll: hsspi-pll {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <200000000>;
++ };
+ };
+
+ psci {
+@@ -117,6 +124,19 @@
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x800000>;
+
++ hsspi: spi@1000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
++ reg = <0x1000 0x600>, <0x2610 0x4>;
++ reg-names = "hsspi", "spim-ctrl";
++ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&hsspi_pll &hsspi_pll>;
++ clock-names = "hsspi", "pll";
++ num-cs = <8>;
++ status = "disabled";
++ };
++
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+@@ -60,6 +60,7 @@
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
++
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+@@ -67,6 +68,12 @@
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
++
++ hsspi_pll: hsspi-pll {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <200000000>;
++ };
+ };
+
+ psci {
+@@ -99,6 +106,18 @@
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x800000>;
+
++ hsspi: spi@1000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";
++ reg = <0x1000 0x600>;
++ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&hsspi_pll &hsspi_pll>;
++ clock-names = "hsspi", "pll";
++ num-cs = <8>;
++ status = "disabled";
++ };
++
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+@@ -79,6 +79,7 @@
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
++
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+@@ -86,6 +87,12 @@
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
++
++ hsspi_pll: hsspi-pll {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <400000000>;
++ };
+ };
+
+ psci {
+@@ -117,6 +124,18 @@
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x800000>;
+
++ hsspi: spi@1000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";
++ reg = <0x1000 0x600>;
++ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&hsspi_pll &hsspi_pll>;
++ clock-names = "hsspi", "pll";
++ num-cs = <8>;
++ status = "disabled";
++ };
++
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
+@@ -79,6 +79,7 @@
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
++
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+@@ -86,6 +87,12 @@
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
++
++ hsspi_pll: hsspi-pll {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <200000000>;
++ };
+ };
+
+ psci {
+@@ -117,6 +124,19 @@
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x800000>;
+
++ hsspi: spi@1000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";
++ reg = <0x1000 0x600>, <0x2610 0x4>;
++ reg-names = "hsspi", "spim-ctrl";
++ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&hsspi_pll &hsspi_pll>;
++ clock-names = "hsspi", "pll";
++ num-cs = <8>;
++ status = "disabled";
++ };
++
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+@@ -60,6 +60,12 @@
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
++
++ hsspi_pll: hsspi-pll {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <400000000>;
++ };
+ };
+
+ psci {
+@@ -100,5 +106,17 @@
+ clock-names = "refclk";
+ status = "disabled";
+ };
++
++ hsspi: spi@1000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
++ reg = <0x1000 0x600>;
++ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&hsspi_pll &hsspi_pll>;
++ clock-names = "hsspi", "pll";
++ num-cs = <8>;
++ status = "disabled";
++ };
+ };
+ };
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+@@ -78,6 +78,12 @@
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
++
++ hsspi_pll: hsspi-pll {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <400000000>;
++ };
+ };
+
+ psci {
+@@ -137,5 +143,17 @@
+ clock-names = "refclk";
+ status = "disabled";
+ };
++
++ hsspi: spi@1000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
++ reg = <0x1000 0x600>;
++ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&hsspi_pll &hsspi_pll>;
++ clock-names = "hsspi", "pll";
++ num-cs = <8>;
++ status = "disabled";
++ };
+ };
+ };
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
+@@ -28,3 +28,7 @@
+ &uart0 {
+ status = "okay";
+ };
++
++&hsspi {
++ status = "okay";
++};
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
+@@ -28,3 +28,7 @@
+ &uart0 {
+ status = "okay";
+ };
++
++&hsspi {
++ status = "okay";
++};
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
+@@ -28,3 +28,7 @@
+ &uart0 {
+ status = "okay";
+ };
++
++&hsspi {
++ status = "okay";
++};
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
+@@ -28,3 +28,7 @@
+ &uart0 {
+ status = "okay";
+ };
++
++&hsspi {
++ status = "okay";
++};
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
+@@ -28,3 +28,7 @@
+ &uart0 {
+ status = "okay";
+ };
++
++&hsspi {
++ status = "okay";
++};
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
+@@ -28,3 +28,7 @@
+ &uart0 {
+ status = "okay";
+ };
++
++&hsspi {
++ status = "okay";
++};
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
+@@ -28,3 +28,7 @@
+ &uart0 {
+ status = "okay";
+ };
++
++&hsspi {
++ status = "okay";
++};
--- /dev/null
+From 477cad715de1dfc256a20da3ed83b62f3cb2944d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 28 Feb 2023 15:45:18 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add on-SoC USB ports
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 has 3 USB controllers each with 2 USB ports. Home routers often
+have LEDs indicating state of selected USB ports. Describe those SoC USB
+ports to allow using them as LED trigger sources.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/all/20230228144520.21816-1-zajec5@gmail.com/
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 39 +++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+@@ -148,6 +148,19 @@
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb_phy PHY_TYPE_USB2>;
+ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ehci_port1: port@1 {
++ reg = <1>;
++ #trigger-source-cells = <0>;
++ };
++
++ ehci_port2: port@2 {
++ reg = <2>;
++ #trigger-source-cells = <0>;
++ };
+ };
+
+ ohci: usb@c400 {
+@@ -156,6 +169,19 @@
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb_phy PHY_TYPE_USB2>;
+ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ohci_port1: port@1 {
++ reg = <1>;
++ #trigger-source-cells = <0>;
++ };
++
++ ohci_port2: port@2 {
++ reg = <2>;
++ #trigger-source-cells = <0>;
++ };
+ };
+
+ xhci: usb@d000 {
+@@ -164,6 +190,19 @@
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb_phy PHY_TYPE_USB3>;
+ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ xhci_port1: port@1 {
++ reg = <1>;
++ #trigger-source-cells = <0>;
++ };
++
++ xhci_port2: port@2 {
++ reg = <2>;
++ #trigger-source-cells = <0>;
++ };
+ };
+
+ bus@80000 {
--- /dev/null
+From 889e53ccccc29ff4bf8d4c89cca34e8768845747 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 28 Feb 2023 15:45:19 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add Netgear R8000P USB
+ LED triggers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This device has 2 USB LEDs meant to be triggered by devices in relevant
+USB ports.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/all/20230228144520.21816-2-zajec5@gmail.com/
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
+@@ -58,12 +58,16 @@
+ function = "usb2";
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
++ trigger-sources = <&ohci_port1>, <&ehci_port1>;
++ linux,default-trigger = "usbport";
+ };
+
+ led-usb3 {
+ function = "usb3";
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
++ trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>;
++ linux,default-trigger = "usbport";
+ };
+
+ led-wifi {
--- /dev/null
+From e6d356b146b75f1f77621aab7950a1eb550859f9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 28 Feb 2023 15:45:20 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TP-Link C2300 USB
+ LED triggers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This device has 2 USB LEDs meant to be triggered by devices in relevant
+USB ports.
+
+While at it fix typo in USB LED name.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/all/20230228144520.21816-3-zajec5@gmail.com/
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
+@@ -64,12 +64,16 @@
+ function = "usb2";
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
++ trigger-sources = <&ohci_port1>, <&ehci_port1>;
++ linux,default-trigger = "usbport";
+ };
+
+ led-usb3 {
+- function = "usbd3";
++ function = "usb3";
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
++ trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>;
++ linux,default-trigger = "usbport";
+ };
+
+ led-brightness {
--- /dev/null
+From 085679b15b5af65f9610f619afde41da0f966194 Mon Sep 17 00:00:00 2001
+From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
+Date: Wed, 16 Nov 2022 13:49:32 +0100
+Subject: [PATCH] mtd: parsers: refer to ARCH_BCMBCA instead of ARCH_BCM4908
+
+Commit dd5c672d7ca9 ("arm64: bcmbca: Merge ARCH_BCM4908 to ARCH_BCMBCA")
+removes config ARCH_BCM4908 as config ARCH_BCMBCA has the same intent.
+
+Probably due to concurrent development, commit 002181f5b150 ("mtd: parsers:
+add Broadcom's U-Boot parser") introduces 'Broadcom's U-Boot partition
+parser' that depends on ARCH_BCM4908, but this use was not visible during
+the config refactoring from the commit above. Hence, these two changes
+create a reference to a non-existing config symbol.
+
+Adjust the MTD_BRCM_U_BOOT definition to refer to ARCH_BCMBCA instead of
+ARCH_BCM4908 to remove the reference to the non-existing config symbol
+ARCH_BCM4908.
+
+Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20221116124932.4748-1-lukas.bulwahn@gmail.com
+---
+ drivers/mtd/parsers/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/parsers/Kconfig
++++ b/drivers/mtd/parsers/Kconfig
+@@ -22,7 +22,7 @@ config MTD_BCM63XX_PARTS
+
+ config MTD_BRCM_U_BOOT
+ tristate "Broadcom's U-Boot partition parser"
+- depends on ARCH_BCM4908 || COMPILE_TEST
++ depends on ARCH_BCMBCA || COMPILE_TEST
+ help
+ Broadcom uses a custom way of storing U-Boot environment variables.
+ They are placed inside U-Boot partition itself at unspecified offset.
--- /dev/null
+From 3a1cc23a75abcd9cea585eb84846507363d58397 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 25 Oct 2022 15:22:45 +0200
+Subject: [PATCH] net: broadcom: bcm4908_enet: use build_skb()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+RX code can be more efficient with the build_skb(). Allocating actual
+SKB around eth packet buffer - right before passing it up - results in
+a better cache usage.
+
+Without RPS (echo 0 > rps_cpus) BCM4908 NAT masq performance "jumps"
+between two speeds: ~900 Mbps and 940 Mbps (it's a 4 CPUs SoC). This
+change bumps the lower speed from 905 Mb/s to 918 Mb/s (tested using
+single stream iperf 2.0.5 traffic).
+
+There are more optimizations to consider. One obvious to try is GRO
+however as BCM4908 doesn't do hw csum is may actually lower performance.
+Sometimes. Some early testing:
+
+┌─────────────────────────────────┬─────────────────────┬────────────────────┐
+│ │ netif_receive_skb() │ napi_gro_receive() │
+├─────────────────────────────────┼─────────────────────┼────────────────────┤
+│ netdev_alloc_skb() │ 905 Mb/s │ 892 Mb/s │
+│ napi_alloc_frag() + build_skb() │ 918 Mb/s │ 917 Mb/s │
+└─────────────────────────────────┴─────────────────────┴────────────────────┘
+
+Another ideas:
+1. napi_build_skb()
+2. skb_copy_from_linear_data() for small packets
+
+Those need proper testing first though. That can be done later.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20221025132245.22871-1-zajec5@gmail.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 53 +++++++++++++-------
+ 1 file changed, 36 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -36,13 +36,24 @@
+ #define ENET_MAX_ETH_OVERHEAD (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
+ ETH_FCS_LEN + 4) /* 32 */
+
++#define ENET_RX_SKB_BUF_SIZE (NET_SKB_PAD + NET_IP_ALIGN + \
++ ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
++ ENET_MTU_MAX + ETH_FCS_LEN + 4)
++#define ENET_RX_SKB_BUF_ALLOC_SIZE (SKB_DATA_ALIGN(ENET_RX_SKB_BUF_SIZE) + \
++ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
++#define ENET_RX_BUF_DMA_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
++#define ENET_RX_BUF_DMA_SIZE (ENET_RX_SKB_BUF_SIZE - ENET_RX_BUF_DMA_OFFSET)
++
+ struct bcm4908_enet_dma_ring_bd {
+ __le32 ctl;
+ __le32 addr;
+ } __packed;
+
+ struct bcm4908_enet_dma_ring_slot {
+- struct sk_buff *skb;
++ union {
++ void *buf; /* RX */
++ struct sk_buff *skb; /* TX */
++ };
+ unsigned int len;
+ dma_addr_t dma_addr;
+ };
+@@ -260,22 +271,21 @@ static int bcm4908_enet_dma_alloc_rx_buf
+ u32 tmp;
+ int err;
+
+- slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD;
+-
+- slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
+- if (!slot->skb)
++ slot->buf = napi_alloc_frag(ENET_RX_SKB_BUF_ALLOC_SIZE);
++ if (!slot->buf)
+ return -ENOMEM;
+
+- slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
++ slot->dma_addr = dma_map_single(dev, slot->buf + ENET_RX_BUF_DMA_OFFSET,
++ ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE);
+ err = dma_mapping_error(dev, slot->dma_addr);
+ if (err) {
+ dev_err(dev, "Failed to map DMA buffer: %d\n", err);
+- kfree_skb(slot->skb);
+- slot->skb = NULL;
++ skb_free_frag(slot->buf);
++ slot->buf = NULL;
+ return err;
+ }
+
+- tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
++ tmp = ENET_RX_BUF_DMA_SIZE << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
+ tmp |= DMA_CTL_STATUS_OWN;
+ if (idx == enet->rx_ring.length - 1)
+ tmp |= DMA_CTL_STATUS_WRAP;
+@@ -315,11 +325,11 @@ static void bcm4908_enet_dma_uninit(stru
+
+ for (i = rx_ring->length - 1; i >= 0; i--) {
+ slot = &rx_ring->slots[i];
+- if (!slot->skb)
++ if (!slot->buf)
+ continue;
+ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
+- kfree_skb(slot->skb);
+- slot->skb = NULL;
++ skb_free_frag(slot->buf);
++ slot->buf = NULL;
+ }
+ }
+
+@@ -575,6 +585,7 @@ static int bcm4908_enet_poll_rx(struct n
+ while (handled < weight) {
+ struct bcm4908_enet_dma_ring_bd *buf_desc;
+ struct bcm4908_enet_dma_ring_slot slot;
++ struct sk_buff *skb;
+ u32 ctl;
+ int len;
+ int err;
+@@ -598,16 +609,24 @@ static int bcm4908_enet_poll_rx(struct n
+
+ if (len < ETH_ZLEN ||
+ (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
+- kfree_skb(slot.skb);
++ skb_free_frag(slot.buf);
+ enet->netdev->stats.rx_dropped++;
+ break;
+ }
+
+- dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
++ dma_unmap_single(dev, slot.dma_addr, ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE);
++
++ skb = build_skb(slot.buf, ENET_RX_SKB_BUF_ALLOC_SIZE);
++ if (unlikely(!skb)) {
++ skb_free_frag(slot.buf);
++ enet->netdev->stats.rx_dropped++;
++ break;
++ }
++ skb_reserve(skb, ENET_RX_BUF_DMA_OFFSET);
++ skb_put(skb, len - ETH_FCS_LEN);
++ skb->protocol = eth_type_trans(skb, enet->netdev);
+
+- skb_put(slot.skb, len - ETH_FCS_LEN);
+- slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
+- netif_receive_skb(slot.skb);
++ netif_receive_skb(skb);
+
+ enet->netdev->stats.rx_packets++;
+ enet->netdev->stats.rx_bytes += len;
--- /dev/null
+From 471ef777ec79baadc5cd9773d08f95f49cf5e2b1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 31 Oct 2022 11:48:56 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: report queued and transmitted
+ bytes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This allows BQL to operate avoiding buffer bloat and reducing latency.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20221031104856.32388-1-zajec5@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -505,6 +505,7 @@ static int bcm4908_enet_stop(struct net_
+ netif_carrier_off(netdev);
+ napi_disable(&rx_ring->napi);
+ napi_disable(&tx_ring->napi);
++ netdev_reset_queue(netdev);
+
+ bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);
+ bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);
+@@ -564,6 +565,8 @@ static netdev_tx_t bcm4908_enet_start_xm
+ if (ring->write_idx + 1 == ring->length - 1)
+ tmp |= DMA_CTL_STATUS_WRAP;
+
++ netdev_sent_queue(enet->netdev, skb->len);
++
+ buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
+ buf_desc->ctl = cpu_to_le32(tmp);
+
+@@ -671,6 +674,7 @@ static int bcm4908_enet_poll_tx(struct n
+ tx_ring->read_idx = 0;
+ }
+
++ netdev_completed_queue(enet->netdev, handled, bytes);
+ enet->netdev->stats.tx_packets += handled;
+ enet->netdev->stats.tx_bytes += bytes;
+
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 14 Jul 2023 08:28:41 +0200
+Subject: [PATCH] leds: bcm63138: rename dependency symbol ARCH_BCM4908 to
+ ARCH_BCMBCA
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Symbol ARCH_BCM4908 has been merged/removed without updating leds
+Kconfig.
+
+Fixes: dd5c672d7ca9 ("arm64: bcmbca: Merge ARCH_BCM4908 to ARCH_BCMBCA")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/leds/blink/Kconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/leds/blink/Kconfig
++++ b/drivers/leds/blink/Kconfig
+@@ -1,10 +1,10 @@
+ config LEDS_BCM63138
+ tristate "LED Support for Broadcom BCM63138 SoC"
+ depends on LEDS_CLASS
+- depends on ARCH_BCM4908 || ARCH_BCM_5301X || BCM63XX || COMPILE_TEST
++ depends on ARCH_BCMBCA || ARCH_BCM_5301X || BCM63XX || COMPILE_TEST
+ depends on HAS_IOMEM
+ depends on OF
+- default ARCH_BCM4908
++ default ARCH_BCMBCA
+ help
+ This option enables support for LED controller that is part of
+ BCM63138 SoC. The same hardware block is known to be also used
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 15 Feb 2021 22:01:03 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: limit amount of GPIOs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Linux driver can't handle more than 64 GPIOs
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+@@ -343,7 +343,7 @@
+ gpio0: gpio-controller@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg-names = "dirout", "dat";
+- reg = <0x500 0x28>, <0x528 0x28>;
++ reg = <0x500 0x8>, <0x528 0x8>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 12 Aug 2021 11:52:42 +0200
+Subject: [PATCH] arm64: don't issue HVC on boot
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Broadcom's CFE loader seems to miss setting SCR_EL3.HCE which results in
+generating an UNDEF and kernel panic on the first HVC.
+
+HVC gets issued by kernels 5.12+ while booting, by kexec and KVM. Until
+someone finds a workaround we have to avoid all above.
+
+Workarounds: 0c93df9622d4 ("arm64: Initialise as nVHE before switching to VHE")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ arch/arm64/kernel/hyp-stub.S | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/kernel/hyp-stub.S
++++ b/arch/arm64/kernel/hyp-stub.S
+@@ -301,7 +301,7 @@ SYM_FUNC_START(finalise_el2)
+ b.ne 1f
+
+ mov x0, #HVC_FINALISE_EL2
+- hvc #0
++// hvc #0
+ 1:
+ ret
+ SYM_FUNC_END(finalise_el2)
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 21 Jan 2021 10:44:53 +0100
+Subject: [PATCH] mtd: rawnand: brcmnand: disable WP on BCM4908
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 contains NAND controller version 0x0701 (v7.1). It means that
+NAND_WP should be available.
+
+For some reason setting #WP on doesn't result in clearing NAND_STATUS_WP
+status bit:
+[ 1.077857] bcm63138_nand ff801800.nand: timeout on status poll (expected c0000040 got c00000c0)
+[ 1.086832] bcm63138_nand ff801800.nand: nand #WP expected on
+
+For now try working without touching #WP.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+@@ -39,7 +39,11 @@
+ * 1: NAND_WP is set by default, cleared for erase/write operations
+ * 2: NAND_WP is always cleared
+ */
++#if IS_ENABLED(CONFIG_ARCH_BCMBCA)
++static int wp_on = 0;
++#else
+ static int wp_on = 1;
++#endif
+ module_param(wp_on, int, 0444);
+
+ /***********************************************************************
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 15 Feb 2021 23:59:26 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: enable GPHY for switch probing
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+GPHY needs to be enabled to succesfully probe & setup switch port
+connected to it. Otherwise hardcoding PHY OUI would be required.
+
+Before:
+brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch wan (uninitialized): error -5 setting up PHY for tree 0, switch 0, port 7
+
+After:
+brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch wan (uninitialized): PHY [800c05c0.mdio--1:0c] driver [Generic PHY] (irq=POLL)
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/net/dsa/bcm_sf2.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -1512,10 +1512,14 @@ static int bcm_sf2_sw_probe(struct platf
+ rev = reg_readl(priv, REG_PHY_REVISION);
+ priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
+
++ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
++
+ ret = b53_switch_register(dev);
+ if (ret)
+ goto out_mdio;
+
++ bcm_sf2_gphy_enable_set(priv->dev->ds, false);
++
+ dev_info(&pdev->dev,
+ "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
+ priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 16 Feb 2021 00:06:35 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: keep GPHY enabled on the BCM4908
+
+Trying to access disabled PHY results in MDIO_READ_FAIL and:
+[ 11.962886] brcm-sf2 80080000.switch wan: configuring for phy/internal link mode
+[ 11.972500] 8021q: adding VLAN 0 to HW filter on device wan
+[ 11.980205] ------------[ cut here ]------------
+[ 11.984885] WARNING: CPU: 0 PID: 7 at phy_error+0x10/0x58
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/net/dsa/bcm_sf2.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -1526,6 +1526,12 @@ static int bcm_sf2_sw_probe(struct platf
+ priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
+ priv->irq0, priv->irq1);
+
++ /* BCM4908 has 5 GPHYs which means bcm_sf2_port_setup() will not enable
++ * GPHY when needed. Leave it enabled here.
++ */
++ if (priv->type == BCM4908_DEVICE_ID)
++ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
++
+ return 0;
+
+ out_mdio:
--- /dev/null
+From 588743d4612ddef445bfa19f1c339dad1fcd5fdc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 26 Oct 2021 12:17:02 +0200
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: Add Luxul RT-20
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
+ bcm4906-netgear-r8000p.dtb \
+ bcm4906-tplink-archer-c2300-v1.dtb \
+ bcm4908-asus-gt-ac5300.dtb \
++ bcm4908-luxul-rt-20.dtb \
+ bcm4908-netgear-raxe500.dtb \
+ bcm94908.dtb \
+ bcm4912-asus-gt-ax6000.dtb \
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 21 May 2021 11:14:04 +0200
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: change ports on Asus GT-AC5300
+
+---
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
+@@ -77,16 +77,16 @@
+ };
+
+ port@2 {
+- label = "lan6";
++ label = "lan4";
+ };
+
+ port@3 {
+- label = "lan5";
++ label = "lan3";
+ };
+
+ /* External BCM53134S switch */
+ port@7 {
+- label = "sw";
++ label = "wan";
+ reg = <7>;
+ phy-mode = "rgmii";
+
projects / openwrt / staging / thess.git / commitdiff