}
}
+#ifndef PM8001_USE_MSIX
/**
* pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
* @pm8001_ha: our hba card information
pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
}
+#else
+
/**
* pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
* @pm8001_ha: our hba card information
msi_index += MSIX_TABLE_BASE;
pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
}
+#endif
/**
* pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
{
#ifdef PM8001_USE_MSIX
pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
- return;
-#endif
+#else
pm8001_chip_intx_interrupt_enable(pm8001_ha);
-
+#endif
}
/**
{
#ifdef PM8001_USE_MSIX
pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
- return;
-#endif
+#else
pm8001_chip_intx_interrupt_disable(pm8001_ha);
-
+#endif
}
/**
static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
{
- u32 value;
#ifdef PM8001_USE_MSIX
return 1;
-#endif
+#else
+ u32 value;
+
value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
if (value)
return 1;
return 0;
-
+#endif
}
/**