mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bit
authorKishon Vijay Abraham I <kishon@ti.com>
Thu, 21 Sep 2017 14:51:36 +0000 (16:51 +0200)
committerTom Rini <trini@konsulko.com>
Fri, 19 Jan 2018 20:49:23 +0000 (15:49 -0500)
omap_hsmmc driver uses "|" in a couple of places for disabling a bit.
While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a
_mask_ argument to take care of resetting a bit), it's incorrectly used
for resetting flags in "omap_hsmmc_send_cmd".

Fix it here by using "&= ~()" to reset a bit.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/include/asm/omap_mmc.h
drivers/mmc/omap_hsmmc.c

index 128cd8120df4f864efe9c50b887e574b3c1695cd..bf9de9b21151c50e56c3450aa0cfc2357285d47a 100644 (file)
@@ -90,10 +90,9 @@ struct omap_hsmmc_plat {
 #define DMA_MASTER                     (0x1 << 20)
 #define BLEN_512BYTESLEN               (0x200 << 0)
 #define NBLK_STPCNT                    (0x0 << 16)
-#define DE_DISABLE                     (0x0 << 0)
-#define BCE_DISABLE                    (0x0 << 1)
+#define DE_ENABLE                      (0x1 << 0)
 #define BCE_ENABLE                     (0x1 << 1)
-#define ACEN_DISABLE                   (0x0 << 2)
+#define ACEN_ENABLE                    (0x1 << 2)
 #define DDIR_OFFSET                    (4)
 #define DDIR_MASK                      (0x1 << 4)
 #define DDIR_WRITE                     (0x0 << 4)
@@ -134,7 +133,6 @@ struct omap_hsmmc_plat {
 #define ICS_NOTREADY                   (0x0 << 1)
 #define ICE_OSCILLATE                  (0x1 << 0)
 #define CEN_MASK                       (0x1 << 2)
-#define CEN_DISABLE                    (0x0 << 2)
 #define CEN_ENABLE                     (0x1 << 2)
 #define CLKD_OFFSET                    (6)
 #define CLKD_MASK                      (0x3FF << 6)
index 224c06aea81d93cdbe22d212243b2c57133f5e5e..b12d6d9102ed57e7aac5b9616d2c45143c94757b 100644 (file)
@@ -294,7 +294,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
 
        dsor = 240;
        mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
-               (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+               (ICE_STOP | DTO_15THDTO));
        mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
                (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
        start = get_timer(0);
@@ -544,7 +544,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 
        /* enable default flags */
        flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
-                       MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
+                       MSBS_SGLEBLK);
+       flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
 
        if (cmd->resp_type & MMC_RSP_CRC)
                flags |= CCCE_CHECK;
@@ -811,7 +812,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev)
        }
 
        mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
-                               (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+                               (ICE_STOP | DTO_15THDTO));
 
        mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
                                (dsor << CLKD_OFFSET) | ICE_OSCILLATE);