drm/i915: Implement new w/a for underruns with wm1+ disabled

The new workaround from the hw team involves leaving WM1
still disabled but programming the blocks value
identically to WM0, and we also need to set the "ignore
lines watermark" bit for WM1.

v2: Fix commit message wording a bit

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190213165424.22904-3-ville.syrjala@linux.intel.com
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9485645a41b05fdd3d8e3d6f13a8f8d392898f93..c7ec9b16904621488ecebf6887aa7180f1b8da4c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4463,6 +4463,13 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
                for_each_plane_id_on_crtc(intel_crtc, plane_id) {
                        wm = &cstate->wm.skl.optimal.planes[plane_id];
                        memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+
+                       /* W/A for underruns with WM1+ disabled */
+                       if (IS_ICELAKE(dev_priv) &&
+                           level == 1 && wm->wm[0].plane_en) {
+                               wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
+                               wm->wm[level].ignore_lines = true;
+                       }
                }
        }