*/
static const unsigned long bcm96338_regs_base[] = {
+ [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE,
[RSET_PERF] = BCM_6338_PERF_BASE,
[RSET_TIMER] = BCM_6338_TIMER_BASE,
[RSET_WDT] = BCM_6338_WDT_BASE,
* 6338 register sets base address
*/
+#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
#define BCM_6338_PERF_BASE (0xfffe0000)
#define BCM_6338_BB_BASE (0xfffe0100) /* bus bridge registers */
#define BCM_6338_TIMER_BASE (0xfffe0200)
#else
#ifdef CONFIG_BCM63XX_CPU_6338
switch (set) {
+ case RSET_DSL_LMEM:
+ return BCM_6338_DSL_LMEM_BASE;
case RSET_PERF:
return BCM_6338_PERF_BASE;
case RSET_TIMER:
switch (bcm63xx_get_cpu_id()) {
case BCM6358_CPU_ID:
return 40;
+ case BCM6338_CPU_ID:
+ return 7;
+ case BCM6345_CPU_ID:
+ return 16;
case BCM6348_CPU_ID:
default:
return 37;
#define cpu_has_smartmips 0
#define cpu_has_vtag_icache 0
-#if !defined(BCMCPU_RUNTIME_DETECT) && defined(CONFIG_BCMCPU_IS_6348)
+#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCMCPU_IS_6348) || defined(CONFIG_CPU_IS_6338) || defined(CONFIG_CPU_IS_BCM6345))
#define cpu_has_dc_aliases 0
#endif