--- /dev/null
+Sync the hifive-unleashed-a00 dts from Linux with
+below commit details:
+
+commit <2993c9b04e616df0848b655d7202a707a70fc876> ("riscv: dts: HiFive
+Unleashed: add default chosen/stdout-path")
+
+Idea is to periodically sync the dts from Linux instead of
+tweaking internal changes one after another, so better not
+add any intermediate changes in between. This would help to
+maintain the dts files easy and meaningful since we are
+reusing device tree files from Linux.
+
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+---
+ arch/riscv/dts/Makefile | 1 +
+ arch/riscv/dts/fu540-c000.dtsi | 251 ++++++++++++++++++++++++
+ arch/riscv/dts/hifive-unleashed-a00.dts | 96 +++++++++
+ 3 files changed, 348 insertions(+)
+ create mode 100644 arch/riscv/dts/fu540-c000.dtsi
+ create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts
+
+diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
+index f9cd606a9a..4f30e6936f 100644
+--- a/arch/riscv/dts/Makefile
++++ b/arch/riscv/dts/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0+
+
+ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
++dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
+
+ targets += $(dtb-y)
+
+diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi
+new file mode 100644
+index 0000000000..afa43c7ea3
+--- /dev/null
++++ b/arch/riscv/dts/fu540-c000.dtsi
+@@ -0,0 +1,251 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/* Copyright (c) 2018-2019 SiFive, Inc */
++
++/dts-v1/;
++
++#include <dt-bindings/clock/sifive-fu540-prci.h>
++
++/ {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ compatible = "sifive,fu540-c000", "sifive,fu540";
++
++ aliases {
++ serial0 = &uart0;
++ serial1 = &uart1;
++ ethernet0 = ð0;
++ };
++
++ chosen {
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ cpu0: cpu@0 {
++ compatible = "sifive,e51", "sifive,rocket0", "riscv";
++ device_type = "cpu";
++ i-cache-block-size = <64>;
++ i-cache-sets = <128>;
++ i-cache-size = <16384>;
++ reg = <0>;
++ riscv,isa = "rv64imac";
++ status = "disabled";
++ cpu0_intc: interrupt-controller {
++ #interrupt-cells = <1>;
++ compatible = "riscv,cpu-intc";
++ interrupt-controller;
++ };
++ };
++ cpu1: cpu@1 {
++ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
++ d-cache-block-size = <64>;
++ d-cache-sets = <64>;
++ d-cache-size = <32768>;
++ d-tlb-sets = <1>;
++ d-tlb-size = <32>;
++ device_type = "cpu";
++ i-cache-block-size = <64>;
++ i-cache-sets = <64>;
++ i-cache-size = <32768>;
++ i-tlb-sets = <1>;
++ i-tlb-size = <32>;
++ mmu-type = "riscv,sv39";
++ reg = <1>;
++ riscv,isa = "rv64imafdc";
++ tlb-split;
++ cpu1_intc: interrupt-controller {
++ #interrupt-cells = <1>;
++ compatible = "riscv,cpu-intc";
++ interrupt-controller;
++ };
++ };
++ cpu2: cpu@2 {
++ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
++ d-cache-block-size = <64>;
++ d-cache-sets = <64>;
++ d-cache-size = <32768>;
++ d-tlb-sets = <1>;
++ d-tlb-size = <32>;
++ device_type = "cpu";
++ i-cache-block-size = <64>;
++ i-cache-sets = <64>;
++ i-cache-size = <32768>;
++ i-tlb-sets = <1>;
++ i-tlb-size = <32>;
++ mmu-type = "riscv,sv39";
++ reg = <2>;
++ riscv,isa = "rv64imafdc";
++ tlb-split;
++ cpu2_intc: interrupt-controller {
++ #interrupt-cells = <1>;
++ compatible = "riscv,cpu-intc";
++ interrupt-controller;
++ };
++ };
++ cpu3: cpu@3 {
++ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
++ d-cache-block-size = <64>;
++ d-cache-sets = <64>;
++ d-cache-size = <32768>;
++ d-tlb-sets = <1>;
++ d-tlb-size = <32>;
++ device_type = "cpu";
++ i-cache-block-size = <64>;
++ i-cache-sets = <64>;
++ i-cache-size = <32768>;
++ i-tlb-sets = <1>;
++ i-tlb-size = <32>;
++ mmu-type = "riscv,sv39";
++ reg = <3>;
++ riscv,isa = "rv64imafdc";
++ tlb-split;
++ cpu3_intc: interrupt-controller {
++ #interrupt-cells = <1>;
++ compatible = "riscv,cpu-intc";
++ interrupt-controller;
++ };
++ };
++ cpu4: cpu@4 {
++ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
++ d-cache-block-size = <64>;
++ d-cache-sets = <64>;
++ d-cache-size = <32768>;
++ d-tlb-sets = <1>;
++ d-tlb-size = <32>;
++ device_type = "cpu";
++ i-cache-block-size = <64>;
++ i-cache-sets = <64>;
++ i-cache-size = <32768>;
++ i-tlb-sets = <1>;
++ i-tlb-size = <32>;
++ mmu-type = "riscv,sv39";
++ reg = <4>;
++ riscv,isa = "rv64imafdc";
++ tlb-split;
++ cpu4_intc: interrupt-controller {
++ #interrupt-cells = <1>;
++ compatible = "riscv,cpu-intc";
++ interrupt-controller;
++ };
++ };
++ };
++ soc {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
++ ranges;
++ plic0: interrupt-controller@c000000 {
++ #interrupt-cells = <1>;
++ compatible = "sifive,plic-1.0.0";
++ reg = <0x0 0xc000000 0x0 0x4000000>;
++ riscv,ndev = <53>;
++ interrupt-controller;
++ interrupts-extended = <
++ &cpu0_intc 0xffffffff
++ &cpu1_intc 0xffffffff &cpu1_intc 9
++ &cpu2_intc 0xffffffff &cpu2_intc 9
++ &cpu3_intc 0xffffffff &cpu3_intc 9
++ &cpu4_intc 0xffffffff &cpu4_intc 9>;
++ };
++ prci: clock-controller@10000000 {
++ compatible = "sifive,fu540-c000-prci";
++ reg = <0x0 0x10000000 0x0 0x1000>;
++ clocks = <&hfclk>, <&rtcclk>;
++ #clock-cells = <1>;
++ };
++ uart0: serial@10010000 {
++ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
++ reg = <0x0 0x10010000 0x0 0x1000>;
++ interrupt-parent = <&plic0>;
++ interrupts = <4>;
++ clocks = <&prci PRCI_CLK_TLCLK>;
++ status = "disabled";
++ };
++ uart1: serial@10011000 {
++ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
++ reg = <0x0 0x10011000 0x0 0x1000>;
++ interrupt-parent = <&plic0>;
++ interrupts = <5>;
++ clocks = <&prci PRCI_CLK_TLCLK>;
++ status = "disabled";
++ };
++ i2c0: i2c@10030000 {
++ compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
++ reg = <0x0 0x10030000 0x0 0x1000>;
++ interrupt-parent = <&plic0>;
++ interrupts = <50>;
++ clocks = <&prci PRCI_CLK_TLCLK>;
++ reg-shift = <2>;
++ reg-io-width = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ qspi0: spi@10040000 {
++ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
++ reg = <0x0 0x10040000 0x0 0x1000
++ 0x0 0x20000000 0x0 0x10000000>;
++ interrupt-parent = <&plic0>;
++ interrupts = <51>;
++ clocks = <&prci PRCI_CLK_TLCLK>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ qspi1: spi@10041000 {
++ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
++ reg = <0x0 0x10041000 0x0 0x1000
++ 0x0 0x30000000 0x0 0x10000000>;
++ interrupt-parent = <&plic0>;
++ interrupts = <52>;
++ clocks = <&prci PRCI_CLK_TLCLK>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ qspi2: spi@10050000 {
++ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
++ reg = <0x0 0x10050000 0x0 0x1000>;
++ interrupt-parent = <&plic0>;
++ interrupts = <6>;
++ clocks = <&prci PRCI_CLK_TLCLK>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ eth0: ethernet@10090000 {
++ compatible = "sifive,fu540-c000-gem";
++ interrupt-parent = <&plic0>;
++ interrupts = <53>;
++ reg = <0x0 0x10090000 0x0 0x2000
++ 0x0 0x100a0000 0x0 0x1000>;
++ local-mac-address = [00 00 00 00 00 00];
++ clock-names = "pclk", "hclk";
++ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
++ <&prci PRCI_CLK_GEMGXLPLL>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ pwm0: pwm@10020000 {
++ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
++ reg = <0x0 0x10020000 0x0 0x1000>;
++ interrupt-parent = <&plic0>;
++ interrupts = <42 43 44 45>;
++ clocks = <&prci PRCI_CLK_TLCLK>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++ pwm1: pwm@10021000 {
++ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
++ reg = <0x0 0x10021000 0x0 0x1000>;
++ interrupt-parent = <&plic0>;
++ interrupts = <46 47 48 49>;
++ clocks = <&prci PRCI_CLK_TLCLK>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ };
++};
+diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts
+new file mode 100644
+index 0000000000..88cfcb96bf
+--- /dev/null
++++ b/arch/riscv/dts/hifive-unleashed-a00.dts
+@@ -0,0 +1,96 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/* Copyright (c) 2018-2019 SiFive, Inc */
++
++#include "fu540-c000.dtsi"
++
++/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
++#define RTCCLK_FREQ 1000000
++
++/ {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ model = "SiFive HiFive Unleashed A00";
++ compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
++
++ chosen {
++ stdout-path = "serial0";
++ };
++
++ cpus {
++ timebase-frequency = <RTCCLK_FREQ>;
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0x0 0x80000000 0x2 0x00000000>;
++ };
++
++ soc {
++ };
++
++ hfclk: hfclk {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <33333333>;
++ clock-output-names = "hfclk";
++ };
++
++ rtcclk: rtcclk {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <RTCCLK_FREQ>;
++ clock-output-names = "rtcclk";
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&uart1 {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++};
++
++&qspi0 {
++ status = "okay";
++ flash@0 {
++ compatible = "issi,is25wp256", "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <50000000>;
++ m25p,fast-read;
++ spi-tx-bus-width = <4>;
++ spi-rx-bus-width = <4>;
++ };
++};
++
++&qspi2 {
++ status = "okay";
++ mmc@0 {
++ compatible = "mmc-spi-slot";
++ reg = <0>;
++ spi-max-frequency = <20000000>;
++ voltage-ranges = <3300 3300>;
++ disable-wp;
++ };
++};
++
++ð0 {
++ status = "okay";
++ phy-mode = "gmii";
++ phy-handle = <&phy0>;
++ phy0: ethernet-phy@0 {
++ reg = <0>;
++ };
++};
++
++&pwm0 {
++ status = "okay";
++};
++
++&pwm1 {
++ status = "okay";
++};
+
+From patchwork Wed Oct 16 14:58:11 2019
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+ Wed, 16 Oct 2019 07:58:32 -0700 (PDT)
+From: Jagan Teki <jagan@amarulasolutions.com>
+To: Rick Chen <rick@andestech.com>, Paul Walmsley <paul.walmsley@sifive.com>,
+ Palmer Dabbelt <palmer@sifive.com>, Anup Patel <anup.patel@wdc.com>,
+ Atish Patra <atish.patra@wdc.com>, Bin Meng <bmeng.cn@gmail.com>
+Date: Wed, 16 Oct 2019 20:28:11 +0530
+Message-Id: <20191016145814.19036-3-jagan@amarulasolutions.com>
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+MIME-Version: 1.0
+Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com
+Subject: [U-Boot] [PATCH v2 2/5] sifive: fu540: Enable OF_SEPARATE
+X-BeenThere: u-boot@lists.denx.de
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+Precedence: list
+List-Id: U-Boot discussion <u-boot.lists.denx.de>
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+
+Use dts support from U-Boot via OF_SEPARATE instead of depending from
+opensbi.
+
+This would help to make the necessary changes in drivers and devicetrees
+in uboot tree itself. this feature would also be helpful to not pass
+dtb during opensbi builds.
+
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+---
+ configs/sifive_fu540_defconfig | 3 ++-
+ doc/board/sifive/fu540.rst | 2 +-
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
+index 48865e5f11..979d0a0418 100644
+--- a/configs/sifive_fu540_defconfig
++++ b/configs/sifive_fu540_defconfig
+@@ -6,6 +6,7 @@ CONFIG_RISCV_SMODE=y
+ CONFIG_DISTRO_DEFAULTS=y
+ CONFIG_FIT=y
+ CONFIG_MISC_INIT_R=y
++CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
+ CONFIG_DISPLAY_CPUINFO=y
+ CONFIG_DISPLAY_BOARDINFO=y
+-CONFIG_OF_PRIOR_STAGE=y
++CONFIG_OF_SEPARATE=y
+diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
+index 7807f5b2c1..91b94ee06f 100644
+--- a/doc/board/sifive/fu540.rst
++++ b/doc/board/sifive/fu540.rst
+@@ -58,7 +58,7 @@ firmware. We need to compile OpenSBI with below command:
+
+ .. code-block:: none
+
+- make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<path to u-boot.bin> FW_PAYLOAD_FDT_PATH=<path to hifive-unleashed-a00.dtb from Linux>
++ make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<path to u-boot-dtb.bin>
+
+ (Note: Prefer hifive-unleashed-a00.dtb from Linux-5.3 or higher)
+ (Note: Linux-5.2 is also fine but it does not have ethernet DT node)
+
+From patchwork Wed Oct 16 14:58:12 2019
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+ Wed, 16 Oct 2019 07:58:35 -0700 (PDT)
+From: Jagan Teki <jagan@amarulasolutions.com>
+To: Rick Chen <rick@andestech.com>, Paul Walmsley <paul.walmsley@sifive.com>,
+ Palmer Dabbelt <palmer@sifive.com>, Anup Patel <anup.patel@wdc.com>,
+ Atish Patra <atish.patra@wdc.com>, Bin Meng <bmeng.cn@gmail.com>
+Date: Wed, 16 Oct 2019 20:28:12 +0530
+Message-Id: <20191016145814.19036-4-jagan@amarulasolutions.com>
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+MIME-Version: 1.0
+Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com
+Subject: [U-Boot] [PATCH v2 3/5] mtd: spi-nor: ids: Add is25wp256 chip
+X-BeenThere: u-boot@lists.denx.de
+X-Mailman-Version: 2.1.18
+Precedence: list
+List-Id: U-Boot discussion <u-boot.lists.denx.de>
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+
+Add is25wp256, chip to spi-nor id table.
+
+Tested on SiFive FU540 board.
+
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Tested-by: Bin Meng <bmeng.cn@gmail.com>
+---
+ drivers/mtd/spi/spi-nor-ids.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
+index 6996c0a286..04db986561 100644
+--- a/drivers/mtd/spi/spi-nor-ids.c
++++ b/drivers/mtd/spi/spi-nor-ids.c
+@@ -128,6 +128,8 @@ const struct flash_info spi_nor_ids[] = {
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++ { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
++ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ #endif
+ #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
+ /* Macronix */
+
+From patchwork Wed Oct 16 14:58:13 2019
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+ Wed, 16 Oct 2019 07:58:39 -0700 (PDT)
+From: Jagan Teki <jagan@amarulasolutions.com>
+To: Rick Chen <rick@andestech.com>, Paul Walmsley <paul.walmsley@sifive.com>,
+ Palmer Dabbelt <palmer@sifive.com>, Anup Patel <anup.patel@wdc.com>,
+ Atish Patra <atish.patra@wdc.com>, Bin Meng <bmeng.cn@gmail.com>
+Date: Wed, 16 Oct 2019 20:28:13 +0530
+Message-Id: <20191016145814.19036-5-jagan@amarulasolutions.com>
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+MIME-Version: 1.0
+Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com
+Subject: [U-Boot] [PATCH v2 4/5] riscv: dts: hifive-unleashed-a00: Add
+ -u-boot.dtsi
+X-BeenThere: u-boot@lists.denx.de
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+Precedence: list
+List-Id: U-Boot discussion <u-boot.lists.denx.de>
+List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
+ <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
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+
+Add u-boot specific dts file for hifive-unleashed-a00, this
+would help to add u-boot specific properties and other node
+changes without touching the base dts(i) files which are easy
+to sync from Linux.
+
+Added spi2 alias for qspi2 as an initial u-boot specific
+property change.
+
+spi probing in current dm model is very much rely on aliases
+numbering. even though the qspi2 can't comes under any associated
+spi nor flash it would require to specify the same to make proper
+binding happen for other spi slaves.
+
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+---
+ arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+ create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+
+diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+new file mode 100644
+index 0000000000..25ec8265a5
+--- /dev/null
++++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+@@ -0,0 +1,10 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
++ */
++
++/ {
++ aliases {
++ spi2 = &qspi2;
++ };
++};
+
+From patchwork Wed Oct 16 14:58:14 2019
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+ Wed, 16 Oct 2019 07:58:42 -0700 (PDT)
+From: Jagan Teki <jagan@amarulasolutions.com>
+To: Rick Chen <rick@andestech.com>, Paul Walmsley <paul.walmsley@sifive.com>,
+ Palmer Dabbelt <palmer@sifive.com>, Anup Patel <anup.patel@wdc.com>,
+ Atish Patra <atish.patra@wdc.com>, Bin Meng <bmeng.cn@gmail.com>
+Date: Wed, 16 Oct 2019 20:28:14 +0530
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+Subject: [U-Boot] [PATCH v2 5/5] sifive: fu540: Enable spi-nor flash support
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+
+HiFive Unleashed A00 support is25wp256 spi-nor flash,
+So enable the same and add test result log for future
+reference.
+
+Tested on SiFive FU540 board.
+
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Tested-by: Bin Meng <bmeng.cn@gmail.com>
+---
+ .../dts/hifive-unleashed-a00-u-boot.dtsi | 1 +
+ board/sifive/fu540/Kconfig | 3 +++
+ doc/board/sifive/fu540.rst | 19 +++++++++++++++++++
+ 3 files changed, 23 insertions(+)
+
+diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+index 25ec8265a5..d7a64134db 100644
+--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
++++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+@@ -5,6 +5,7 @@
+
+ / {
+ aliases {
++ spi0 = &qspi0;
+ spi2 = &qspi2;
+ };
+ };
+diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
+index 5d65080429..c5a1bca03c 100644
+--- a/board/sifive/fu540/Kconfig
++++ b/board/sifive/fu540/Kconfig
+@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
++ imply CMD_SF
+ imply CLK_SIFIVE
+ imply CLK_SIFIVE_FU540_PRCI
+ imply DOS_PARTITION
+@@ -40,6 +41,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
+ imply SIFIVE_SERIAL
+ imply SPI
+ imply SPI_SIFIVE
++ imply SPI_FLASH
++ imply SPI_FLASH_ISSI
+ imply MMC
+ imply MMC_SPI
+ imply MMC_BROKEN_CD
+diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
+index 91b94ee06f..2e70cad02e 100644
+--- a/doc/board/sifive/fu540.rst
++++ b/doc/board/sifive/fu540.rst
+@@ -366,3 +366,22 @@ load uImage.
+
+ Please press Enter to activate this console.
+ / #
++
++Sample spi nor flash test
++-------------------------
++
++.. code-block:: none
++
++ => sf probe 0:2
++ SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
++ => sf erase 0x1000000 0x100000
++ SF: 1048576 bytes @ 0x1000000 Erased: OK
++ => mw.b 0xc0000000 0xaa 0x100000
++ => sf write 0xc0000000 0x1000000 0x100000
++ device 0 offset 0x1000000, size 0x100000
++ SF: 1048576 bytes @ 0x1000000 Written: OK
++ => sf read 0xf0000000 0x1000000 0x100000
++ device 0 offset 0x1000000, size 0x100000
++ SF: 1048576 bytes @ 0x1000000 Read: OK
++ => cmp.b 0xf0000000 0xc0000000 0x100000
++ Total of 1048576 byte(s) were the same
projects / openwrt / staging / wigyori.git / commitdiff