zynqmp: pm: Fix model of ACPU clocks

In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not correct. ACPU clock model contains only
mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF
clocks which have only gates. The models of ACPU and ACPU_HALF clocks
are fixed and ACPU_FULL clock is added.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index 8c157928091590850318e67c2e4875dca5d29634..d91f4e467eb07fc94f693471b7872e6bb1174a2f 100644 (file)
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -330,18 +330,6 @@ static struct pm_clock_node acpu_nodes[] = {
                .mult = NA_MULT,
                .div = NA_DIV,
        },
-       {
-               .type = TYPE_GATE,
-               .offset = PERIPH_GATE_SHIFT,
-               .width = PERIPH_GATE_WIDTH,
-               .clkflags = CLK_SET_RATE_PARENT |
-                           CLK_IGNORE_UNUSED |
-                           CLK_IS_BASIC |
-                           CLK_IS_CRITICAL,
-               .typeflags = NA_TYPE_FLAGS,
-               .mult = NA_MULT,
-               .div = NA_DIV,
-       },
 };
 
 static struct pm_clock_node generic_mux_div_nodes[] = {
@@ -476,6 +464,20 @@ static struct pm_clock_node acpu_half_nodes[] = {
        },
 };
 
+static struct pm_clock_node acpu_full_nodes[] = {
+       {
+               .type = TYPE_GATE,
+               .offset = 24,
+               .width = PERIPH_GATE_WIDTH,
+               .clkflags = CLK_IGNORE_UNUSED |
+                           CLK_SET_RATE_PARENT |
+                           CLK_IS_BASIC,
+               .typeflags = NA_TYPE_FLAGS,
+               .mult = NA_MULT,
+               .div = NA_DIV,
+       },
+};
+
 static struct pm_clock_node wdt_nodes[] = {
        {
                .type = TYPE_MUX,
@@ -1205,6 +1207,17 @@ static struct pm_clock clocks[] = {
                .nodes = &acpu_nodes,
                .num_nodes = ARRAY_SIZE(acpu_nodes),
        },
+       [CLK_ACPU_FULL] = {
+               .name = "acpu_full",
+               .control_reg = CRF_APB_ACPU_CTRL,
+               .status_reg = 0,
+               .parents = &((int32_t []) {
+                       CLK_ACPU | PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN,
+                       CLK_NA_PARENT
+               }),
+               .nodes = &acpu_full_nodes,
+               .num_nodes = ARRAY_SIZE(acpu_full_nodes),
+       },
        [CLK_DBG_TRACE] = {
                .name = "dbg_trace",
                .control_reg = CRF_APB_DBG_TRACE_CTRL,

diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
index 671c29fedf97604b7d6ef57f078597ffd061fe56..8d5e96788d8b5f276bfcfa560f79dc759d604bf2 100644 (file)
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
@@ -159,6 +159,7 @@ enum clock_id {
        CLK_VPLL_POST_SRC,
        CLK_CAN0_MIO,
        CLK_CAN1_MIO,
+       CLK_ACPU_FULL,
        END_OF_OUTPUT_CLKS,
 };