ARM: UniPhier: fix SBC init code

Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
index f44195d2ca971ddc0992f7eb3b0579350ea8f59d..374a8c06800bc5632b940b9324961d02c7f37138 100644 (file)
--- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
+++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
@@ -25,13 +25,12 @@ void sbc_init(void)
        writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
        writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
 
-#if !defined(CONFIG_SPL_BUILD)
        /* XECS0: boot/sub memory (boot swap = off/on) */
        writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
        writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
        writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
        writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
+
        /* XECS3: peripherals */
        writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
        writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
@@ -43,9 +42,9 @@ void sbc_init(void)
        writel(0x0400bc01, SBBASE1);
        writel(0x0800bf01, SBBASE3);
 
-#if !defined(CONFIG_SPL_BUILD)
        /* enable access to sub memory when boot swap is on */
-       sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
-#endif
+       if (boot_is_swapped())
+               sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
+
        sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
 }

diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
index 69405594b87ddfeef573027264d91ecec6b3e9cd..4cc5e75724a914202ee5e3033f549599aaf3b2f4 100644 (file)
--- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
+++ b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
@@ -42,13 +42,12 @@ void sbc_init(void)
                writel(0x0200be01, SBBASE1);
        }
 #elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-#if !defined(CONFIG_SPL_BUILD)
        /* XECS0: boot/sub memory (boot swap = off/on) */
        writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
        writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
        writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
        writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
+
        /* XECS1: sub/boot memory (boot swap = off/on) */
        writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
        writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
@@ -65,9 +64,10 @@ void sbc_init(void)
        writel(0x0400bc01, SBBASE1); /* sub memory */
        writel(0x0800bf01, SBBASE3); /* peripherals */
 
-#if !defined(CONFIG_SPL_BUILD)
-       sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
-#endif
+       /* enable access to sub memory when boot swap is on */
+       if (boot_is_swapped())
+               sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
+
        sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
        writel(0x00000001, SG_LOADPINCTRL);
 

diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c
index febd0e434136614d0b59b4c62f6adfd478431c93..fdef88e1268a7e132469b6c20249a9cb8dba69ed 100644 (file)
--- a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c
+++ b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2011-2015 Panasonic Corporation
  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
@@ -19,18 +19,18 @@ void sbc_init(void)
        tmp &= 0xfffffcff;
        writel(tmp, PC0CTRL);
 
-#if !defined(CONFIG_SPL_BUILD)
-       /* XECS0 : dummy */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
-       /* XECS1 : boot memory (always boot swap = on) */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+       /*
+        * SBCTRL0* does not need settings because PH1-sLD8 has no support for
+        * XECS0.  The boot swap must be enabled to boot from the support card.
+        */
+
+       if (boot_is_swapped()) {
+               /* XECS1 : boot memory if boot swap is on */
+               writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+               writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+               writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+               writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+       }
 
        /* XECS4 : sub memory */
        writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
@@ -54,5 +54,5 @@ void sbc_init(void)
        sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
 
        /* dummy read to assure write process */
-       readl(SG_PINCTRL(33));
+       readl(SG_PINCTRL(0));
 }