m68knommu: general interrupt controller for ColdFire 532x parts

The ColdFire 532x family of parts uses 2 of the same INTC interrupt
controlers used in the ColdFire 520x family. So modify the code to
support both parts. The extra code for the second INTC controler in
the case of the 520x is easily optimized away to nothing.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index e79b9bc76a123805f5b3b5a8402bebdc9f4b39ca..91de39c8d865a5491537806f2bdbb95c0f67f937 100644 (file)
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -11,9 +11,8 @@
 #define m520xsim_h
 /****************************************************************************/
 
-
 /*
- *  Define the 5282 SIM register set addresses.
+ *  Define the 520x SIM register set addresses.
  */
 #define MCFICM_INTC0        0x48000     /* Base for Interrupt Ctrl 0 */
 #define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
@@ -26,6 +25,18 @@
 #define MCFINTC_CIMR        0x1d        /* Clear interrupt mask 0-63 */
 #define MCFINTC_ICR0        0x40        /* Base ICR register */
 
+/*
+ *  The common interrupt controller code just wants to know the absolute
+ *  address to the SIMR and CIMR registers (not offsets into IPSBAR).
+ *  The 520x family only has a single INTC unit.
+ */
+#define MCFINTC0_SIMR       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR)
+#define MCFINTC0_CIMR       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR)
+#define        MCFINTC0_ICR0       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0)
+#define MCFINTC1_SIMR       (0)
+#define MCFINTC1_CIMR       (0)
+#define        MCFINTC1_ICR0       (0)
+
 #define MCFINT_VECBASE      64
 #define MCFINT_UART0        26          /* Interrupt number for UART0 */
 #define MCFINT_UART1        27          /* Interrupt number for UART1 */

diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 3e80810b378474547a73793fddc52b26c0f71a4a..41c57e0f445ab8cf3d56f6524817e411eb2ddbcf 100644 (file)
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -58,10 +58,12 @@
 
 #define        MCFSIM_IMR_MASKALL      0xFFFFFFFF      /* All SIM intr sources */
 
-#define MCFSIM_IMR_SIMR0       0xFC04801C
-#define MCFSIM_IMR_SIMR1       0xFC04C01C
-#define MCFSIM_IMR_CIMR0       0xFC04801D
-#define MCFSIM_IMR_CIMR1       0xFC04C01D
+#define        MCFINTC0_SIMR           0xFC04801C
+#define        MCFINTC0_CIMR           0xFC04801D
+#define        MCFINTC0_ICR0           0xFC048040
+#define        MCFINTC1_SIMR           0xFC04C01C
+#define        MCFINTC1_CIMR           0xFC04C01D
+#define        MCFINTC1_ICR0           0xFC04C040
 
 #define MCFSIM_ICR_TIMER1      (0xFC048040+32)
 #define MCFSIM_ICR_TIMER2      (0xFC048040+33)
@@ -87,16 +89,16 @@
 
 
 #define mcf_enable_irq0(irq)           \
-       *((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq);
+       *((volatile unsigned char *) (MCFINTC0_CIMR)) = (irq);
 
 #define mcf_enable_irq1(irq)           \
-       *((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq);
+       *((volatile unsigned char *) (MCFINTC1_CIMR)) = (irq);
 
 #define mcf_disable_irq0(irq)          \
-       *((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq);
+       *((volatile unsigned char *) (MCFINTC0_SIMR)) = (irq);
 
 #define mcf_disable_irq1(irq)          \
-       *((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq);
+       *((volatile unsigned char *) (MCFINTC1_SIMR)) = (irq);
 
 /*
  *     Define the Cache register flags.

diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c
index f9965d7ee7c57e0e9a8eefcc0d2f35d35c295532..93d567bbf33dbfb50e29640234e05ef21e0af984 100644 (file)
--- a/arch/m68knommu/kernel/irq.c
+++ b/arch/m68knommu/kernel/irq.c
@@ -30,7 +30,8 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
 }
 
 #if !defined(CONFIG_M520x) && !defined(CONFIG_M523x) && \
-    !defined(CONFIG_M527x) && !defined(CONFIG_M528x)
+    !defined(CONFIG_M527x) && !defined(CONFIG_M528x) && \
+    !defined(CONFIG_M532x)
 
 static struct irq_chip m_irq_chip = {
        .name           = "M68K-INTC",

diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile
index bce9a62d3a137fb79d65ca66273ca4ed31473402..6c5f699cf14545e5c2d30946dbeaf628a2b3e1a8 100644 (file)
--- a/arch/m68knommu/platform/coldfire/Makefile
+++ b/arch/m68knommu/platform/coldfire/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_M527x)   += pit.o intc-2.o
 obj-$(CONFIG_M5272)    += timers.o
 obj-$(CONFIG_M528x)    += pit.o intc-2.o
 obj-$(CONFIG_M5307)    += timers.o
-obj-$(CONFIG_M532x)    += timers.o
+obj-$(CONFIG_M532x)    += timers.o intc-simr.o
 obj-$(CONFIG_M5407)    += timers.o
 
 obj-y                  += pinmux.o gpio.o

diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
index 3b614a3508fcc6f639475901bfbbba8c7d2a5e98..86fc2047d7acd99409d6ae337ef0a127bbf90850 100644 (file)
--- a/arch/m68knommu/platform/coldfire/intc-simr.c
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -20,20 +20,32 @@
 
 static void intc_irq_mask(unsigned int irq)
 {
-       if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63))
-               __raw_writeb(irq - MCFINT_VECBASE, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR);
+       if (irq >= MCFINT_VECBASE) {
+               if (irq < MCFINT_VECBASE + 64)
+                       __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR);
+               else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR)
+                       __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR);
+       }
 }
 
 static void intc_irq_unmask(unsigned int irq)
 {
-       if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63))
-               __raw_writeb(irq - MCFINT_VECBASE, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR);
+       if (irq >= MCFINT_VECBASE) {
+               if (irq < MCFINT_VECBASE + 64)
+                       __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR);
+               else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR)
+                       __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR);
+       }
 }
 
 static int intc_irq_set_type(unsigned int irq, unsigned int type)
 {
-       if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63))
-               __raw_writeb(5, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + irq - MCFINT_VECBASE);
+       if (irq >= MCFINT_VECBASE) {
+               if (irq < MCFINT_VECBASE + 64)
+                       __raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE);
+               else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0)
+                       __raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64);
+       }
        return 0;
 }