mediatek: add new dts files for mt7622 to v4.14

Signed-off-by: John Crispin <john@phrozen.org>

diff --git a/target/linux/mediatek/files-4.14/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/target/linux/mediatek/files-4.14/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
new file mode 100644 (file)
index 0000000..62a876c
--- /dev/null
+++ b/target/linux/mediatek/files-4.14/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -0,0 +1,574 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "mt7622.dtsi"
+#include "mt6380.dtsi"
+
+/ {
+       model = "Bananapi BPI-R64";
+       compatible = "bananapi,bpi-r64", "mediatek,mt7622";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+               bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
+       };
+
+       cpus {
+               cpu@0 {
+                       proc-supply = <&mt6380_vcpu_reg>;
+                       sram-supply = <&mt6380_vm_reg>;
+               };
+
+               cpu@1 {
+                       proc-supply = <&mt6380_vcpu_reg>;
+                       sram-supply = <&mt6380_vm_reg>;
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+
+               factory {
+                       label = "factory";
+                       linux,code = <BTN_0>;
+                       gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+               };
+
+               wps {
+                       label = "wps";
+                       linux,code = <KEY_WPS_BUTTON>;
+                       gpios = <&pio 102 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               green {
+                       label = "bpi-r64:pio:green";
+                       gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+
+               red {
+                       label = "bpi-r64:pio:red";
+                       gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+       };
+
+       gsw: gsw@0 {
+               compatible = "mediatek,mt753x";
+               mediatek,ethsys = <&ethsys>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       memory {
+               reg = <0 0x40000000 0 0x40000000>;
+       };
+
+       reg_1p8v: regulator-1p8v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-1.8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+       };
+
+       reg_3p3v: regulator-3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       reg_5v: regulator-5v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-5V";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+};
+
+&bch {
+       status = "disabled";
+};
+
+&btif {
+       status = "okay";
+};
+
+&cir {
+       pinctrl-names = "default";
+       pinctrl-0 = <&irrx_pins>;
+       status = "okay";
+};
+
+&eth {
+       pinctrl-names = "default";
+       pinctrl-0 = <&eth_pins>;
+       status = "okay";
+
+       gmac1: mac@1 {
+               compatible = "mediatek,eth-mac";
+               reg = <1>;
+               phy-handle = <&phy5>;
+       };
+
+       mdio: mdio-bus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               phy5: ethernet-phy@5 {
+                       reg = <5>;
+                       phy-mode = "sgmii";
+               };
+       };
+};
+
+&i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c1_pins>;
+       status = "okay";
+};
+
+&i2c2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c2_pins>;
+       status = "okay";
+};
+
+&mmc0 {
+       pinctrl-names = "default", "state_uhs";
+       pinctrl-0 = <&emmc_pins_default>;
+       pinctrl-1 = <&emmc_pins_uhs>;
+       status = "okay";
+       bus-width = <8>;
+       max-frequency = <50000000>;
+       cap-mmc-highspeed;
+       mmc-hs200-1_8v;
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_1p8v>;
+       assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+       assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+       non-removable;
+};
+
+&mmc1 {
+       pinctrl-names = "default", "state_uhs";
+       pinctrl-0 = <&sd0_pins_default>;
+       pinctrl-1 = <&sd0_pins_uhs>;
+       status = "okay";
+       bus-width = <4>;
+       max-frequency = <50000000>;
+       cap-sd-highspeed;
+       r_smpl = <1>;
+       cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_3p3v>;
+       assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+       assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+};
+
+&nandc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&parallel_nand_pins>;
+       status = "disabled";
+};
+
+&nor_flash {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi_nor_pins>;
+       status = "disabled";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+       };
+};
+
+&pcie {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+       status = "okay";
+
+       pcie@0,0 {
+               status = "okay";
+       };
+
+       pcie@1,0 {
+               status = "okay";
+       };
+};
+
+&pio {
+       /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
+        * SATA functions. i.e. output-high: PCIe, output-low: SATA
+        */
+       asm_sel {
+               gpio-hog;
+               gpios = <90 GPIO_ACTIVE_HIGH>;
+               output-high;
+       };
+
+       /* eMMC is shared pin with parallel NAND */
+       emmc_pins_default: emmc-pins-default {
+               mux {
+                       function = "emmc", "emmc_rst";
+                       groups = "emmc";
+               };
+
+               /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+                * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+                * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+                */
+               conf-cmd-dat {
+                       pins = "NDL0", "NDL1", "NDL2",
+                              "NDL3", "NDL4", "NDL5",
+                              "NDL6", "NDL7", "NRB";
+                       input-enable;
+                       bias-pull-up;
+               };
+
+               conf-clk {
+                       pins = "NCLE";
+                       bias-pull-down;
+               };
+       };
+
+       emmc_pins_uhs: emmc-pins-uhs {
+               mux {
+                       function = "emmc";
+                       groups = "emmc";
+               };
+
+               conf-cmd-dat {
+                       pins = "NDL0", "NDL1", "NDL2",
+                              "NDL3", "NDL4", "NDL5",
+                              "NDL6", "NDL7", "NRB";
+                       input-enable;
+                       drive-strength = <4>;
+                       bias-pull-up;
+               };
+
+               conf-clk {
+                       pins = "NCLE";
+                       drive-strength = <4>;
+                       bias-pull-down;
+               };
+       };
+
+       eth_pins: eth-pins {
+               mux {
+                       function = "eth";
+                       groups = "mdc_mdio", "rgmii_via_gmac2";
+               };
+       };
+
+       i2c1_pins: i2c1-pins {
+               mux {
+                       function = "i2c";
+                       groups =  "i2c1_0";
+               };
+       };
+
+       i2c2_pins: i2c2-pins {
+               mux {
+                       function = "i2c";
+                       groups =  "i2c2_0";
+               };
+       };
+
+       i2s1_pins: i2s1-pins {
+               mux {
+                       function = "i2s";
+                       groups =  "i2s_out_mclk_bclk_ws",
+                                 "i2s1_in_data",
+                                 "i2s1_out_data";
+               };
+
+               conf {
+                       pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
+                              "I2S_WS", "I2S_MCLK";
+                       drive-strength = <12>;
+                       bias-pull-down;
+               };
+       };
+
+       irrx_pins: irrx-pins {
+               mux {
+                       function = "ir";
+                       groups =  "ir_1_rx";
+               };
+       };
+
+       irtx_pins: irtx-pins {
+               mux {
+                       function = "ir";
+                       groups =  "ir_1_tx";
+               };
+       };
+
+       /* Parallel nand is shared pin with eMMC */
+       parallel_nand_pins: parallel-nand-pins {
+               mux {
+                       function = "flash";
+                       groups = "par_nand";
+               };
+       };
+
+       pcie0_pins: pcie0-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie0_pad_perst",
+                                "pcie0_1_waken",
+                                "pcie0_1_clkreq";
+               };
+       };
+
+       pcie1_pins: pcie1-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie1_pad_perst",
+                                "pcie1_0_waken",
+                                "pcie1_0_clkreq";
+               };
+       };
+
+       pmic_bus_pins: pmic-bus-pins {
+               mux {
+                       function = "pmic";
+                       groups = "pmic_bus";
+               };
+       };
+
+       pwm7_pins: pwm1-2-pins {
+               mux {
+                       function = "pwm";
+                       groups = "pwm_ch7_2";
+               };
+       };
+
+       wled_pins: wled-pins {
+               mux {
+                       function = "led";
+                       groups = "wled";
+               };
+       };
+
+       sd0_pins_default: sd0-pins-default {
+               mux {
+                       function = "sd";
+                       groups = "sd_0";
+               };
+
+               /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+                *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+                *  DAT2, DAT3, CMD, CLK for SD respectively.
+                */
+               conf-cmd-data {
+                       pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+                              "I2S2_IN","I2S4_OUT";
+                       input-enable;
+                       drive-strength = <8>;
+                       bias-pull-up;
+               };
+               conf-clk {
+                       pins = "I2S3_OUT";
+                       drive-strength = <12>;
+                       bias-pull-down;
+               };
+               conf-cd {
+                       pins = "TXD3";
+                       bias-pull-up;
+               };
+       };
+
+       sd0_pins_uhs: sd0-pins-uhs {
+               mux {
+                       function = "sd";
+                       groups = "sd_0";
+               };
+
+               conf-cmd-data {
+                       pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+                              "I2S2_IN","I2S4_OUT";
+                       input-enable;
+                       bias-pull-up;
+               };
+
+               conf-clk {
+                       pins = "I2S3_OUT";
+                       bias-pull-down;
+               };
+       };
+
+       /* Serial NAND is shared pin with SPI-NOR */
+       serial_nand_pins: serial-nand-pins {
+               mux {
+                       function = "flash";
+                       groups = "snfi";
+               };
+       };
+
+       spic0_pins: spic0-pins {
+               mux {
+                       function = "spi";
+                       groups = "spic0_0";
+               };
+       };
+
+       spic1_pins: spic1-pins {
+               mux {
+                       function = "spi";
+                       groups = "spic1_0";
+               };
+       };
+
+       /* SPI-NOR is shared pin with serial NAND */
+       spi_nor_pins: spi-nor-pins {
+               mux {
+                       function = "flash";
+                       groups = "spi_nor";
+               };
+       };
+
+       /* serial NAND is shared pin with SPI-NOR */
+       serial_nand_pins: serial-nand-pins {
+               mux {
+                       function = "flash";
+                       groups = "snfi";
+               };
+       };
+
+       uart0_pins: uart0-pins {
+               mux {
+                       function = "uart";
+                       groups = "uart0_0_tx_rx" ;
+               };
+       };
+
+       uart2_pins: uart2-pins {
+               mux {
+                       function = "uart";
+                       groups = "uart2_1_tx_rx" ;
+               };
+       };
+
+       watchdog_pins: watchdog-pins {
+               mux {
+                       function = "watchdog";
+                       groups = "watchdog";
+               };
+       };
+};
+
+&pwm {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pwm7_pins>;
+       status = "okay";
+};
+
+&pwrap {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pmic_bus_pins>;
+
+       status = "okay";
+};
+
+&sata {
+       status = "disable";
+};
+
+&sata_phy {
+       status = "disable";
+};
+
+&spi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spic0_pins>;
+       status = "okay";
+};
+
+&spi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spic1_pins>;
+       status = "okay";
+};
+
+&ssusb {
+       vusb33-supply = <&reg_3p3v>;
+       vbus-supply = <&reg_5v>;
+       status = "okay";
+};
+
+&u3phy {
+       status = "okay";
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart2_pins>;
+       status = "okay";
+};
+
+&watchdog {
+       pinctrl-names = "default";
+       pinctrl-0 = <&watchdog_pins>;
+       status = "okay";
+};
+
+&gsw {
+       mediatek,mdio = <&mdio>;
+       mediatek,portmap = "llllw";
+       mediatek,mdio_master_pinmux = <0>;
+       reset-gpios = <&pio 54 0>;
+       interrupt-parent = <&pio>;
+       interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+       status = "okay";
+
+       port5: port@5 {
+               compatible = "mediatek,mt753x-port";
+               reg = <5>;
+               phy-mode = "rgmii";
+               fixed-link {
+                       speed = <1000>;
+                       full-duplex;
+               };
+       };
+
+       port6: port@6 {
+               compatible = "mediatek,mt753x-port";
+               reg = <6>;
+               phy-mode = "sgmii";
+               fixed-link {
+                       speed = <2500>;
+                       full-duplex;
+               };
+       };
+};
+
+

diff --git a/target/linux/mediatek/files-4.14/arch/arm64/boot/dts/mediatek/mt7622-lynx-rfb1.dts b/target/linux/mediatek/files-4.14/arch/arm64/boot/dts/mediatek/mt7622-lynx-rfb1.dts
new file mode 100755 (executable)
index 0000000..f8423fc
--- /dev/null
+++ b/target/linux/mediatek/files-4.14/arch/arm64/boot/dts/mediatek/mt7622-lynx-rfb1.dts
@@ -0,0 +1,549 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ming Huang <ming.huang@mediatek.com>
+ *        Sean Wang <sean.wang@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "mt7622.dtsi"
+#include "mt6380.dtsi"
+
+/ {
+       model = "MediaTek MT7622 RFB1 board";
+       compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+               bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
+       };
+
+       cpus {
+               cpu@0 {
+                       proc-supply = <&mt6380_vcpu_reg>;
+                       sram-supply = <&mt6380_vm_reg>;
+               };
+
+               cpu@1 {
+                       proc-supply = <&mt6380_vcpu_reg>;
+                       sram-supply = <&mt6380_vm_reg>;
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+               poll-interval = <100>;
+
+               factory {
+                       label = "factory";
+                       linux,code = <BTN_0>;
+                       gpios = <&pio 0 0>;
+               };
+
+               wps {
+                       label = "wps";
+                       linux,code = <KEY_WPS_BUTTON>;
+                       gpios = <&pio 102 0>;
+               };
+       };
+
+       gsw: gsw@0 {
+               compatible = "mediatek,mt753x";
+               mediatek,ethsys = <&ethsys>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       memory {
+               reg = <0 0x40000000 0 0x3F000000>;
+       };
+
+       reg_1p8v: regulator-1p8v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-1.8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+       };
+
+       reg_3p3v: regulator-3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       reg_5v: regulator-5v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-5V";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+};
+
+&pcie {
+       pinctrl-names = "default", "pcie1_pins";
+       pinctrl-0 = <&pcie0_pins>;
+       pinctrl-1 = <&pcie1_pins>;
+       status = "okay";
+
+       pcie@0,0 {
+               status = "okay";
+       };
+
+       pcie@1,0 {
+               status = "okay";
+       };
+
+};
+
+&pio {
+       /* eMMC is shared pin with parallel NAND */
+       emmc_pins_default: emmc-pins-default {
+               mux {
+                       function = "emmc", "emmc_rst";
+                       groups = "emmc";
+               };
+
+               /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+                * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+                * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+                */
+               conf-cmd-dat {
+                       pins = "NDL0", "NDL1", "NDL2",
+                              "NDL3", "NDL4", "NDL5",
+                              "NDL6", "NDL7", "NRB";
+                       input-enable;
+                       bias-pull-up;
+               };
+
+               conf-clk {
+                       pins = "NCLE";
+                       bias-pull-down;
+               };
+       };
+
+       emmc_pins_uhs: emmc-pins-uhs {
+               mux {
+                       function = "emmc";
+                       groups = "emmc";
+               };
+
+               conf-cmd-dat {
+                       pins = "NDL0", "NDL1", "NDL2",
+                              "NDL3", "NDL4", "NDL5",
+                              "NDL6", "NDL7", "NRB";
+                       input-enable;
+                       drive-strength = <4>;
+                       bias-pull-up;
+               };
+
+               conf-clk {
+                       pins = "NCLE";
+                       drive-strength = <4>;
+                       bias-pull-down;
+               };
+       };
+
+       eth_pins: eth-pins {
+               mux {
+                       function = "eth";
+                       groups = "mdc_mdio", "rgmii_via_gmac2";
+               };
+       };
+
+       i2c1_pins: i2c1-pins {
+               mux {
+                       function = "i2c";
+                       groups =  "i2c1_0";
+               };
+       };
+
+       i2c2_pins: i2c2-pins {
+               mux {
+                       function = "i2c";
+                       groups =  "i2c2_0";
+               };
+       };
+
+       i2s1_pins: i2s1-pins {
+               mux {
+                       function = "i2s";
+                       groups =  "i2s_out_mclk_bclk_ws",
+                                 "i2s1_in_data",
+                                 "i2s1_out_data";
+               };
+
+               conf {
+                       pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
+                              "I2S_WS", "I2S_MCLK";
+                       drive-strength = <12>;
+                       bias-pull-down;
+               };
+       };
+
+       irrx_pins: irrx-pins {
+               mux {
+                       function = "ir";
+                       groups =  "ir_1_rx";
+               };
+       };
+
+       irtx_pins: irtx-pins {
+               mux {
+                       function = "ir";
+                       groups =  "ir_1_tx";
+               };
+       };
+
+       /* Parallel nand is shared pin with eMMC */
+       parallel_nand_pins: parallel-nand-pins {
+               mux {
+                       function = "flash";
+                       groups = "par_nand";
+               };
+       };
+
+       pcie0_pins: pcie0-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie0_pad_perst",
+                                "pcie0_1_waken",
+                                "pcie0_1_clkreq";
+               };
+       };
+
+       pcie1_pins: pcie1-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie1_pad_perst",
+                                "pcie1_0_waken",
+                                "pcie1_0_clkreq";
+               };
+       };
+
+       pmic_bus_pins: pmic-bus-pins {
+               mux {
+                       function = "pmic";
+                       groups = "pmic_bus";
+               };
+       };
+
+       pwm7_pins: pwm1-2-pins {
+               mux {
+                       function = "pwm";
+                       groups = "pwm_ch7_2";
+               };
+       };
+
+       wled_pins: wled-pins {
+               mux {
+                       function = "led";
+                       groups = "wled";
+               };
+       };
+
+       sd0_pins_default: sd0-pins-default {
+               mux {
+                       function = "sd";
+                       groups = "sd_0";
+               };
+
+               /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+                *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+                *  DAT2, DAT3, CMD, CLK for SD respectively.
+                */
+               conf-cmd-data {
+                       pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+                              "I2S2_IN","I2S4_OUT";
+                       input-enable;
+                       drive-strength = <8>;
+                       bias-pull-up;
+               };
+               conf-clk {
+                       pins = "I2S3_OUT";
+                       drive-strength = <12>;
+                       bias-pull-down;
+               };
+               conf-cd {
+                       pins = "TXD3";
+                       bias-pull-up;
+               };
+       };
+
+       sd0_pins_uhs: sd0-pins-uhs {
+               mux {
+                       function = "sd";
+                       groups = "sd_0";
+               };
+
+               conf-cmd-data {
+                       pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+                              "I2S2_IN","I2S4_OUT";
+                       input-enable;
+                       bias-pull-up;
+               };
+
+               conf-clk {
+                       pins = "I2S3_OUT";
+                       bias-pull-down;
+               };
+       };
+
+       /* Serial NAND is shared pin with SPI-NOR */
+       serial_nand_pins: serial-nand-pins {
+               mux {
+                       function = "flash";
+                       groups = "snfi";
+               };
+       };
+
+       spic0_pins: spic0-pins {
+               mux {
+                       function = "spi";
+                       groups = "spic0_0";
+               };
+       };
+
+       spic1_pins: spic1-pins {
+               mux {
+                       function = "spi";
+                       groups = "spic1_0";
+               };
+       };
+
+       /* SPI-NOR is shared pin with serial NAND */
+       spi_nor_pins: spi-nor-pins {
+               mux {
+                       function = "flash";
+                       groups = "spi_nor";
+               };
+       };
+
+       /* serial NAND is shared pin with SPI-NOR */
+       serial_nand_pins: serial-nand-pins {
+               mux {
+                       function = "flash";
+                       groups = "snfi";
+               };
+       };
+
+       uart0_pins: uart0-pins {
+               mux {
+                       function = "uart";
+                       groups = "uart0_0_tx_rx" ;
+               };
+       };
+
+       uart2_pins: uart2-pins {
+               mux {
+                       function = "uart";
+                       groups = "uart2_1_tx_rx" ;
+               };
+       };
+
+       watchdog_pins: watchdog-pins {
+               mux {
+                       function = "watchdog";
+                       groups = "watchdog";
+               };
+       };
+};
+
+&bch {
+       status = "okay";
+};
+
+&btif {
+       status = "okay";
+};
+
+&cir {
+       pinctrl-names = "default";
+       pinctrl-0 = <&irrx_pins>;
+       status = "okay";
+};
+
+&eth {
+       status = "okay";
+       gmac0: mac@0 {
+                compatible = "mediatek,eth-mac";
+                reg = <0>;
+                phy-mode = "sgmii";
+                fixed-link {
+                        speed = <1000>;
+                        full-duplex;
+                        pause;
+                };
+        };
+        gmac1: mac@1 {
+                compatible = "mediatek,eth-mac";
+                reg = <1>;
+                phy-mode = "rgmii";
+                fixed-link {
+                        speed = <1000>;
+                        full-duplex;
+                        pause;
+                };
+        };
+        mdio: mdio-bus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+};
+
+&gsw {
+       mediatek,mdio = <&mdio>;
+       mediatek,portmap = "llllw";
+       mediatek,mdio_master_pinmux = <0>;
+       reset-gpios = <&pio 54 0>;
+       interrupt-parent = <&pio>;
+       interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+       status = "okay";
+
+       port5: port@5 {
+               compatible = "mediatek,mt753x-port";
+               reg = <5>;
+               phy-mode = "rgmii";
+               fixed-link {
+                       speed = <1000>;
+                       full-duplex;
+               };
+       };
+
+       port6: port@6 {
+               compatible = "mediatek,mt753x-port";
+               reg = <6>;
+               phy-mode = "sgmii";
+               fixed-link {
+                       speed = <2500>;
+                       full-duplex;
+               };
+       };
+};
+
+&i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c1_pins>;
+       status = "okay";
+};
+
+&i2c2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c2_pins>;
+       status = "okay";
+};
+
+&mmc0 {
+       pinctrl-names = "default", "state_uhs";
+       pinctrl-0 = <&emmc_pins_default>;
+       pinctrl-1 = <&emmc_pins_uhs>;
+       status = "okay";
+       bus-width = <8>;
+       max-frequency = <50000000>;
+       cap-mmc-highspeed;
+       mmc-hs200-1_8v;
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_1p8v>;
+       assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+       assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+       non-removable;
+};
+
+&mmc1 {
+       pinctrl-names = "default", "state_uhs";
+       pinctrl-0 = <&sd0_pins_default>;
+       pinctrl-1 = <&sd0_pins_uhs>;
+       status = "okay";
+       bus-width = <4>;
+       max-frequency = <50000000>;
+       cap-sd-highspeed;
+       r_smpl = <1>;
+       cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_3p3v>;
+       assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+       assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+};
+
+&nandc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&parallel_nand_pins>;
+       status = "disabled";
+};
+
+&nor_flash {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi_nor_pins>;
+       status = "disabled";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+       };
+};
+
+&pwm {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pwm7_pins>;
+       status = "okay";
+};
+
+&pwrap {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pmic_bus_pins>;
+
+       status = "okay";
+};
+
+&spi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spic0_pins>;
+       status = "okay";
+};
+
+&spi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spic1_pins>;
+       status = "okay";
+};
+
+&ssusb {
+       vusb33-supply = <&reg_3p3v>;
+       vbus-supply = <&reg_5v>;
+       status = "okay";
+};
+
+&u3phy {
+       status = "okay";
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart2_pins>;
+       status = "okay";
+};
+
+&watchdog {
+       pinctrl-names = "default";
+       pinctrl-0 = <&watchdog_pins>;
+       status = "okay";
+};