drm/radeon: fix up pll selection on DCE5/6

Selecting ATOM_PPLL_INVALID should be equivalent as the
DCPLL or PPLL0 are already programmed for the DISPCLK, but
the preferred method is to always specify the PLL selected.
SetPixelClock will check the parameters and skip the
programming if the PLL is already set up.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 3904d7964a4b02e3b0e34930f3bc97a65c07add3..bbbeb98d4bb7d2b199322e2f5b31d064efeab531 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1539,7 +1539,11 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
                                 * crtc virtual pixel clock.
                                 */
                                if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
-                                       if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
+                                       if (ASIC_IS_DCE5(rdev))
+                                               return ATOM_DCPLL;
+                                       else if (ASIC_IS_DCE6(rdev))
+                                               return ATOM_PPLL0;
+                                       else if (rdev->clock.dp_extclk)
                                                return ATOM_PPLL_INVALID;
                                }
                        }