+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ARCH_BCM is not set
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-# CONFIG_ARCH_MULTI_V6 is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MVEBU=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SUNXI is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARCH_VIRT is not set
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-# CONFIG_ARCH_WM8850 is not set
-CONFIG_ARM=y
-CONFIG_ARMADA_370_XP_TIMER=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BOUNCE=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CACHE_PL310=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PJ4B=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/mvebu.S"
-CONFIG_DEBUG_MVEBU_UART=y
-# CONFIG_DEBUG_MVEBU_UART_ALTERNATE is not set
-# CONFIG_DEBUG_PINCTRL is not set
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DEBUG_USER=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_FAT_FS=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_DEBUG=y
-CONFIG_IRQ_WORK=y
-CONFIG_ISO9660_FS=y
-CONFIG_JBD=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LOCAL_TIMERS=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MACH_ARMADA_370=y
-CONFIG_MACH_ARMADA_370_XP=y
-CONFIG_MACH_ARMADA_XP=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MEMORY=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MSDOS_FS=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_PXA3xx=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP_OF=y
-# CONFIG_MTD_SM_COMMON is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MVEBU_CLK_CORE=y
-CONFIG_MVEBU_CLK_COREDIV=y
-CONFIG_MVEBU_CLK_CPU=y
-CONFIG_MVEBU_CLK_GATING=y
-CONFIG_MVEBU_DEVBUS=y
-CONFIG_MVEBU_MBUS=y
-CONFIG_MVMDIO=y
-CONFIG_MVNETA=y
-CONFIG_MV_XOR=y
-CONFIG_NEED_DMA_MAP_STATE=y
-# CONFIG_NEON is not set
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_UTF8=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MVEBU=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_370=y
-CONFIG_PINCTRL_ARMADA_XP=y
-CONFIG_PINCTRL_MVEBU=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINMUX=y
-CONFIG_PJ4B_ERRATA_4742=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_PLAT_ORION=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_MV is not set
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_ORION=y
-CONFIG_STOP_MACHINE=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TEGRA_HOST1X is not set
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_STATS=y
-CONFIG_TREE_RCU=y
-CONFIG_UID16=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-# CONFIG_XEN is not set
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-From 6c52eba54044791592aefd139bdc2a7b6127e981 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 17 Apr 2013 16:51:34 -0300
-Subject: [PATCH 001/203] ARM: mvebu: Add support for USB storage class in
- mvebu_defconfig
-
-Some boards can have built-in USB storage class controllers so
-it's better to have this option included by default.
-
-Currently this option is needed to support built-in USB MMC controller
-found in Globalscale Mirabox board.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/configs/mvebu_defconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/configs/mvebu_defconfig
-+++ b/arch/arm/configs/mvebu_defconfig
-@@ -60,6 +60,7 @@ CONFIG_USB_SUPPORT=y
- CONFIG_USB=y
- CONFIG_USB_EHCI_HCD=y
- CONFIG_USB_EHCI_ROOT_HUB_TT=y
-+CONFIG_USB_STORAGE=y
- CONFIG_MMC=y
- CONFIG_MMC_MVSDIO=y
- CONFIG_NEW_LEDS=y
+++ /dev/null
-From cf6eb4599d60cb9fa81465aa018c71d11e19ea6a Mon Sep 17 00:00:00 2001
-From: Simon Baatz <gmbnomis@gmail.com>
-Date: Mon, 13 May 2013 23:18:58 +0200
-Subject: [PATCH 002/203] ARM: mvebu: Use standard MMC binding for all users of
- mvsdio
-
-In order to prepare the switch to the standard MMC device tree parser
-for mvsdio, adapt all current uses of mvsdio in the dts files to the
-standard format.
-
-Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370-db.dts | 1 +
- arch/arm/boot/dts/armada-370-mirabox.dts | 1 +
- arch/arm/boot/dts/armada-370-rd.dts | 1 +
- arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++++
- arch/arm/boot/dts/armada-xp-db.dts | 1 +
- arch/arm/boot/dts/kirkwood-dreamplug.dts | 1 +
- arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | 2 ++
- arch/arm/boot/dts/kirkwood-mplcec4.dts | 2 +-
- arch/arm/boot/dts/kirkwood-topkick.dts | 1 +
- arch/arm/boot/dts/kirkwood.dtsi | 4 ++++
- 10 files changed, 17 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/armada-370-db.dts
-+++ b/arch/arm/boot/dts/armada-370-db.dts
-@@ -74,6 +74,7 @@
- */
- status = "disabled";
- /* No CD or WP GPIOs */
-+ broken-cd;
- };
-
- usb@50000 {
---- a/arch/arm/boot/dts/armada-370-mirabox.dts
-+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
-@@ -99,6 +99,7 @@
- * No CD or WP GPIOs: SDIO interface used for
- * Wifi/Bluetooth chip
- */
-+ broken-cd;
- };
-
- usb@50000 {
---- a/arch/arm/boot/dts/armada-370-rd.dts
-+++ b/arch/arm/boot/dts/armada-370-rd.dts
-@@ -64,6 +64,7 @@
- pinctrl-names = "default";
- status = "okay";
- /* No CD or WP GPIOs */
-+ broken-cd;
- };
-
- usb@50000 {
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -143,6 +143,10 @@
- reg = <0xd4000 0x200>;
- interrupts = <54>;
- clocks = <&gateclk 17>;
-+ bus-width = <4>;
-+ cap-sdio-irq;
-+ cap-sd-highspeed;
-+ cap-mmc-highspeed;
- status = "disabled";
- };
-
---- a/arch/arm/boot/dts/armada-xp-db.dts
-+++ b/arch/arm/boot/dts/armada-xp-db.dts
-@@ -97,6 +97,7 @@
- pinctrl-names = "default";
- status = "okay";
- /* No CD or WP GPIOs */
-+ broken-cd;
- };
-
- usb@50000 {
---- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
-+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
-@@ -79,6 +79,7 @@
- pinctrl-names = "default";
- status = "okay";
- /* No CD or WP GPIOs */
-+ broken-cd;
- };
- };
-
---- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
-+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
-@@ -72,6 +72,8 @@
-
- mvsdio@90000 {
- status = "okay";
-+ /* No CD or WP GPIOs */
-+ broken-cd;
- };
- };
-
---- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
-+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
-@@ -136,7 +136,7 @@
- pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
- pinctrl-names = "default";
- status = "okay";
-- cd-gpios = <&gpio1 15 0>;
-+ cd-gpios = <&gpio1 15 1>;
- /* No WP GPIO */
- };
- };
---- a/arch/arm/boot/dts/kirkwood-topkick.dts
-+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
-@@ -154,6 +154,7 @@
- pinctrl-names = "default";
- status = "okay";
- /* No CD or WP GPIOs */
-+ broken-cd;
- };
- };
-
---- a/arch/arm/boot/dts/kirkwood.dtsi
-+++ b/arch/arm/boot/dts/kirkwood.dtsi
-@@ -200,6 +200,10 @@
- reg = <0x90000 0x200>;
- interrupts = <28>;
- clocks = <&gate_clk 4>;
-+ bus-width = <4>;
-+ cap-sdio-irq;
-+ cap-sd-highspeed;
-+ cap-mmc-highspeed;
- status = "disabled";
- };
- };
+++ /dev/null
-From 74cd8c09ae416261d7595021fc8062836dc750a2 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Fri, 17 May 2013 08:09:58 -0300
-Subject: [PATCH 003/203] ARM: mvebu: Add support for NOR flash device on
- Armada XP-DB board
-
-The Armada XP Development Board (DB-78460-BP) has a NOR flash device
-connected to the Device Bus. This commit adds the device tree node
-to support this device.
-
-This SoC supports a flexible and dynamic decoding window allocation
-scheme; but since this feature is still not implemented we need
-to specify the window base address in the device tree node itself.
-
-This base address has been selected in a completely arbitrary fashion.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-xp-db.dts | 32 ++++++++++++++++++++++++++++++++
- 1 file changed, 32 insertions(+)
-
---- a/arch/arm/boot/dts/armada-xp-db.dts
-+++ b/arch/arm/boot/dts/armada-xp-db.dts
-@@ -30,6 +30,9 @@
- };
-
- soc {
-+ ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
-+ 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
-+
- internal-regs {
- serial@12000 {
- clock-frequency = <250000000>;
-@@ -156,6 +159,35 @@
- status = "okay";
- };
- };
-+
-+ devbus-bootcs@10400 {
-+ status = "okay";
-+ ranges = <0 0xf0000000 0x1000000>;
-+
-+ /* Device Bus parameters are required */
-+
-+ /* Read parameters */
-+ devbus,bus-width = <8>;
-+ devbus,turn-off-ps = <60000>;
-+ devbus,badr-skew-ps = <0>;
-+ devbus,acc-first-ps = <124000>;
-+ devbus,acc-next-ps = <248000>;
-+ devbus,rd-setup-ps = <0>;
-+ devbus,rd-hold-ps = <0>;
-+
-+ /* Write parameters */
-+ devbus,sync-enable = <0>;
-+ devbus,wr-high-ps = <60000>;
-+ devbus,wr-low-ps = <60000>;
-+ devbus,ale-wr-ps = <60000>;
-+
-+ /* NOR 16 MiB */
-+ nor@0 {
-+ compatible = "cfi-flash";
-+ reg = <0 0x1000000>;
-+ bank-width = <2>;
-+ };
-+ };
- };
- };
- };
+++ /dev/null
-From 7d375772a601bdf227902454705e402fc65b8bdf Mon Sep 17 00:00:00 2001
-From: Andrew Murray <Andrew.Murray@arm.com>
-Date: Tue, 7 May 2013 16:31:12 +0100
-Subject: [PATCH 004/203] of/pci: Provide support for parsing PCI DT ranges
- property
-
-This patch factors out common implementation patterns to reduce overall kernel
-code and provide a means for host bridge drivers to directly obtain struct
-resources from the DT's ranges property without relying on architecture specific
-DT handling. This will make it easier to write archiecture independent host bridge
-drivers and mitigate against further duplication of DT parsing code.
-
-This patch can be used in the following way:
-
- struct of_pci_range_parser parser;
- struct of_pci_range range;
-
- if (of_pci_range_parser_init(&parser, np))
- ; //no ranges property
-
- for_each_of_pci_range(&parser, &range) {
-
- /*
- directly access properties of the address range, e.g.:
- range.pci_space, range.pci_addr, range.cpu_addr,
- range.size, range.flags
-
- alternatively obtain a struct resource, e.g.:
- struct resource res;
- of_pci_range_to_resource(&range, np, &res);
- */
- }
-
-Additionally the implementation takes care of adjacent ranges and merges them
-into a single range (as was the case with powerpc and microblaze).
-
-Signed-off-by: Andrew Murray <Andrew.Murray@arm.com>
-Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Reviewed-by: Rob Herring <rob.herring@calxeda.com>
-Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Linus Walleij <linus.walleij@linaro.org>
-Tested-by: Jingoo Han <jg1.han@samsung.com>
-Acked-by: Grant Likely <grant.likely@secretlab.ca>
----
- drivers/of/address.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++
- include/linux/of_address.h | 48 +++++++++++++++++++++++++++++++++
- 2 files changed, 115 insertions(+)
-
---- a/drivers/of/address.c
-+++ b/drivers/of/address.c
-@@ -224,6 +224,73 @@ int of_pci_address_to_resource(struct de
- return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
- }
- EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
-+
-+int of_pci_range_parser_init(struct of_pci_range_parser *parser,
-+ struct device_node *node)
-+{
-+ const int na = 3, ns = 2;
-+ int rlen;
-+
-+ parser->node = node;
-+ parser->pna = of_n_addr_cells(node);
-+ parser->np = parser->pna + na + ns;
-+
-+ parser->range = of_get_property(node, "ranges", &rlen);
-+ if (parser->range == NULL)
-+ return -ENOENT;
-+
-+ parser->end = parser->range + rlen / sizeof(__be32);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
-+
-+struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
-+ struct of_pci_range *range)
-+{
-+ const int na = 3, ns = 2;
-+
-+ if (!range)
-+ return NULL;
-+
-+ if (!parser->range || parser->range + parser->np > parser->end)
-+ return NULL;
-+
-+ range->pci_space = parser->range[0];
-+ range->flags = of_bus_pci_get_flags(parser->range);
-+ range->pci_addr = of_read_number(parser->range + 1, ns);
-+ range->cpu_addr = of_translate_address(parser->node,
-+ parser->range + na);
-+ range->size = of_read_number(parser->range + parser->pna + na, ns);
-+
-+ parser->range += parser->np;
-+
-+ /* Now consume following elements while they are contiguous */
-+ while (parser->range + parser->np <= parser->end) {
-+ u32 flags, pci_space;
-+ u64 pci_addr, cpu_addr, size;
-+
-+ pci_space = be32_to_cpup(parser->range);
-+ flags = of_bus_pci_get_flags(parser->range);
-+ pci_addr = of_read_number(parser->range + 1, ns);
-+ cpu_addr = of_translate_address(parser->node,
-+ parser->range + na);
-+ size = of_read_number(parser->range + parser->pna + na, ns);
-+
-+ if (flags != range->flags)
-+ break;
-+ if (pci_addr != range->pci_addr + range->size ||
-+ cpu_addr != range->cpu_addr + range->size)
-+ break;
-+
-+ range->size += size;
-+ parser->range += parser->np;
-+ }
-+
-+ return range;
-+}
-+EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
-+
- #endif /* CONFIG_PCI */
-
- /*
---- a/include/linux/of_address.h
-+++ b/include/linux/of_address.h
-@@ -4,6 +4,36 @@
- #include <linux/errno.h>
- #include <linux/of.h>
-
-+struct of_pci_range_parser {
-+ struct device_node *node;
-+ const __be32 *range;
-+ const __be32 *end;
-+ int np;
-+ int pna;
-+};
-+
-+struct of_pci_range {
-+ u32 pci_space;
-+ u64 pci_addr;
-+ u64 cpu_addr;
-+ u64 size;
-+ u32 flags;
-+};
-+
-+#define for_each_of_pci_range(parser, range) \
-+ for (; of_pci_range_parser_one(parser, range);)
-+
-+static inline void of_pci_range_to_resource(struct of_pci_range *range,
-+ struct device_node *np,
-+ struct resource *res)
-+{
-+ res->flags = range->flags;
-+ res->start = range->cpu_addr;
-+ res->end = range->cpu_addr + range->size - 1;
-+ res->parent = res->child = res->sibling = NULL;
-+ res->name = np->full_name;
-+}
-+
- #ifdef CONFIG_OF_ADDRESS
- extern u64 of_translate_address(struct device_node *np, const __be32 *addr);
- extern bool of_can_translate_address(struct device_node *dev);
-@@ -27,6 +57,11 @@ static inline unsigned long pci_address_
- #define pci_address_to_pio pci_address_to_pio
- #endif
-
-+extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
-+ struct device_node *node);
-+extern struct of_pci_range *of_pci_range_parser_one(
-+ struct of_pci_range_parser *parser,
-+ struct of_pci_range *range);
- #else /* CONFIG_OF_ADDRESS */
- #ifndef of_address_to_resource
- static inline int of_address_to_resource(struct device_node *dev, int index,
-@@ -53,6 +88,19 @@ static inline const __be32 *of_get_addre
- {
- return NULL;
- }
-+
-+static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
-+ struct device_node *node)
-+{
-+ return -1;
-+}
-+
-+static inline struct of_pci_range *of_pci_range_parser_one(
-+ struct of_pci_range_parser *parser,
-+ struct of_pci_range *range)
-+{
-+ return NULL;
-+}
- #endif /* CONFIG_OF_ADDRESS */
-
-
+++ /dev/null
-From 3f368ae1994efc17b59ffd34307c76b1f642527e Mon Sep 17 00:00:00 2001
-From: Thierry Reding <thierry.reding@avionic-design.de>
-Date: Mon, 11 Feb 2013 09:22:20 +0100
-Subject: [PATCH 006/203] of/pci: Add of_pci_parse_bus_range() function
-
-This function can be used to parse a bus-range property as specified by
-device nodes representing PCI bridges.
-
-Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
----
- drivers/of/of_pci.c | 25 +++++++++++++++++++++++++
- include/linux/of_pci.h | 1 +
- 2 files changed, 26 insertions(+)
-
---- a/drivers/of/of_pci.c
-+++ b/drivers/of/of_pci.c
-@@ -64,3 +64,28 @@ int of_pci_get_devfn(struct device_node
- return (be32_to_cpup(reg) >> 8) & 0xff;
- }
- EXPORT_SYMBOL_GPL(of_pci_get_devfn);
-+
-+/**
-+ * of_pci_parse_bus_range() - parse the bus-range property of a PCI device
-+ * @node: device node
-+ * @res: address to a struct resource to return the bus-range
-+ *
-+ * Returns 0 on success or a negative error-code on failure.
-+ */
-+int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
-+{
-+ const __be32 *values;
-+ int len;
-+
-+ values = of_get_property(node, "bus-range", &len);
-+ if (!values || len < sizeof(*values) * 2)
-+ return -EINVAL;
-+
-+ res->name = node->name;
-+ res->start = be32_to_cpup(values++);
-+ res->end = be32_to_cpup(values);
-+ res->flags = IORESOURCE_BUS;
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
---- a/include/linux/of_pci.h
-+++ b/include/linux/of_pci.h
-@@ -11,5 +11,6 @@ struct device_node;
- struct device_node *of_pci_find_child_device(struct device_node *parent,
- unsigned int devfn);
- int of_pci_get_devfn(struct device_node *np);
-+int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
-
- #endif
+++ /dev/null
-From f12aa05cbfb88e5541814ffa7be7e195471568bd Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 7 Dec 2012 20:35:20 +0100
-Subject: [PATCH 007/203] clk: mvebu: create parent-child relation for PCIe
- clocks on Armada 370
-
-The Armada 370 has two gatable clocks for each PCIe interface, and we
-want both of them to be enabled. We therefore make one of the two
-clocks a child of the other, as we did for the sataX and sataXlnk
-clocks on Armada XP.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Cc: Mike Turquette <mturquette@linaro.org>
----
- drivers/clk/mvebu/clk-gating-ctrl.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/mvebu/clk-gating-ctrl.c
-+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
-@@ -119,8 +119,8 @@ static const struct mvebu_soc_descr __in
- { "pex1_en", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
-- { "pex0", NULL, 5 },
-- { "pex1", NULL, 9 },
-+ { "pex0", "pex0_en", 5 },
-+ { "pex1", "pex1_en", 9 },
- { "sata0", NULL, 15 },
- { "sdio", NULL, 17 },
- { "tdm", NULL, 25 },
+++ /dev/null
-From 5006da299ae65cadf92932f2f7b062b5a8c65798 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 18 Jan 2013 16:42:01 +0100
-Subject: [PATCH 008/203] clk: mvebu: add more PCIe clocks for Armada XP
-
-The current revision of the datasheet only mentions the gatable clocks
-for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention
-the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0
-interfaces. After confirmation with Marvell engineers, this patch adds
-the missing gatable clocks for those PCIe interfaces.
-
-It also changes the name of the previously existing PCIe gatable
-clocks, in order to match the naming using the datasheets.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Cc: Mike Turquette <mturquette@linaro.org>
----
- drivers/clk/mvebu/clk-gating-ctrl.c | 14 ++++++++++----
- 1 file changed, 10 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/mvebu/clk-gating-ctrl.c
-+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
-@@ -137,10 +137,14 @@ static const struct mvebu_soc_descr __in
- { "ge2", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
-- { "pex0", NULL, 5 },
-- { "pex1", NULL, 6 },
-- { "pex2", NULL, 7 },
-- { "pex3", NULL, 8 },
-+ { "pex00", NULL, 5 },
-+ { "pex01", NULL, 6 },
-+ { "pex02", NULL, 7 },
-+ { "pex03", NULL, 8 },
-+ { "pex10", NULL, 9 },
-+ { "pex11", NULL, 10 },
-+ { "pex12", NULL, 11 },
-+ { "pex13", NULL, 12 },
- { "bp", NULL, 13 },
- { "sata0lnk", NULL, 14 },
- { "sata0", "sata0lnk", 15 },
-@@ -152,6 +156,8 @@ static const struct mvebu_soc_descr __in
- { "xor0", NULL, 22 },
- { "crypto", NULL, 23 },
- { "tdm", NULL, 25 },
-+ { "pex20", NULL, 26 },
-+ { "pex30", NULL, 27 },
- { "xor1", NULL, 28 },
- { "sata1lnk", NULL, 29 },
- { "sata1", "sata1lnk", 30 },
+++ /dev/null
-From cf7b5cb15e46b5357c60188b75b213a7f0b5fd32 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 18 Jan 2013 17:42:58 +0100
-Subject: [PATCH 009/203] pci: PCIe driver for Marvell Armada 370/XP systems
-
-This driver implements the support for the PCIe interfaces on the
-Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
-cover earlier families of Marvell SoCs, such as Dove, Orion and
-Kirkwood.
-
-The driver implements the hw_pci operations needed by the core ARM PCI
-code to setup PCI devices and get their corresponding IRQs, and the
-pci_ops operations that are used by the PCI core to read/write the
-configuration space of PCI devices.
-
-Since the PCIe interfaces of Marvell SoCs are completely separate and
-not linked together in a bus, this driver sets up an emulated PCI host
-bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
-interface.
-
-In addition, this driver enumerates the different PCIe slots, and for
-those having a device plugged in, it sets up the necessary address
-decoding windows, using the mvebu-mbus driver.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
----
- .../devicetree/bindings/pci/mvebu-pci.txt | 220 ++++++
- drivers/pci/Kconfig | 2 +
- drivers/pci/Makefile | 3 +
- drivers/pci/host/Kconfig | 8 +
- drivers/pci/host/Makefile | 1 +
- drivers/pci/host/pci-mvebu.c | 880 +++++++++++++++++++++
- 6 files changed, 1114 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
- create mode 100644 drivers/pci/host/Kconfig
- create mode 100644 drivers/pci/host/Makefile
- create mode 100644 drivers/pci/host/pci-mvebu.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
-@@ -0,0 +1,220 @@
-+* Marvell EBU PCIe interfaces
-+
-+Mandatory properties:
-+- compatible: one of the following values:
-+ marvell,armada-370-pcie
-+ marvell,armada-xp-pcie
-+- #address-cells, set to <3>
-+- #size-cells, set to <2>
-+- #interrupt-cells, set to <1>
-+- bus-range: PCI bus numbers covered
-+- device_type, set to "pci"
-+- ranges: ranges for the PCI memory and I/O regions, as well as the
-+ MMIO registers to control the PCIe interfaces.
-+
-+In addition, the Device Tree node must have sub-nodes describing each
-+PCIe interface, having the following mandatory properties:
-+- reg: used only for interrupt mapping, so only the first four bytes
-+ are used to refer to the correct bus number and device number.
-+- assigned-addresses: reference to the MMIO registers used to control
-+ this PCIe interface.
-+- clocks: the clock associated to this PCIe interface
-+- marvell,pcie-port: the physical PCIe port number
-+- status: either "disabled" or "okay"
-+- device_type, set to "pci"
-+- #address-cells, set to <3>
-+- #size-cells, set to <2>
-+- #interrupt-cells, set to <1>
-+- ranges, empty property.
-+- interrupt-map-mask and interrupt-map, standard PCI properties to
-+ define the mapping of the PCIe interface to interrupt numbers.
-+
-+and the following optional properties:
-+- marvell,pcie-lane: the physical PCIe lane number, for ports having
-+ multiple lanes. If this property is not found, we assume that the
-+ value is 0.
-+
-+Example:
-+
-+pcie-controller {
-+ compatible = "marvell,armada-xp-pcie";
-+ status = "disabled";
-+ device_type = "pci";
-+
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ bus-range = <0x00 0xff>;
-+
-+ ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
-+ 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
-+ 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
-+ 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
-+ 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
-+ 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
-+ 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
-+ 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
-+ 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
-+ 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
-+ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
-+ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-+
-+ pcie@1,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
-+ reg = <0x0800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 58>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 5>;
-+ status = "disabled";
-+ };
-+
-+ pcie@2,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
-+ reg = <0x1000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 59>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <1>;
-+ clocks = <&gateclk 6>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
-+ reg = <0x1800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 60>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <2>;
-+ clocks = <&gateclk 7>;
-+ status = "disabled";
-+ };
-+
-+ pcie@4,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
-+ reg = <0x2000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 61>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <3>;
-+ clocks = <&gateclk 8>;
-+ status = "disabled";
-+ };
-+
-+ pcie@5,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
-+ reg = <0x2800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 62>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 9>;
-+ status = "disabled";
-+ };
-+
-+ pcie@6,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
-+ reg = <0x3000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 63>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <1>;
-+ clocks = <&gateclk 10>;
-+ status = "disabled";
-+ };
-+
-+ pcie@7,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
-+ reg = <0x3800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 64>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <2>;
-+ clocks = <&gateclk 11>;
-+ status = "disabled";
-+ };
-+
-+ pcie@8,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
-+ reg = <0x4000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 65>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <3>;
-+ clocks = <&gateclk 12>;
-+ status = "disabled";
-+ };
-+ pcie@9,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
-+ reg = <0x4800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 99>;
-+ marvell,pcie-port = <2>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 26>;
-+ status = "disabled";
-+ };
-+
-+ pcie@10,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
-+ reg = <0x5000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 103>;
-+ marvell,pcie-port = <3>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 27>;
-+ status = "disabled";
-+ };
-+};
---- a/drivers/pci/Kconfig
-+++ b/drivers/pci/Kconfig
-@@ -125,3 +125,5 @@ config PCI_IOAPIC
- config PCI_LABEL
- def_bool y if (DMI || ACPI)
- select NLS
-+
-+source "drivers/pci/host/Kconfig"
---- a/drivers/pci/Makefile
-+++ b/drivers/pci/Makefile
-@@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen
- obj-$(CONFIG_OF) += of.o
-
- ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
-+
-+# PCI host controller drivers
-+obj-y += host/
---- /dev/null
-+++ b/drivers/pci/host/Kconfig
-@@ -0,0 +1,8 @@
-+menu "PCI host controller drivers"
-+ depends on PCI
-+
-+config PCI_MVEBU
-+ bool "Marvell EBU PCIe controller"
-+ depends on ARCH_MVEBU
-+
-+endmenu
---- /dev/null
-+++ b/drivers/pci/host/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
---- /dev/null
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -0,0 +1,880 @@
-+/*
-+ * PCIe driver for Marvell Armada 370 and Armada XP SoCs
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/pci.h>
-+#include <linux/clk.h>
-+#include <linux/module.h>
-+#include <linux/mbus.h>
-+#include <linux/slab.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_address.h>
-+#include <linux/of_pci.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_platform.h>
-+
-+/*
-+ * PCIe unit register offsets.
-+ */
-+#define PCIE_DEV_ID_OFF 0x0000
-+#define PCIE_CMD_OFF 0x0004
-+#define PCIE_DEV_REV_OFF 0x0008
-+#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
-+#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
-+#define PCIE_HEADER_LOG_4_OFF 0x0128
-+#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
-+#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
-+#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
-+#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
-+#define PCIE_WIN5_CTRL_OFF 0x1880
-+#define PCIE_WIN5_BASE_OFF 0x1884
-+#define PCIE_WIN5_REMAP_OFF 0x188c
-+#define PCIE_CONF_ADDR_OFF 0x18f8
-+#define PCIE_CONF_ADDR_EN 0x80000000
-+#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
-+#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
-+#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
-+#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
-+#define PCIE_CONF_ADDR(bus, devfn, where) \
-+ (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
-+ PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
-+ PCIE_CONF_ADDR_EN)
-+#define PCIE_CONF_DATA_OFF 0x18fc
-+#define PCIE_MASK_OFF 0x1910
-+#define PCIE_MASK_ENABLE_INTS 0x0f000000
-+#define PCIE_CTRL_OFF 0x1a00
-+#define PCIE_CTRL_X1_MODE 0x0001
-+#define PCIE_STAT_OFF 0x1a04
-+#define PCIE_STAT_BUS 0xff00
-+#define PCIE_STAT_LINK_DOWN BIT(0)
-+#define PCIE_DEBUG_CTRL 0x1a60
-+#define PCIE_DEBUG_SOFT_RESET BIT(20)
-+
-+/*
-+ * This product ID is registered by Marvell, and used when the Marvell
-+ * SoC is not the root complex, but an endpoint on the PCIe bus. It is
-+ * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
-+ * bridge.
-+ */
-+#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
-+
-+/* PCI configuration space of a PCI-to-PCI bridge */
-+struct mvebu_sw_pci_bridge {
-+ u16 vendor;
-+ u16 device;
-+ u16 command;
-+ u16 status;
-+ u16 class;
-+ u8 interface;
-+ u8 revision;
-+ u8 bist;
-+ u8 header_type;
-+ u8 latency_timer;
-+ u8 cache_line_size;
-+ u32 bar[2];
-+ u8 primary_bus;
-+ u8 secondary_bus;
-+ u8 subordinate_bus;
-+ u8 secondary_latency_timer;
-+ u8 iobase;
-+ u8 iolimit;
-+ u16 secondary_status;
-+ u16 membase;
-+ u16 memlimit;
-+ u16 prefmembase;
-+ u16 prefmemlimit;
-+ u32 prefbaseupper;
-+ u32 preflimitupper;
-+ u16 iobaseupper;
-+ u16 iolimitupper;
-+ u8 cappointer;
-+ u8 reserved1;
-+ u16 reserved2;
-+ u32 romaddr;
-+ u8 intline;
-+ u8 intpin;
-+ u16 bridgectrl;
-+};
-+
-+struct mvebu_pcie_port;
-+
-+/* Structure representing all PCIe interfaces */
-+struct mvebu_pcie {
-+ struct platform_device *pdev;
-+ struct mvebu_pcie_port *ports;
-+ struct resource io;
-+ struct resource realio;
-+ struct resource mem;
-+ struct resource busn;
-+ int nports;
-+};
-+
-+/* Structure representing one PCIe interface */
-+struct mvebu_pcie_port {
-+ char *name;
-+ void __iomem *base;
-+ spinlock_t conf_lock;
-+ int haslink;
-+ u32 port;
-+ u32 lane;
-+ int devfn;
-+ struct clk *clk;
-+ struct mvebu_sw_pci_bridge bridge;
-+ struct device_node *dn;
-+ struct mvebu_pcie *pcie;
-+ phys_addr_t memwin_base;
-+ size_t memwin_size;
-+ phys_addr_t iowin_base;
-+ size_t iowin_size;
-+};
-+
-+static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
-+{
-+ return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
-+}
-+
-+static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
-+{
-+ u32 stat;
-+
-+ stat = readl(port->base + PCIE_STAT_OFF);
-+ stat &= ~PCIE_STAT_BUS;
-+ stat |= nr << 8;
-+ writel(stat, port->base + PCIE_STAT_OFF);
-+}
-+
-+/*
-+ * Setup PCIE BARs and Address Decode Wins:
-+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
-+ * WIN[0-3] -> DRAM bank[0-3]
-+ */
-+static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
-+{
-+ const struct mbus_dram_target_info *dram;
-+ u32 size;
-+ int i;
-+
-+ dram = mv_mbus_dram_info();
-+
-+ /* First, disable and clear BARs and windows. */
-+ for (i = 1; i < 3; i++) {
-+ writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
-+ writel(0, port->base + PCIE_BAR_LO_OFF(i));
-+ writel(0, port->base + PCIE_BAR_HI_OFF(i));
-+ }
-+
-+ for (i = 0; i < 5; i++) {
-+ writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
-+ writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
-+ writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
-+ }
-+
-+ writel(0, port->base + PCIE_WIN5_CTRL_OFF);
-+ writel(0, port->base + PCIE_WIN5_BASE_OFF);
-+ writel(0, port->base + PCIE_WIN5_REMAP_OFF);
-+
-+ /* Setup windows for DDR banks. Count total DDR size on the fly. */
-+ size = 0;
-+ for (i = 0; i < dram->num_cs; i++) {
-+ const struct mbus_dram_window *cs = dram->cs + i;
-+
-+ writel(cs->base & 0xffff0000,
-+ port->base + PCIE_WIN04_BASE_OFF(i));
-+ writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
-+ writel(((cs->size - 1) & 0xffff0000) |
-+ (cs->mbus_attr << 8) |
-+ (dram->mbus_dram_target_id << 4) | 1,
-+ port->base + PCIE_WIN04_CTRL_OFF(i));
-+
-+ size += cs->size;
-+ }
-+
-+ /* Round up 'size' to the nearest power of two. */
-+ if ((size & (size - 1)) != 0)
-+ size = 1 << fls(size);
-+
-+ /* Setup BAR[1] to all DRAM banks. */
-+ writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
-+ writel(0, port->base + PCIE_BAR_HI_OFF(1));
-+ writel(((size - 1) & 0xffff0000) | 1,
-+ port->base + PCIE_BAR_CTRL_OFF(1));
-+}
-+
-+static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
-+{
-+ u16 cmd;
-+ u32 mask;
-+
-+ /* Point PCIe unit MBUS decode windows to DRAM space. */
-+ mvebu_pcie_setup_wins(port);
-+
-+ /* Master + slave enable. */
-+ cmd = readw(port->base + PCIE_CMD_OFF);
-+ cmd |= PCI_COMMAND_IO;
-+ cmd |= PCI_COMMAND_MEMORY;
-+ cmd |= PCI_COMMAND_MASTER;
-+ writew(cmd, port->base + PCIE_CMD_OFF);
-+
-+ /* Enable interrupt lines A-D. */
-+ mask = readl(port->base + PCIE_MASK_OFF);
-+ mask |= PCIE_MASK_ENABLE_INTS;
-+ writel(mask, port->base + PCIE_MASK_OFF);
-+}
-+
-+static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
-+ struct pci_bus *bus,
-+ u32 devfn, int where, int size, u32 *val)
-+{
-+ writel(PCIE_CONF_ADDR(bus->number, devfn, where),
-+ port->base + PCIE_CONF_ADDR_OFF);
-+
-+ *val = readl(port->base + PCIE_CONF_DATA_OFF);
-+
-+ if (size == 1)
-+ *val = (*val >> (8 * (where & 3))) & 0xff;
-+ else if (size == 2)
-+ *val = (*val >> (8 * (where & 3))) & 0xffff;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
-+ struct pci_bus *bus,
-+ u32 devfn, int where, int size, u32 val)
-+{
-+ int ret = PCIBIOS_SUCCESSFUL;
-+
-+ writel(PCIE_CONF_ADDR(bus->number, devfn, where),
-+ port->base + PCIE_CONF_ADDR_OFF);
-+
-+ if (size == 4)
-+ writel(val, port->base + PCIE_CONF_DATA_OFF);
-+ else if (size == 2)
-+ writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
-+ else if (size == 1)
-+ writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
-+ else
-+ ret = PCIBIOS_BAD_REGISTER_NUMBER;
-+
-+ return ret;
-+}
-+
-+static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
-+{
-+ phys_addr_t iobase;
-+
-+ /* Are the new iobase/iolimit values invalid? */
-+ if (port->bridge.iolimit < port->bridge.iobase ||
-+ port->bridge.iolimitupper < port->bridge.iobaseupper) {
-+
-+ /* If a window was configured, remove it */
-+ if (port->iowin_base) {
-+ mvebu_mbus_del_window(port->iowin_base,
-+ port->iowin_size);
-+ port->iowin_base = 0;
-+ port->iowin_size = 0;
-+ }
-+
-+ return;
-+ }
-+
-+ /*
-+ * We read the PCI-to-PCI bridge emulated registers, and
-+ * calculate the base address and size of the address decoding
-+ * window to setup, according to the PCI-to-PCI bridge
-+ * specifications. iobase is the bus address, port->iowin_base
-+ * is the CPU address.
-+ */
-+ iobase = ((port->bridge.iobase & 0xF0) << 8) |
-+ (port->bridge.iobaseupper << 16);
-+ port->iowin_base = port->pcie->io.start + iobase;
-+ port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
-+ (port->bridge.iolimitupper << 16)) -
-+ iobase);
-+
-+ mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
-+ port->iowin_size,
-+ iobase,
-+ MVEBU_MBUS_PCI_IO);
-+
-+ pci_ioremap_io(iobase, port->iowin_base);
-+}
-+
-+static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
-+{
-+ /* Are the new membase/memlimit values invalid? */
-+ if (port->bridge.memlimit < port->bridge.membase) {
-+
-+ /* If a window was configured, remove it */
-+ if (port->memwin_base) {
-+ mvebu_mbus_del_window(port->memwin_base,
-+ port->memwin_size);
-+ port->memwin_base = 0;
-+ port->memwin_size = 0;
-+ }
-+
-+ return;
-+ }
-+
-+ /*
-+ * We read the PCI-to-PCI bridge emulated registers, and
-+ * calculate the base address and size of the address decoding
-+ * window to setup, according to the PCI-to-PCI bridge
-+ * specifications.
-+ */
-+ port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
-+ port->memwin_size =
-+ (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
-+ port->memwin_base;
-+
-+ mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
-+ port->memwin_size,
-+ MVEBU_MBUS_NO_REMAP,
-+ MVEBU_MBUS_PCI_MEM);
-+}
-+
-+/*
-+ * Initialize the configuration space of the PCI-to-PCI bridge
-+ * associated with the given PCIe interface.
-+ */
-+static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
-+{
-+ struct mvebu_sw_pci_bridge *bridge = &port->bridge;
-+
-+ memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
-+
-+ bridge->status = PCI_STATUS_CAP_LIST;
-+ bridge->class = PCI_CLASS_BRIDGE_PCI;
-+ bridge->vendor = PCI_VENDOR_ID_MARVELL;
-+ bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
-+ bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
-+ bridge->cache_line_size = 0x10;
-+
-+ /* We support 32 bits I/O addressing */
-+ bridge->iobase = PCI_IO_RANGE_TYPE_32;
-+ bridge->iolimit = PCI_IO_RANGE_TYPE_32;
-+}
-+
-+/*
-+ * Read the configuration space of the PCI-to-PCI bridge associated to
-+ * the given PCIe interface.
-+ */
-+static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
-+ unsigned int where, int size, u32 *value)
-+{
-+ struct mvebu_sw_pci_bridge *bridge = &port->bridge;
-+
-+ switch (where & ~3) {
-+ case PCI_VENDOR_ID:
-+ *value = bridge->device << 16 | bridge->vendor;
-+ break;
-+
-+ case PCI_COMMAND:
-+ *value = bridge->status << 16 | bridge->command;
-+ break;
-+
-+ case PCI_CLASS_REVISION:
-+ *value = bridge->class << 16 | bridge->interface << 8 |
-+ bridge->revision;
-+ break;
-+
-+ case PCI_CACHE_LINE_SIZE:
-+ *value = bridge->bist << 24 | bridge->header_type << 16 |
-+ bridge->latency_timer << 8 | bridge->cache_line_size;
-+ break;
-+
-+ case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
-+ *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
-+ break;
-+
-+ case PCI_PRIMARY_BUS:
-+ *value = (bridge->secondary_latency_timer << 24 |
-+ bridge->subordinate_bus << 16 |
-+ bridge->secondary_bus << 8 |
-+ bridge->primary_bus);
-+ break;
-+
-+ case PCI_IO_BASE:
-+ *value = (bridge->secondary_status << 16 |
-+ bridge->iolimit << 8 |
-+ bridge->iobase);
-+ break;
-+
-+ case PCI_MEMORY_BASE:
-+ *value = (bridge->memlimit << 16 | bridge->membase);
-+ break;
-+
-+ case PCI_PREF_MEMORY_BASE:
-+ *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
-+ break;
-+
-+ case PCI_PREF_BASE_UPPER32:
-+ *value = bridge->prefbaseupper;
-+ break;
-+
-+ case PCI_PREF_LIMIT_UPPER32:
-+ *value = bridge->preflimitupper;
-+ break;
-+
-+ case PCI_IO_BASE_UPPER16:
-+ *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
-+ break;
-+
-+ case PCI_ROM_ADDRESS1:
-+ *value = 0;
-+ break;
-+
-+ default:
-+ *value = 0xffffffff;
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ if (size == 2)
-+ *value = (*value >> (8 * (where & 3))) & 0xffff;
-+ else if (size == 1)
-+ *value = (*value >> (8 * (where & 3))) & 0xff;
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+/* Write to the PCI-to-PCI bridge configuration space */
-+static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
-+ unsigned int where, int size, u32 value)
-+{
-+ struct mvebu_sw_pci_bridge *bridge = &port->bridge;
-+ u32 mask, reg;
-+ int err;
-+
-+ if (size == 4)
-+ mask = 0x0;
-+ else if (size == 2)
-+ mask = ~(0xffff << ((where & 3) * 8));
-+ else if (size == 1)
-+ mask = ~(0xff << ((where & 3) * 8));
-+ else
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+
-+ err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
-+ if (err)
-+ return err;
-+
-+ value = (reg & mask) | value << ((where & 3) * 8);
-+
-+ switch (where & ~3) {
-+ case PCI_COMMAND:
-+ bridge->command = value & 0xffff;
-+ bridge->status = value >> 16;
-+ break;
-+
-+ case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
-+ bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
-+ break;
-+
-+ case PCI_IO_BASE:
-+ /*
-+ * We also keep bit 1 set, it is a read-only bit that
-+ * indicates we support 32 bits addressing for the
-+ * I/O
-+ */
-+ bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
-+ bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
-+ bridge->secondary_status = value >> 16;
-+ mvebu_pcie_handle_iobase_change(port);
-+ break;
-+
-+ case PCI_MEMORY_BASE:
-+ bridge->membase = value & 0xffff;
-+ bridge->memlimit = value >> 16;
-+ mvebu_pcie_handle_membase_change(port);
-+ break;
-+
-+ case PCI_PREF_MEMORY_BASE:
-+ bridge->prefmembase = value & 0xffff;
-+ bridge->prefmemlimit = value >> 16;
-+ break;
-+
-+ case PCI_PREF_BASE_UPPER32:
-+ bridge->prefbaseupper = value;
-+ break;
-+
-+ case PCI_PREF_LIMIT_UPPER32:
-+ bridge->preflimitupper = value;
-+ break;
-+
-+ case PCI_IO_BASE_UPPER16:
-+ bridge->iobaseupper = value & 0xffff;
-+ bridge->iolimitupper = value >> 16;
-+ mvebu_pcie_handle_iobase_change(port);
-+ break;
-+
-+ case PCI_PRIMARY_BUS:
-+ bridge->primary_bus = value & 0xff;
-+ bridge->secondary_bus = (value >> 8) & 0xff;
-+ bridge->subordinate_bus = (value >> 16) & 0xff;
-+ bridge->secondary_latency_timer = (value >> 24) & 0xff;
-+ mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
-+{
-+ return sys->private_data;
-+}
-+
-+static struct mvebu_pcie_port *
-+mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
-+ int devfn)
-+{
-+ int i;
-+
-+ for (i = 0; i < pcie->nports; i++) {
-+ struct mvebu_pcie_port *port = &pcie->ports[i];
-+ if (bus->number == 0 && port->devfn == devfn)
-+ return port;
-+ if (bus->number != 0 &&
-+ port->bridge.secondary_bus == bus->number)
-+ return port;
-+ }
-+
-+ return NULL;
-+}
-+
-+/* PCI configuration space write function */
-+static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
-+ int where, int size, u32 val)
-+{
-+ struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
-+ struct mvebu_pcie_port *port;
-+ unsigned long flags;
-+ int ret;
-+
-+ port = mvebu_pcie_find_port(pcie, bus, devfn);
-+ if (!port)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ /* Access the emulated PCI-to-PCI bridge */
-+ if (bus->number == 0)
-+ return mvebu_sw_pci_bridge_write(port, where, size, val);
-+
-+ if (!port->haslink || PCI_SLOT(devfn) != 0)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ /* Access the real PCIe interface */
-+ spin_lock_irqsave(&port->conf_lock, flags);
-+ ret = mvebu_pcie_hw_wr_conf(port, bus,
-+ PCI_DEVFN(1, PCI_FUNC(devfn)),
-+ where, size, val);
-+ spin_unlock_irqrestore(&port->conf_lock, flags);
-+
-+ return ret;
-+}
-+
-+/* PCI configuration space read function */
-+static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
-+ int size, u32 *val)
-+{
-+ struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
-+ struct mvebu_pcie_port *port;
-+ unsigned long flags;
-+ int ret;
-+
-+ port = mvebu_pcie_find_port(pcie, bus, devfn);
-+ if (!port) {
-+ *val = 0xffffffff;
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ }
-+
-+ /* Access the emulated PCI-to-PCI bridge */
-+ if (bus->number == 0)
-+ return mvebu_sw_pci_bridge_read(port, where, size, val);
-+
-+ if (!port->haslink || PCI_SLOT(devfn) != 0) {
-+ *val = 0xffffffff;
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ }
-+
-+ /* Access the real PCIe interface */
-+ spin_lock_irqsave(&port->conf_lock, flags);
-+ ret = mvebu_pcie_hw_rd_conf(port, bus,
-+ PCI_DEVFN(1, PCI_FUNC(devfn)),
-+ where, size, val);
-+ spin_unlock_irqrestore(&port->conf_lock, flags);
-+
-+ return ret;
-+}
-+
-+static struct pci_ops mvebu_pcie_ops = {
-+ .read = mvebu_pcie_rd_conf,
-+ .write = mvebu_pcie_wr_conf,
-+};
-+
-+static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
-+{
-+ struct mvebu_pcie *pcie = sys_to_pcie(sys);
-+ int i;
-+
-+ pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
-+ pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
-+ pci_add_resource(&sys->resources, &pcie->busn);
-+
-+ for (i = 0; i < pcie->nports; i++) {
-+ struct mvebu_pcie_port *port = &pcie->ports[i];
-+ mvebu_pcie_setup_hw(port);
-+ }
-+
-+ return 1;
-+}
-+
-+static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ struct of_irq oirq;
-+ int ret;
-+
-+ ret = of_irq_map_pci(dev, &oirq);
-+ if (ret)
-+ return ret;
-+
-+ return irq_create_of_mapping(oirq.controller, oirq.specifier,
-+ oirq.size);
-+}
-+
-+static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
-+{
-+ struct mvebu_pcie *pcie = sys_to_pcie(sys);
-+ struct pci_bus *bus;
-+
-+ bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
-+ &mvebu_pcie_ops, sys, &sys->resources);
-+ if (!bus)
-+ return NULL;
-+
-+ pci_scan_child_bus(bus);
-+
-+ return bus;
-+}
-+
-+resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
-+ const struct resource *res,
-+ resource_size_t start,
-+ resource_size_t size,
-+ resource_size_t align)
-+{
-+ if (dev->bus->number != 0)
-+ return start;
-+
-+ /*
-+ * On the PCI-to-PCI bridge side, the I/O windows must have at
-+ * least a 64 KB size and be aligned on their size, and the
-+ * memory windows must have at least a 1 MB size and be
-+ * aligned on their size
-+ */
-+ if (res->flags & IORESOURCE_IO)
-+ return round_up(start, max((resource_size_t)SZ_64K, size));
-+ else if (res->flags & IORESOURCE_MEM)
-+ return round_up(start, max((resource_size_t)SZ_1M, size));
-+ else
-+ return start;
-+}
-+
-+static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie)
-+{
-+ struct hw_pci hw;
-+
-+ memset(&hw, 0, sizeof(hw));
-+
-+ hw.nr_controllers = 1;
-+ hw.private_data = (void **)&pcie;
-+ hw.setup = mvebu_pcie_setup;
-+ hw.scan = mvebu_pcie_scan_bus;
-+ hw.map_irq = mvebu_pcie_map_irq;
-+ hw.ops = &mvebu_pcie_ops;
-+ hw.align_resource = mvebu_pcie_align_resource;
-+
-+ pci_common_init(&hw);
-+}
-+
-+/*
-+ * Looks up the list of register addresses encoded into the reg =
-+ * <...> property for one that matches the given port/lane. Once
-+ * found, maps it.
-+ */
-+static void __iomem * __init
-+mvebu_pcie_map_registers(struct platform_device *pdev,
-+ struct device_node *np,
-+ struct mvebu_pcie_port *port)
-+{
-+ struct resource regs;
-+ int ret = 0;
-+
-+ ret = of_address_to_resource(np, 0, ®s);
-+ if (ret)
-+ return NULL;
-+
-+ return devm_request_and_ioremap(&pdev->dev, ®s);
-+}
-+
-+static int __init mvebu_pcie_probe(struct platform_device *pdev)
-+{
-+ struct mvebu_pcie *pcie;
-+ struct device_node *np = pdev->dev.of_node;
-+ struct of_pci_range range;
-+ struct of_pci_range_parser parser;
-+ struct device_node *child;
-+ int i, ret;
-+
-+ pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
-+ GFP_KERNEL);
-+ if (!pcie)
-+ return -ENOMEM;
-+
-+ pcie->pdev = pdev;
-+
-+ if (of_pci_range_parser_init(&parser, np))
-+ return -EINVAL;
-+
-+ /* Get the I/O and memory ranges from DT */
-+ for_each_of_pci_range(&parser, &range) {
-+ unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
-+ if (restype == IORESOURCE_IO) {
-+ of_pci_range_to_resource(&range, np, &pcie->io);
-+ of_pci_range_to_resource(&range, np, &pcie->realio);
-+ pcie->io.name = "I/O";
-+ pcie->realio.start = max_t(resource_size_t,
-+ PCIBIOS_MIN_IO,
-+ range.pci_addr);
-+ pcie->realio.end = min_t(resource_size_t,
-+ IO_SPACE_LIMIT,
-+ range.pci_addr + range.size);
-+ }
-+ if (restype == IORESOURCE_MEM) {
-+ of_pci_range_to_resource(&range, np, &pcie->mem);
-+ pcie->mem.name = "MEM";
-+ }
-+ }
-+
-+ /* Get the bus range */
-+ ret = of_pci_parse_bus_range(np, &pcie->busn);
-+ if (ret) {
-+ dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ for_each_child_of_node(pdev->dev.of_node, child) {
-+ if (!of_device_is_available(child))
-+ continue;
-+ pcie->nports++;
-+ }
-+
-+ pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
-+ sizeof(struct mvebu_pcie_port),
-+ GFP_KERNEL);
-+ if (!pcie->ports)
-+ return -ENOMEM;
-+
-+ i = 0;
-+ for_each_child_of_node(pdev->dev.of_node, child) {
-+ struct mvebu_pcie_port *port = &pcie->ports[i];
-+
-+ if (!of_device_is_available(child))
-+ continue;
-+
-+ port->pcie = pcie;
-+
-+ if (of_property_read_u32(child, "marvell,pcie-port",
-+ &port->port)) {
-+ dev_warn(&pdev->dev,
-+ "ignoring PCIe DT node, missing pcie-port property\n");
-+ continue;
-+ }
-+
-+ if (of_property_read_u32(child, "marvell,pcie-lane",
-+ &port->lane))
-+ port->lane = 0;
-+
-+ port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
-+ port->port, port->lane);
-+
-+ port->devfn = of_pci_get_devfn(child);
-+ if (port->devfn < 0)
-+ continue;
-+
-+ port->base = mvebu_pcie_map_registers(pdev, child, port);
-+ if (!port->base) {
-+ dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
-+ port->port, port->lane);
-+ continue;
-+ }
-+
-+ if (mvebu_pcie_link_up(port)) {
-+ port->haslink = 1;
-+ dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
-+ port->port, port->lane);
-+ } else {
-+ port->haslink = 0;
-+ dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
-+ port->port, port->lane);
-+ }
-+
-+ port->clk = of_clk_get_by_name(child, NULL);
-+ if (!port->clk) {
-+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
-+ port->port, port->lane);
-+ iounmap(port->base);
-+ port->haslink = 0;
-+ continue;
-+ }
-+
-+ port->dn = child;
-+
-+ clk_prepare_enable(port->clk);
-+ spin_lock_init(&port->conf_lock);
-+
-+ mvebu_sw_pci_bridge_init(port);
-+
-+ i++;
-+ }
-+
-+ mvebu_pcie_enable(pcie);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mvebu_pcie_of_match_table[] = {
-+ { .compatible = "marvell,armada-xp-pcie", },
-+ { .compatible = "marvell,armada-370-pcie", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
-+
-+static struct platform_driver mvebu_pcie_driver = {
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "mvebu-pcie",
-+ .of_match_table =
-+ of_match_ptr(mvebu_pcie_of_match_table),
-+ },
-+};
-+
-+static int __init mvebu_pcie_init(void)
-+{
-+ return platform_driver_probe(&mvebu_pcie_driver,
-+ mvebu_pcie_probe);
-+}
-+
-+subsys_initcall(mvebu_pcie_init);
-+
-+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
-+MODULE_DESCRIPTION("Marvell EBU PCIe driver");
-+MODULE_LICENSE("GPLv2");
+++ /dev/null
-From 430d545623552ddc6b68785032cc9129d0a00b43 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 7 Dec 2012 20:56:52 +0100
-Subject: [PATCH 010/203] arm: mvebu: PCIe support is now available on mvebu
-
-Now that the PCIe driver for mvebu has been integrated and all its
-relevant dependencies, we can mark the ARCH_MVEBU platform has
-MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
----
- arch/arm/mach-mvebu/Kconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/mach-mvebu/Kconfig
-+++ b/arch/arm/mach-mvebu/Kconfig
-@@ -16,6 +16,8 @@ config ARCH_MVEBU
- select MVEBU_MBUS
- select ZONE_DMA if ARM_LPAE
- select ARCH_REQUIRE_GPIOLIB
-+ select MIGHT_HAVE_PCI
-+ select PCI_QUIRKS if PCI
-
- if ARCH_MVEBU
-
+++ /dev/null
-From c3da1bb20af37c09a07756d54420470788f131c7 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 7 Dec 2012 22:49:57 +0100
-Subject: [PATCH 011/203] arm: mvebu: update defconfig with PCI and USB support
-
-Now that we have the necessary drivers and Device Tree informations to
-support PCIe on Armada 370 and Armada XP, enable the CONFIG_PCI
-option.
-
-Also, since the Armada 370 Mirabox has a built-in USB XHCI controller
-connected on the PCIe bus, enable the corresponding options as well.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
----
- arch/arm/configs/mvebu_defconfig | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/arch/arm/configs/mvebu_defconfig
-+++ b/arch/arm/configs/mvebu_defconfig
-@@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y
- CONFIG_MACH_ARMADA_XP=y
- # CONFIG_CACHE_L2X0 is not set
- # CONFIG_SWP_EMULATE is not set
-+CONFIG_PCI=y
-+CONFIG_PCI_MVEBU=y
- CONFIG_SMP=y
- CONFIG_AEABI=y
- CONFIG_HIGHMEM=y
-@@ -61,6 +63,7 @@ CONFIG_USB=y
- CONFIG_USB_EHCI_HCD=y
- CONFIG_USB_EHCI_ROOT_HUB_TT=y
- CONFIG_USB_STORAGE=y
-+CONFIG_USB_XHCI_HCD=y
- CONFIG_MMC=y
- CONFIG_MMC_MVSDIO=y
- CONFIG_NEW_LEDS=y
+++ /dev/null
-From f865fd0e1c10bb044d56037eaa6ac4a4a122c62a Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Tue, 21 May 2013 12:33:28 +0200
-Subject: [PATCH 012/203] arm: mvebu: mark functions of armada-370-xp.c as
- static
-
-All the functions in armada-370-xp.c are called from the
-DT_MACHINE_START function pointers, so there is no need for them to be
-visible outside of this file, and we therefore mark them as static.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/mach-mvebu/armada-370-xp.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm/mach-mvebu/armada-370-xp.c
-+++ b/arch/arm/mach-mvebu/armada-370-xp.c
-@@ -38,18 +38,18 @@ static struct map_desc armada_370_xp_io_
- },
- };
-
--void __init armada_370_xp_map_io(void)
-+static void __init armada_370_xp_map_io(void)
- {
- iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
- }
-
--void __init armada_370_xp_timer_and_clk_init(void)
-+static void __init armada_370_xp_timer_and_clk_init(void)
- {
- mvebu_clocks_init();
- armada_370_xp_timer_init();
- }
-
--void __init armada_370_xp_init_early(void)
-+static void __init armada_370_xp_init_early(void)
- {
- char *mbus_soc_name;
-
+++ /dev/null
-From 8b417cc752ac4158dcfcf02beafce80b90fd827d Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 23 Apr 2013 16:21:26 -0300
-Subject: [PATCH 013/203] drivers: memory: Introduce Marvell EBU Device Bus
- driver
-
-Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and
-Discovery (mv78xx0) supports a Device Bus controller to access several
-kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA).
-
-This commit adds a driver to handle this controller. So far only
-Armada 370, Armada XP and Discovery SoCs are supported.
-
-The driver must be registered through a device tree node;
-as explained in the binding document.
-
-For each child node in the device tree, this driver will:
- * set timing parameters
- * register a child device
- * setup an address decoding window, using the mbus driver
-
-Keep in mind the address decoding window setup is only a temporary hack.
-This code will be removed from this devbus driver as soon as a proper device
-tree binding for the mbus driver is added.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Acked-by: Jason Cooper <jason@lakedaemon.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../bindings/memory-controllers/mvebu-devbus.txt | 156 ++++++++++
- drivers/memory/Kconfig | 10 +
- drivers/memory/Makefile | 1 +
- drivers/memory/mvebu-devbus.c | 340 +++++++++++++++++++++
- 4 files changed, 507 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
- create mode 100644 drivers/memory/mvebu-devbus.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
-@@ -0,0 +1,156 @@
-+Device tree bindings for MVEBU Device Bus controllers
-+
-+The Device Bus controller available in some Marvell's SoC allows to control
-+different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
-+The actual devices are instantiated from the child nodes of a Device Bus node.
-+
-+Required properties:
-+
-+ - compatible: Currently only Armada 370/XP SoC are supported,
-+ with this compatible string:
-+
-+ marvell,mvebu-devbus
-+
-+ - reg: A resource specifier for the register space.
-+ This is the base address of a chip select within
-+ the controller's register space.
-+ (see the example below)
-+
-+ - #address-cells: Must be set to 1
-+ - #size-cells: Must be set to 1
-+ - ranges: Must be set up to reflect the memory layout with four
-+ integer values for each chip-select line in use:
-+ 0 <physical address of mapping> <size>
-+
-+Mandatory timing properties for child nodes:
-+
-+Read parameters:
-+
-+ - devbus,turn-off-ps: Defines the time during which the controller does not
-+ drive the AD bus after the completion of a device read.
-+ This prevents contentions on the Device Bus after a read
-+ cycle from a slow device.
-+
-+ - devbus,bus-width: Defines the bus width (e.g. <16>)
-+
-+ - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
-+ to read data sample. This parameter is useful for
-+ synchronous pipelined devices, where the address
-+ precedes the read data by one or two cycles.
-+
-+ - devbus,acc-first-ps: Defines the time delay from the negation of
-+ ALE[0] to the cycle that the first read data is sampled
-+ by the controller.
-+
-+ - devbus,acc-next-ps: Defines the time delay between the cycle that
-+ samples data N and the cycle that samples data N+1
-+ (in burst accesses).
-+
-+ - devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
-+ DEV_OEn assertion. If set to 0 (default),
-+ DEV_OEn and DEV_CSn are asserted at the same cycle.
-+ This parameter has no affect on <acc-first-ps> parameter
-+ (no affect on first data sample). Set <rd-setup-ps>
-+ to a value smaller than <acc-first-ps>.
-+
-+ - devbus,rd-hold-ps: Defines the time between the last data sample to the
-+ de-assertion of DEV_CSn. If set to 0 (default),
-+ DEV_OEn and DEV_CSn are de-asserted at the same cycle
-+ (the cycle of the last data sample).
-+ This parameter has no affect on DEV_OEn de-assertion.
-+ DEV_OEn is always de-asserted the next cycle after
-+ last data sampled. Also this parameter has no
-+ affect on <turn-off-ps> parameter.
-+ Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
-+
-+Write parameters:
-+
-+ - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
-+ to the DEV_WEn assertion.
-+
-+ - devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
-+ A[2:0] and Data are kept valid as long as DEV_WEn
-+ is active. This parameter defines the setup time of
-+ address and data to DEV_WEn rise.
-+
-+ - devbus,wr-high-ps: Defines the time during which DEV_WEn is kept
-+ inactive (high) between data beats of a burst write.
-+ DEV_A[2:0] and Data are kept valid (do not toggle) for
-+ <wr-high-ps> - <tick> ps.
-+ This parameter defines the hold time of address and
-+ data after DEV_WEn rise.
-+
-+ - devbus,sync-enable: Synchronous device enable.
-+ 1: True
-+ 0: False
-+
-+An example for an Armada XP GP board, with a 16 MiB NOR device as child
-+is showed below. Note that the Device Bus driver is in charge of allocating
-+the mbus address decoding window for each of its child devices.
-+The window is created using the chip select specified in the child
-+device node together with the base address and size specified in the ranges
-+property. For instance, in the example below the allocated decoding window
-+will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
-+for chip select 0 (a.k.a DEV_BOOTCS).
-+
-+This address window handling is done in this mvebu-devbus only as a temporary
-+solution. It will be removed when the support for mbus device tree binding is
-+added.
-+
-+The reg property implicitly specifies the chip select as this:
-+
-+ 0x10400: DEV_BOOTCS
-+ 0x10408: DEV_CS0
-+ 0x10410: DEV_CS1
-+ 0x10418: DEV_CS2
-+ 0x10420: DEV_CS3
-+
-+Example:
-+
-+ devbus-bootcs@d0010400 {
-+ status = "okay";
-+ ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ /* Device Bus parameters are required */
-+
-+ /* Read parameters */
-+ devbus,bus-width = <8>;
-+ devbus,turn-off-ps = <60000>;
-+ devbus,badr-skew-ps = <0>;
-+ devbus,acc-first-ps = <124000>;
-+ devbus,acc-next-ps = <248000>;
-+ devbus,rd-setup-ps = <0>;
-+ devbus,rd-hold-ps = <0>;
-+
-+ /* Write parameters */
-+ devbus,sync-enable = <0>;
-+ devbus,wr-high-ps = <60000>;
-+ devbus,wr-low-ps = <60000>;
-+ devbus,ale-wr-ps = <60000>;
-+
-+ flash@0 {
-+ compatible = "cfi-flash";
-+
-+ /* 16 MiB */
-+ reg = <0 0x1000000>;
-+ bank-width = <2>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ /*
-+ * We split the 16 MiB in two partitions,
-+ * just as an example.
-+ */
-+ partition@0 {
-+ label = "First";
-+ reg = <0 0x800000>;
-+ };
-+
-+ partition@800000 {
-+ label = "Second";
-+ reg = <0x800000 0x800000>;
-+ };
-+ };
-+ };
---- a/drivers/memory/Kconfig
-+++ b/drivers/memory/Kconfig
-@@ -20,6 +20,16 @@ config TI_EMIF
- parameters and other settings during frequency, voltage and
- temperature changes
-
-+config MVEBU_DEVBUS
-+ bool "Marvell EBU Device Bus Controller"
-+ default y
-+ depends on PLAT_ORION && OF
-+ help
-+ This driver is for the Device Bus controller available in some
-+ Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
-+ Armada 370 and Armada XP. This controller allows to handle flash
-+ devices such as NOR, NAND, SRAM, and FPGA.
-+
- config TEGRA20_MC
- bool "Tegra20 Memory Controller(MC) driver"
- default y
---- a/drivers/memory/Makefile
-+++ b/drivers/memory/Makefile
-@@ -6,5 +6,6 @@ ifeq ($(CONFIG_DDR),y)
- obj-$(CONFIG_OF) += of_memory.o
- endif
- obj-$(CONFIG_TI_EMIF) += emif.o
-+obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
- obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o
- obj-$(CONFIG_TEGRA30_MC) += tegra30-mc.o
---- /dev/null
-+++ b/drivers/memory/mvebu-devbus.c
-@@ -0,0 +1,340 @@
-+/*
-+ * Marvell EBU SoC Device Bus Controller
-+ * (memory controller for NOR/NAND/SRAM/FPGA devices)
-+ *
-+ * Copyright (C) 2013 Marvell
-+ *
-+ * This program is free software: you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation version 2 of the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/clk.h>
-+#include <linux/mbus.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_address.h>
-+#include <linux/platform_device.h>
-+
-+/* Register definitions */
-+#define DEV_WIDTH_BIT 30
-+#define BADR_SKEW_BIT 28
-+#define RD_HOLD_BIT 23
-+#define ACC_NEXT_BIT 17
-+#define RD_SETUP_BIT 12
-+#define ACC_FIRST_BIT 6
-+
-+#define SYNC_ENABLE_BIT 24
-+#define WR_HIGH_BIT 16
-+#define WR_LOW_BIT 8
-+
-+#define READ_PARAM_OFFSET 0x0
-+#define WRITE_PARAM_OFFSET 0x4
-+
-+static const char * const devbus_wins[] = {
-+ "devbus-boot",
-+ "devbus-cs0",
-+ "devbus-cs1",
-+ "devbus-cs2",
-+ "devbus-cs3",
-+};
-+
-+struct devbus_read_params {
-+ u32 bus_width;
-+ u32 badr_skew;
-+ u32 turn_off;
-+ u32 acc_first;
-+ u32 acc_next;
-+ u32 rd_setup;
-+ u32 rd_hold;
-+};
-+
-+struct devbus_write_params {
-+ u32 sync_enable;
-+ u32 wr_high;
-+ u32 wr_low;
-+ u32 ale_wr;
-+};
-+
-+struct devbus {
-+ struct device *dev;
-+ void __iomem *base;
-+ unsigned long tick_ps;
-+};
-+
-+static int get_timing_param_ps(struct devbus *devbus,
-+ struct device_node *node,
-+ const char *name,
-+ u32 *ticks)
-+{
-+ u32 time_ps;
-+ int err;
-+
-+ err = of_property_read_u32(node, name, &time_ps);
-+ if (err < 0) {
-+ dev_err(devbus->dev, "%s has no '%s' property\n",
-+ name, node->full_name);
-+ return err;
-+ }
-+
-+ *ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps;
-+
-+ dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n",
-+ name, time_ps, *ticks);
-+ return 0;
-+}
-+
-+static int devbus_set_timing_params(struct devbus *devbus,
-+ struct device_node *node)
-+{
-+ struct devbus_read_params r;
-+ struct devbus_write_params w;
-+ u32 value;
-+ int err;
-+
-+ dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
-+ devbus->tick_ps);
-+
-+ /* Get read timings */
-+ err = of_property_read_u32(node, "devbus,bus-width", &r.bus_width);
-+ if (err < 0) {
-+ dev_err(devbus->dev,
-+ "%s has no 'devbus,bus-width' property\n",
-+ node->full_name);
-+ return err;
-+ }
-+ /* Convert bit width to byte width */
-+ r.bus_width /= 8;
-+
-+ err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
-+ &r.badr_skew);
-+ if (err < 0)
-+ return err;
-+
-+ err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
-+ &r.turn_off);
-+ if (err < 0)
-+ return err;
-+
-+ err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
-+ &r.acc_first);
-+ if (err < 0)
-+ return err;
-+
-+ err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
-+ &r.acc_next);
-+ if (err < 0)
-+ return err;
-+
-+ err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
-+ &r.rd_setup);
-+ if (err < 0)
-+ return err;
-+
-+ err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
-+ &r.rd_hold);
-+ if (err < 0)
-+ return err;
-+
-+ /* Get write timings */
-+ err = of_property_read_u32(node, "devbus,sync-enable",
-+ &w.sync_enable);
-+ if (err < 0) {
-+ dev_err(devbus->dev,
-+ "%s has no 'devbus,sync-enable' property\n",
-+ node->full_name);
-+ return err;
-+ }
-+
-+ err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
-+ &w.ale_wr);
-+ if (err < 0)
-+ return err;
-+
-+ err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
-+ &w.wr_low);
-+ if (err < 0)
-+ return err;
-+
-+ err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
-+ &w.wr_high);
-+ if (err < 0)
-+ return err;
-+
-+ /* Set read timings */
-+ value = r.bus_width << DEV_WIDTH_BIT |
-+ r.badr_skew << BADR_SKEW_BIT |
-+ r.rd_hold << RD_HOLD_BIT |
-+ r.acc_next << ACC_NEXT_BIT |
-+ r.rd_setup << RD_SETUP_BIT |
-+ r.acc_first << ACC_FIRST_BIT |
-+ r.turn_off;
-+
-+ dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
-+ devbus->base + READ_PARAM_OFFSET,
-+ value);
-+
-+ writel(value, devbus->base + READ_PARAM_OFFSET);
-+
-+ /* Set write timings */
-+ value = w.sync_enable << SYNC_ENABLE_BIT |
-+ w.wr_low << WR_LOW_BIT |
-+ w.wr_high << WR_HIGH_BIT |
-+ w.ale_wr;
-+
-+ dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
-+ devbus->base + WRITE_PARAM_OFFSET,
-+ value);
-+
-+ writel(value, devbus->base + WRITE_PARAM_OFFSET);
-+
-+ return 0;
-+}
-+
-+static int mvebu_devbus_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct device_node *node = pdev->dev.of_node;
-+ struct device_node *parent;
-+ struct devbus *devbus;
-+ struct resource *res;
-+ struct clk *clk;
-+ unsigned long rate;
-+ const __be32 *ranges;
-+ int err, cs;
-+ int addr_cells, p_addr_cells, size_cells;
-+ int ranges_len, tuple_len;
-+ u32 base, size;
-+
-+ devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
-+ if (!devbus)
-+ return -ENOMEM;
-+
-+ devbus->dev = dev;
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ devbus->base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(devbus->base))
-+ return PTR_ERR(devbus->base);
-+
-+ clk = devm_clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(clk))
-+ return PTR_ERR(clk);
-+ clk_prepare_enable(clk);
-+
-+ /*
-+ * Obtain clock period in picoseconds,
-+ * we need this in order to convert timing
-+ * parameters from cycles to picoseconds.
-+ */
-+ rate = clk_get_rate(clk) / 1000;
-+ devbus->tick_ps = 1000000000 / rate;
-+
-+ /* Read the device tree node and set the new timing parameters */
-+ err = devbus_set_timing_params(devbus, node);
-+ if (err < 0)
-+ return err;
-+
-+ /*
-+ * Allocate an address window for this device.
-+ * If the device probing fails, then we won't be able to
-+ * remove the allocated address decoding window.
-+ *
-+ * FIXME: This is only a temporary hack! We need to do this here
-+ * because we still don't have device tree bindings for mbus.
-+ * Once that support is added, we will declare these address windows
-+ * statically in the device tree, and remove the window configuration
-+ * from here.
-+ */
-+
-+ /*
-+ * Get the CS to choose the window string.
-+ * This is a bit hacky, but it will be removed once the
-+ * address windows are declared in the device tree.
-+ */
-+ cs = (((unsigned long)devbus->base) % 0x400) / 8;
-+
-+ /*
-+ * Parse 'ranges' property to obtain a (base,size) window tuple.
-+ * This will be removed once the address windows
-+ * are declared in the device tree.
-+ */
-+ parent = of_get_parent(node);
-+ if (!parent)
-+ return -EINVAL;
-+
-+ p_addr_cells = of_n_addr_cells(parent);
-+ of_node_put(parent);
-+
-+ addr_cells = of_n_addr_cells(node);
-+ size_cells = of_n_size_cells(node);
-+ tuple_len = (p_addr_cells + addr_cells + size_cells) * sizeof(__be32);
-+
-+ ranges = of_get_property(node, "ranges", &ranges_len);
-+ if (ranges == NULL || ranges_len != tuple_len)
-+ return -EINVAL;
-+
-+ base = of_translate_address(node, ranges + addr_cells);
-+ if (base == OF_BAD_ADDR)
-+ return -EINVAL;
-+ size = of_read_number(ranges + addr_cells + p_addr_cells, size_cells);
-+
-+ /*
-+ * Create an mbus address windows.
-+ * FIXME: Remove this, together with the above code, once the
-+ * address windows are declared in the device tree.
-+ */
-+ err = mvebu_mbus_add_window(devbus_wins[cs], base, size);
-+ if (err < 0)
-+ return err;
-+
-+ /*
-+ * We need to create a child device explicitly from here to
-+ * guarantee that the child will be probed after the timing
-+ * parameters for the bus are written.
-+ */
-+ err = of_platform_populate(node, NULL, NULL, dev);
-+ if (err < 0) {
-+ mvebu_mbus_del_window(base, size);
-+ return err;
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mvebu_devbus_of_match[] = {
-+ { .compatible = "marvell,mvebu-devbus" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
-+
-+static struct platform_driver mvebu_devbus_driver = {
-+ .probe = mvebu_devbus_probe,
-+ .driver = {
-+ .name = "mvebu-devbus",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mvebu_devbus_of_match,
-+ },
-+};
-+
-+static int __init mvebu_devbus_init(void)
-+{
-+ return platform_driver_register(&mvebu_devbus_driver);
-+}
-+module_init(mvebu_devbus_init);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
-+MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller");
+++ /dev/null
-From 348fc73a301b88ec3f2da8c1f02858c75e79455e Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Tue, 21 May 2013 19:53:09 +0200
-Subject: [PATCH 014/203] arm: mvebu: enable two USB interfaces on the Armada
- XP GP board
-
-The Armada XP GP board has two USB slots: one on the front side and
-one on the back side. This commit enables the two USB host controllers
-that correspond to those wo USB slots.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-xp-gp.dts | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm/boot/dts/armada-xp-gp.dts
-+++ b/arch/arm/boot/dts/armada-xp-gp.dts
-@@ -105,6 +105,16 @@
- phy-mode = "rgmii-id";
- };
-
-+ /* Front-side USB slot */
-+ usb@50000 {
-+ status = "okay";
-+ };
-+
-+ /* Back-side USB slot */
-+ usb@51000 {
-+ status = "okay";
-+ };
-+
- spi0: spi@10600 {
- status = "okay";
-
+++ /dev/null
-From 34361044442206dd7d10ff3309f8e0713e0fd856 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 23 May 2013 16:32:51 +0200
-Subject: [PATCH 015/203] pci: mvebu: no longer fake the slot location of
- downstream devices
-
-By default, the Marvell hardware, for each PCIe interface, exhibits
-the following devices:
-
- * On slot 0, a "Marvell Memory controller", identical on all PCIe
- interfaces, and which isn't useful when the Marvell SoC is the PCIe
- root complex (i.e, the normal case when we run Linux on the Marvell
- SoC).
-
- * On slot 1, the real PCIe card connected into the PCIe slot of the
- board.
-
-So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
-emulation is that when the Linux PCI core was trying to access the
-device in slot 0, we were in fact forwarding the configuration
-transaction to the device in slot 1. For all other slots, we were
-telling the Linux PCI core that there was no device connected.
-
-However, new versions of bootloaders from Marvell change the default
-PCIe configuration, and make the real device appear in slot 0, and the
-"Marvell Memory controller" in slot 1.
-
-Therefore, this commit modifies the Marvell PCIe driver to adjust the
-PCIe hardware configuration to make sure that this behavior (real
-device in slot 0, "Marvell Memory controller" in slot 1) is the one
-we'll see regardless of what the bootloader has done. It allows to
-remove the little hack that was forwarding configuration transactions
-on slot 0 to slot 1, which is nice.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- drivers/pci/host/pci-mvebu.c | 19 +++++++++++++++----
- 1 file changed, 15 insertions(+), 4 deletions(-)
-
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -51,6 +51,7 @@
- #define PCIE_CTRL_X1_MODE 0x0001
- #define PCIE_STAT_OFF 0x1a04
- #define PCIE_STAT_BUS 0xff00
-+#define PCIE_STAT_DEV 0x1f0000
- #define PCIE_STAT_LINK_DOWN BIT(0)
- #define PCIE_DEBUG_CTRL 0x1a60
- #define PCIE_DEBUG_SOFT_RESET BIT(20)
-@@ -148,6 +149,16 @@ static void mvebu_pcie_set_local_bus_nr(
- writel(stat, port->base + PCIE_STAT_OFF);
- }
-
-+static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
-+{
-+ u32 stat;
-+
-+ stat = readl(port->base + PCIE_STAT_OFF);
-+ stat &= ~PCIE_STAT_DEV;
-+ stat |= nr << 16;
-+ writel(stat, port->base + PCIE_STAT_OFF);
-+}
-+
- /*
- * Setup PCIE BARs and Address Decode Wins:
- * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
-@@ -572,8 +583,7 @@ static int mvebu_pcie_wr_conf(struct pci
-
- /* Access the real PCIe interface */
- spin_lock_irqsave(&port->conf_lock, flags);
-- ret = mvebu_pcie_hw_wr_conf(port, bus,
-- PCI_DEVFN(1, PCI_FUNC(devfn)),
-+ ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
- where, size, val);
- spin_unlock_irqrestore(&port->conf_lock, flags);
-
-@@ -606,8 +616,7 @@ static int mvebu_pcie_rd_conf(struct pci
-
- /* Access the real PCIe interface */
- spin_lock_irqsave(&port->conf_lock, flags);
-- ret = mvebu_pcie_hw_rd_conf(port, bus,
-- PCI_DEVFN(1, PCI_FUNC(devfn)),
-+ ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
- where, size, val);
- spin_unlock_irqrestore(&port->conf_lock, flags);
-
-@@ -817,6 +826,8 @@ static int __init mvebu_pcie_probe(struc
- continue;
- }
-
-+ mvebu_pcie_set_local_dev_nr(port, 1);
-+
- if (mvebu_pcie_link_up(port)) {
- port->haslink = 1;
- dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
+++ /dev/null
-From 10f725e3a9e73aab2e5601206c88cf9cbc599243 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 23 May 2013 16:32:52 +0200
-Subject: [PATCH 016/203] pci: mvebu: allow the enumeration of devices beyond
- physical bridges
-
-Until now, the Marvell PCIe driver was only allowing the enumeration
-of the devices in the secondary bus of the emulated PCI-to-PCI
-bridge. This works fine when a PCIe device is directly connected into
-a PCIe slot of the Marvell board.
-
-However, when the device connected in the PCIe slot is a physical PCIe
-bridge, beyond which a real PCIe device is connected, it no longer
-worked, as the driver was preventing the Linux PCI core from seeing
-such devices.
-
-This commit fixes that by ensuring that configuration transactions on
-subordinate busses are properly forwarded on the right PCIe interface.
-
-Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
-the emulated PCI-to-PCI bridge is properly detected, with the
-following layout:
-
--[0000:00]-+-01.0-[01]----00.0
- +-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
- | +-05.0-[05]--
- | +-07.0-[06]--
- | \-09.0-[07]----00.0
- \-0a.0-[08]----00.0
-
-Where the PCIe interface that sits beyond the emulated PCI-to-PCI
-bridge at 09.0 allows to access the secondary bus 02, on which there
-is a PCIe bridge that allows to access the 3 to 7 busses, that are
-subordinates to this bridge. And on one of this bus (bus 7), there is
-one real PCIe device connected.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- drivers/pci/host/pci-mvebu.c | 31 ++++++++++++++++++++++++++++---
- 1 file changed, 28 insertions(+), 3 deletions(-)
-
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -554,7 +554,8 @@ mvebu_pcie_find_port(struct mvebu_pcie *
- if (bus->number == 0 && port->devfn == devfn)
- return port;
- if (bus->number != 0 &&
-- port->bridge.secondary_bus == bus->number)
-+ bus->number >= port->bridge.secondary_bus &&
-+ bus->number <= port->bridge.subordinate_bus)
- return port;
- }
-
-@@ -578,7 +579,18 @@ static int mvebu_pcie_wr_conf(struct pci
- if (bus->number == 0)
- return mvebu_sw_pci_bridge_write(port, where, size, val);
-
-- if (!port->haslink || PCI_SLOT(devfn) != 0)
-+ if (!port->haslink)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ /*
-+ * On the secondary bus, we don't want to expose any other
-+ * device than the device physically connected in the PCIe
-+ * slot, visible in slot 0. In slot 1, there's a special
-+ * Marvell device that only makes sense when the Armada is
-+ * used as a PCIe endpoint.
-+ */
-+ if (bus->number == port->bridge.secondary_bus &&
-+ PCI_SLOT(devfn) != 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- /* Access the real PCIe interface */
-@@ -609,7 +621,20 @@ static int mvebu_pcie_rd_conf(struct pci
- if (bus->number == 0)
- return mvebu_sw_pci_bridge_read(port, where, size, val);
-
-- if (!port->haslink || PCI_SLOT(devfn) != 0) {
-+ if (!port->haslink) {
-+ *val = 0xffffffff;
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ }
-+
-+ /*
-+ * On the secondary bus, we don't want to expose any other
-+ * device than the device physically connected in the PCIe
-+ * slot, visible in slot 0. In slot 1, there's a special
-+ * Marvell device that only makes sense when the Armada is
-+ * used as a PCIe endpoint.
-+ */
-+ if (bus->number == port->bridge.secondary_bus &&
-+ PCI_SLOT(devfn) != 0) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
+++ /dev/null
-From 33e771556f5e1a59c7dbcd953ce858dd3e50ed66 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 23 May 2013 16:32:53 +0200
-Subject: [PATCH 017/203] pci: mvebu: fix the emulation of the status register
-
-The status register of the PCI configuration space of PCI-to-PCI
-bridges contain some read-only bits, and so write-1-to-clear bits. So,
-the Linux PCI core sometimes writes 0xffff to this status register,
-and in the current PCI-to-PCI bridge emulation code of the Marvell
-driver, we do take all those 1s being written. Even the read-only bits
-are being overwritten.
-
-For now, all the read-only bits should be emulated to have the zero
-value.
-
-The other bits, that are write-1-to-clear bits are used to report
-various kind of errors, and are never set by the emulated bridge, so
-there is no need to support this write-1-to-clear bits mechanism.
-
-As a conclusion, the easiest solution is to simply emulate this status
-register by returning zero when read, and ignore the writes to it.
-
-This has two visible effects:
-
- * The devsel is no longer 'unknown' in, i.e
-
- Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0
-
- becomes:
-
- Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0
-
- in lspci -v.
-
- This was caused by a value of 11b being read for devsel, which is
- an invalid value. This 11b value being read was due to a previous
- write of 0xffff into the status register.
-
- * The capability list is no longer broken, because we indicate to the
- Linux PCI core that we don't have a Capabilities Pointer in the PCI
- configuration space of this bridge. The following message is
- therefore no longer visible in lspci -v:
-
- Capabilities: [fc] <chain broken>
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- drivers/pci/host/pci-mvebu.c | 5 +----
- 1 file changed, 1 insertion(+), 4 deletions(-)
-
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -69,7 +69,6 @@ struct mvebu_sw_pci_bridge {
- u16 vendor;
- u16 device;
- u16 command;
-- u16 status;
- u16 class;
- u8 interface;
- u8 revision;
-@@ -359,7 +358,6 @@ static void mvebu_sw_pci_bridge_init(str
-
- memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
-
-- bridge->status = PCI_STATUS_CAP_LIST;
- bridge->class = PCI_CLASS_BRIDGE_PCI;
- bridge->vendor = PCI_VENDOR_ID_MARVELL;
- bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
-@@ -386,7 +384,7 @@ static int mvebu_sw_pci_bridge_read(stru
- break;
-
- case PCI_COMMAND:
-- *value = bridge->status << 16 | bridge->command;
-+ *value = bridge->command;
- break;
-
- case PCI_CLASS_REVISION:
-@@ -479,7 +477,6 @@ static int mvebu_sw_pci_bridge_write(str
- switch (where & ~3) {
- case PCI_COMMAND:
- bridge->command = value & 0xffff;
-- bridge->status = value >> 16;
- break;
-
- case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
+++ /dev/null
-From fc7dfe5cd096f5b5343f01f679a96ebc23e9da67 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Tue, 21 May 2013 12:33:26 +0200
-Subject: [PATCH 018/203] arm: mvebu: fix length of SATA registers area in
- .dtsi
-
-The length of the registers area for the Marvell 370/XP SATA
-controller was incorrect in the .dtsi: 0x2400 while it should have
-been 0x5000. Until now, this problem wasn't noticed because there was
-a large static mapping for all I/Os set up by ->map_io(). But since
-we're going to get rid of this static mapping, we need to ensure that
-the register areas are properly sized.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370-xp.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -80,7 +80,7 @@
-
- sata@a0000 {
- compatible = "marvell,orion-sata";
-- reg = <0xa0000 0x2400>;
-+ reg = <0xa0000 0x5000>;
- interrupts = <55>;
- clocks = <&gateclk 15>, <&gateclk 30>;
- clock-names = "0", "1";
+++ /dev/null
-From d887da014c3fabf5fa4da47b143edc069e72fd62 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Tue, 21 May 2013 12:33:27 +0200
-Subject: [PATCH 019/203] arm: mvebu: fix length of Ethernet registers area in
- .dtsi
-
-The length of the registers area for the Marvell 370/XP Ethernet
-controller was incorrect in the .dtsi: 0x2400 while it should have
-been 0x4000. Until now, this problem wasn't noticed because there was
-a large static mapping for all I/Os set up by ->map_io(). But since
-we're going to get rid of this static mapping, we need to ensure that
-the register areas are properly sized.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++--
- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 2 +-
- arch/arm/boot/dts/armada-xp.dtsi | 2 +-
- 3 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -96,7 +96,7 @@
-
- ethernet@70000 {
- compatible = "marvell,armada-370-neta";
-- reg = <0x70000 0x2500>;
-+ reg = <0x70000 0x4000>;
- interrupts = <8>;
- clocks = <&gateclk 4>;
- status = "disabled";
-@@ -104,7 +104,7 @@
-
- ethernet@74000 {
- compatible = "marvell,armada-370-neta";
-- reg = <0x74000 0x2500>;
-+ reg = <0x74000 0x4000>;
- interrupts = <10>;
- clocks = <&gateclk 3>;
- status = "disabled";
---- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-@@ -107,7 +107,7 @@
-
- ethernet@34000 {
- compatible = "marvell,armada-370-neta";
-- reg = <0x34000 0x2500>;
-+ reg = <0x34000 0x4000>;
- interrupts = <14>;
- clocks = <&gateclk 1>;
- status = "disabled";
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -88,7 +88,7 @@
-
- ethernet@30000 {
- compatible = "marvell,armada-370-neta";
-- reg = <0x30000 0x2500>;
-+ reg = <0x30000 0x4000>;
- interrupts = <12>;
- clocks = <&gateclk 2>;
- status = "disabled";
+++ /dev/null
-From 25d3318a445c4f4360f86bf6d1d1a320d9646bb5 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Tue, 4 Jun 2013 04:52:23 +0000
-Subject: [PATCH 020/203] net: mvneta: read MAC address from hardware when
- available
-
-This patch improves the logic used by the mvneta driver to find a MAC
-address for a particular interface. Until now, it was only looking at
-the Device Tree, and if no address was found, was falling back to
-generating a random MAC address.
-
-This patch adds the intermediate solution of reading the MAC address
-from the hardware registers, in case it has been set by the
-bootloader. So the order is now:
-
- 1) MAC address from the Device Tree
- 2) MAC address from the hardware registers
- 3) Random MAC address
-
-This requires moving the MAC address initialization a little bit later
-in the ->probe() code, because it now requires the hardware registers
-to be remapped.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
-Cc: Joe Perches <joe@perches.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/marvell/mvneta.c | 44 ++++++++++++++++++++++++++++-------
- 1 file changed, 35 insertions(+), 9 deletions(-)
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -2260,6 +2260,21 @@ static int mvneta_change_mtu(struct net_
- return 0;
- }
-
-+/* Get mac address */
-+static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
-+{
-+ u32 mac_addr_l, mac_addr_h;
-+
-+ mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
-+ mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
-+ addr[0] = (mac_addr_h >> 24) & 0xFF;
-+ addr[1] = (mac_addr_h >> 16) & 0xFF;
-+ addr[2] = (mac_addr_h >> 8) & 0xFF;
-+ addr[3] = mac_addr_h & 0xFF;
-+ addr[4] = (mac_addr_l >> 8) & 0xFF;
-+ addr[5] = mac_addr_l & 0xFF;
-+}
-+
- /* Handle setting mac address */
- static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
- {
-@@ -2678,7 +2693,9 @@ static int mvneta_probe(struct platform_
- u32 phy_addr;
- struct mvneta_port *pp;
- struct net_device *dev;
-- const char *mac_addr;
-+ const char *dt_mac_addr;
-+ char hw_mac_addr[ETH_ALEN];
-+ const char *mac_from;
- int phy_mode;
- int err;
-
-@@ -2714,13 +2731,6 @@ static int mvneta_probe(struct platform_
- goto err_free_irq;
- }
-
-- mac_addr = of_get_mac_address(dn);
--
-- if (!mac_addr || !is_valid_ether_addr(mac_addr))
-- eth_hw_addr_random(dev);
-- else
-- memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
--
- dev->tx_queue_len = MVNETA_MAX_TXD;
- dev->watchdog_timeo = 5 * HZ;
- dev->netdev_ops = &mvneta_netdev_ops;
-@@ -2751,6 +2761,21 @@ static int mvneta_probe(struct platform_
-
- clk_prepare_enable(pp->clk);
-
-+ dt_mac_addr = of_get_mac_address(dn);
-+ if (dt_mac_addr && is_valid_ether_addr(dt_mac_addr)) {
-+ mac_from = "device tree";
-+ memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
-+ } else {
-+ mvneta_get_mac_addr(pp, hw_mac_addr);
-+ if (is_valid_ether_addr(hw_mac_addr)) {
-+ mac_from = "hardware";
-+ memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
-+ } else {
-+ mac_from = "random";
-+ eth_hw_addr_random(dev);
-+ }
-+ }
-+
- pp->tx_done_timer.data = (unsigned long)dev;
-
- pp->tx_ring_size = MVNETA_MAX_TXD;
-@@ -2783,7 +2808,8 @@ static int mvneta_probe(struct platform_
- goto err_deinit;
- }
-
-- netdev_info(dev, "mac: %pM\n", dev->dev_addr);
-+ netdev_info(dev, "Using %s mac address %pM\n", mac_from,
-+ dev->dev_addr);
-
- platform_set_drvdata(pdev, pp->dev);
-
+++ /dev/null
-From 67373874e07eb8c54ab27f8fe9998690e50b1e91 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 6 Jun 2013 11:21:23 +0200
-Subject: [PATCH 021/203] arm: mvebu: armada-xp-db: ensure PCIe range is
- specified
-
-The ranges DT entry needed by the PCIe controller is defined at the
-SoC .dtsi level. However, some boards have a NOR flash, and to support
-it, they need to override the SoC-level ranges property to add an
-additional range. Since PCIe and NOR support came separately, some
-boards were not properly changed to include the PCIe range in their
-ranges property at the .dts level.
-
-This commit fixes those platforms.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-xp-db.dts | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/boot/dts/armada-xp-db.dts
-+++ b/arch/arm/boot/dts/armada-xp-db.dts
-@@ -31,6 +31,7 @@
-
- soc {
- ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
-+ 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
- 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
-
- internal-regs {
+++ /dev/null
-From 35e8d985e056f583290406258e3f17789bd05bce Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Fri, 7 Jun 2013 13:47:38 -0300
-Subject: [PATCH 022/203] bus: mvebu-mbus: Use pr_fmt
-
-In order to clean message printing, we replace pr_info with pr_fmt.
-This is purely cosmetic change, with the sole purpose of making
-the code a bit more readable.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- drivers/bus/mvebu-mbus.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -49,6 +49,8 @@
- * configuration (file 'devices').
- */
-
-+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-+
- #include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/init.h>
-@@ -762,7 +764,7 @@ int mvebu_mbus_add_window_remap_flags(co
- break;
-
- if (!s->soc->map[i].name) {
-- pr_err("mvebu-mbus: unknown device '%s'\n", devname);
-+ pr_err("unknown device '%s'\n", devname);
- return -ENODEV;
- }
-
-@@ -775,7 +777,7 @@ int mvebu_mbus_add_window_remap_flags(co
- attr |= 0x28;
-
- if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) {
-- pr_err("mvebu-mbus: cannot add window '%s', conflicts with another window\n",
-+ pr_err("cannot add window '%s', conflicts with another window\n",
- devname);
- return -EINVAL;
- }
-@@ -842,7 +844,7 @@ int __init mvebu_mbus_init(const char *s
- break;
-
- if (!of_id->compatible) {
-- pr_err("mvebu-mbus: could not find a matching SoC family\n");
-+ pr_err("could not find a matching SoC family\n");
- return -ENODEV;
- }
-
+++ /dev/null
-From df8ceea297967c3452a514bbde715acebf3bda29 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Fri, 7 Jun 2013 13:47:49 -0300
-Subject: [PATCH 023/203] ARM: mvebu: Remove device tree unused properties on
- A370
-
-These properties are not needed so it's safe to remove them.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370.dtsi | 4 ----
- 1 file changed, 4 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -180,10 +180,6 @@
-
- bus-range = <0x00 0xff>;
-
-- reg = <0x40000 0x2000>, <0x80000 0x2000>;
--
-- reg-names = "pcie0.0", "pcie1.0";
--
- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
+++ /dev/null
-From 9398729313b826469fede3acda5fedd1eb21cb3e Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 5 Jun 2013 09:04:54 +0200
-Subject: [PATCH 024/203] arm: mvebu: remove dependency of SMP init on static
- I/O mapping
-
-The ->smp_init_cpus() function is called very early during boot, at a
-point where dynamic I/O mappings are not yet possible. However, in the
-Armada 370/XP implementation of this function, we have to get the
-number of CPUs. We used to do that by accessing a hardware register,
-which requires relying on a static I/O mapping set up by
-->map_io(). Not only this requires hardcoding a virtual address, but
-it also prevents us from removing the static I/O mapping.
-
-So this commit changes the way used to get the number of CPUs: we now
-use the Device Tree, which is a representation of the hardware, and
-provides us the number of available CPUs. This is also more accurate,
-because it potentially allows to boot the Linux kernel on only a
-number of CPUs given by the Device Tree, instead of unconditionally on
-all CPUs.
-
-As a consequence, the coherency_get_cpu_count() function becomes no
-longer used, so we remove it.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/mach-mvebu/coherency.c | 12 ------------
- arch/arm/mach-mvebu/coherency.h | 4 ----
- arch/arm/mach-mvebu/common.h | 2 ++
- arch/arm/mach-mvebu/platsmp.c | 10 +++++++++-
- 4 files changed, 11 insertions(+), 17 deletions(-)
-
---- a/arch/arm/mach-mvebu/coherency.c
-+++ b/arch/arm/mach-mvebu/coherency.c
-@@ -47,18 +47,6 @@ static struct of_device_id of_coherency_
- { /* end of list */ },
- };
-
--#ifdef CONFIG_SMP
--int coherency_get_cpu_count(void)
--{
-- int reg, cnt;
--
-- reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
-- cnt = (reg & 0xF) + 1;
--
-- return cnt;
--}
--#endif
--
- /* Function defined in coherency_ll.S */
- int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
-
---- a/arch/arm/mach-mvebu/coherency.h
-+++ b/arch/arm/mach-mvebu/coherency.h
-@@ -14,10 +14,6 @@
- #ifndef __MACH_370_XP_COHERENCY_H
- #define __MACH_370_XP_COHERENCY_H
-
--#ifdef CONFIG_SMP
--int coherency_get_cpu_count(void);
--#endif
--
- int set_cpu_coherent(int cpu_id, int smp_group_id);
- int coherency_init(void);
-
---- a/arch/arm/mach-mvebu/common.h
-+++ b/arch/arm/mach-mvebu/common.h
-@@ -15,6 +15,8 @@
- #ifndef __ARCH_MVEBU_COMMON_H
- #define __ARCH_MVEBU_COMMON_H
-
-+#define ARMADA_XP_MAX_CPUS 4
-+
- void mvebu_restart(char mode, const char *cmd);
-
- void armada_370_xp_init_irq(void);
---- a/arch/arm/mach-mvebu/platsmp.c
-+++ b/arch/arm/mach-mvebu/platsmp.c
-@@ -88,8 +88,16 @@ static int __cpuinit armada_xp_boot_seco
-
- static void __init armada_xp_smp_init_cpus(void)
- {
-+ struct device_node *np;
- unsigned int i, ncores;
-- ncores = coherency_get_cpu_count();
-+
-+ np = of_find_node_by_name(NULL, "cpus");
-+ if (!np)
-+ panic("No 'cpus' node found\n");
-+
-+ ncores = of_get_child_count(np);
-+ if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
-+ panic("Invalid number of CPUs in DT\n");
-
- /* Limit possible CPUs to defconfig */
- if (ncores > nr_cpu_ids) {
+++ /dev/null
-From a4dd628f515f361cecfae08e568891442042e4e2 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 5 Jun 2013 09:04:55 +0200
-Subject: [PATCH 025/203] arm: mvebu: avoid hardcoded virtual address in
- coherency code
-
-Now that the coherency_get_cpu_count() function no longer requires a
-very early mapping of the coherency unit registers, we can avoid the
-hardcoded virtual address in coherency.c. However, the coherency
-features are still used quite early, so we need to do the of_iomap()
-early enough, at the ->init_timer() level, so we have the call of
-coherency_init() at this point.
-
-Unfortunately, at ->init_timer() time, it is not possible to register
-a bus notifier, so we add a separate coherency_late_init() function
-that gets called as as postcore_initcall(), when bus notifiers are
-available.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/mach-mvebu/armada-370-xp.c | 2 +-
- arch/arm/mach-mvebu/coherency.c | 20 ++++++++++----------
- 2 files changed, 11 insertions(+), 11 deletions(-)
-
---- a/arch/arm/mach-mvebu/armada-370-xp.c
-+++ b/arch/arm/mach-mvebu/armada-370-xp.c
-@@ -47,6 +47,7 @@ static void __init armada_370_xp_timer_a
- {
- mvebu_clocks_init();
- armada_370_xp_timer_init();
-+ coherency_init();
- }
-
- static void __init armada_370_xp_init_early(void)
-@@ -76,7 +77,6 @@ static void __init armada_370_xp_init_ea
- static void __init armada_370_xp_dt_init(void)
- {
- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- coherency_init();
- }
-
- static const char * const armada_370_xp_dt_compat[] = {
---- a/arch/arm/mach-mvebu/coherency.c
-+++ b/arch/arm/mach-mvebu/coherency.c
-@@ -27,14 +27,7 @@
- #include <asm/smp_plat.h>
- #include "armada-370-xp.h"
-
--/*
-- * Some functions in this file are called very early during SMP
-- * initialization. At that time the device tree framework is not yet
-- * ready, and it is not possible to get the register address to
-- * ioremap it. That's why the pointer below is given with an initial
-- * value matching its virtual mapping
-- */
--static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
-+static void __iomem *coherency_base;
- static void __iomem *coherency_cpu_base;
-
- /* Coherency fabric registers */
-@@ -135,9 +128,16 @@ int __init coherency_init(void)
- coherency_base = of_iomap(np, 0);
- coherency_cpu_base = of_iomap(np, 1);
- set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
-- bus_register_notifier(&platform_bus_type,
-- &mvebu_hwcc_platform_nb);
- }
-
- return 0;
- }
-+
-+static int __init coherency_late_init(void)
-+{
-+ bus_register_notifier(&platform_bus_type,
-+ &mvebu_hwcc_platform_nb);
-+ return 0;
-+}
-+
-+postcore_initcall(coherency_late_init);
+++ /dev/null
-From c7c7e6309ae12f2cb0d9053875876b57bb7587e4 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 5 Jun 2013 09:04:56 +0200
-Subject: [PATCH 026/203] arm: mvebu: move cache and mvebu-mbus initialization
- later
-
-Current, the L2 cache and the mvebu-mbus drivers are initialized at
-->init_early() time. However, at ->init_early() time, ioremap() only
-works if a static I/O mapping has already been put in place. If it's
-not the case, it tries to do a memory allocation with kmalloc() which
-is not possible so early at this stage of the initialization.
-
-Since we want to get rid of the static I/O mapping, we cannot
-initialize the L2 cache driver and the mvebu-mbus driver so early. So,
-we move their initialization to the ->init_time() level, which is
-slightly later (so ioremap() works properly), but sufficiently early
-to be before the call of the ->smp_prepare_cpus() hook, which creates
-an address decoding window for the BootROM, which requires the
-mvebu-mbus driver to be properly initialized.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/mach-mvebu/armada-370-xp.c | 8 ++------
- 1 file changed, 2 insertions(+), 6 deletions(-)
-
---- a/arch/arm/mach-mvebu/armada-370-xp.c
-+++ b/arch/arm/mach-mvebu/armada-370-xp.c
-@@ -45,14 +45,11 @@ static void __init armada_370_xp_map_io(
-
- static void __init armada_370_xp_timer_and_clk_init(void)
- {
-+ char *mbus_soc_name;
-+
- mvebu_clocks_init();
- armada_370_xp_timer_init();
- coherency_init();
--}
--
--static void __init armada_370_xp_init_early(void)
--{
-- char *mbus_soc_name;
-
- /*
- * This initialization will be replaced by a DT-based
-@@ -88,7 +85,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell
- .smp = smp_ops(armada_xp_smp_ops),
- .init_machine = armada_370_xp_dt_init,
- .map_io = armada_370_xp_map_io,
-- .init_early = armada_370_xp_init_early,
- .init_irq = irqchip_init,
- .init_time = armada_370_xp_timer_and_clk_init,
- .restart = mvebu_restart,
+++ /dev/null
-From fe4fce3c521f5d9f3a64c4d06a73a5e6b7324116 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 5 Jun 2013 09:04:57 +0200
-Subject: [PATCH 027/203] arm: mvebu: remove hardcoded static I/O mapping
-
-Now that we have removed the need of the static I/O mapping for early
-initialization reasons, and fixed the registers area length that were
-broken, we can get rid of the static I/O mapping. Only the earlyprintk
-mapping needs to be set up, using the debug_ll_io_init() helper
-function.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/mach-mvebu/armada-370-xp.c | 11 +----------
- arch/arm/mach-mvebu/armada-370-xp.h | 2 --
- 2 files changed, 1 insertion(+), 12 deletions(-)
-
---- a/arch/arm/mach-mvebu/armada-370-xp.c
-+++ b/arch/arm/mach-mvebu/armada-370-xp.c
-@@ -29,18 +29,9 @@
- #include "common.h"
- #include "coherency.h"
-
--static struct map_desc armada_370_xp_io_desc[] __initdata = {
-- {
-- .virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
-- .pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
-- .length = ARMADA_370_XP_REGS_SIZE,
-- .type = MT_DEVICE,
-- },
--};
--
- static void __init armada_370_xp_map_io(void)
- {
-- iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
-+ debug_ll_io_init();
- }
-
- static void __init armada_370_xp_timer_and_clk_init(void)
---- a/arch/arm/mach-mvebu/armada-370-xp.h
-+++ b/arch/arm/mach-mvebu/armada-370-xp.h
-@@ -16,8 +16,6 @@
- #define __MACH_ARMADA_370_XP_H
-
- #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
--#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfec00000)
--#define ARMADA_370_XP_REGS_SIZE SZ_1M
-
- /* These defines can go away once mvebu-mbus has a DT binding */
- #define ARMADA_370_XP_MBUS_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
+++ /dev/null
-From 88260610ea7a2c5a164721af28f59856880221b4 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 6 Jun 2013 12:24:28 +0200
-Subject: [PATCH 028/203] arm: mvebu: don't hardcode a physical address in
- headsmp.S
-
-Now that the coherency_init() function is called a bit earlier, we can
-actually read the physical address of the coherency unit registers
-from the Device Tree, and communicate that to the headsmp.S code,
-which avoids hardcoding a physical address.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Reviewed-by: Will Deacon <will.deacon@arm.com>
-Acked-by: Nicolas Pitre <nico@linaro.org>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/mach-mvebu/coherency.c | 12 ++++++++++++
- arch/arm/mach-mvebu/headsmp.S | 16 ++++++++--------
- 2 files changed, 20 insertions(+), 8 deletions(-)
-
---- a/arch/arm/mach-mvebu/coherency.c
-+++ b/arch/arm/mach-mvebu/coherency.c
-@@ -25,8 +25,10 @@
- #include <linux/dma-mapping.h>
- #include <linux/platform_device.h>
- #include <asm/smp_plat.h>
-+#include <asm/cacheflush.h>
- #include "armada-370-xp.h"
-
-+unsigned long __cpuinitdata coherency_phys_base;
- static void __iomem *coherency_base;
- static void __iomem *coherency_cpu_base;
-
-@@ -124,7 +126,17 @@ int __init coherency_init(void)
-
- np = of_find_matching_node(NULL, of_coherency_table);
- if (np) {
-+ struct resource res;
- pr_info("Initializing Coherency fabric\n");
-+ of_address_to_resource(np, 0, &res);
-+ coherency_phys_base = res.start;
-+ /*
-+ * Ensure secondary CPUs will see the updated value,
-+ * which they read before they join the coherency
-+ * fabric, and therefore before they are coherent with
-+ * the boot CPU cache.
-+ */
-+ sync_cache_w(&coherency_phys_base);
- coherency_base = of_iomap(np, 0);
- coherency_cpu_base = of_iomap(np, 1);
- set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
---- a/arch/arm/mach-mvebu/headsmp.S
-+++ b/arch/arm/mach-mvebu/headsmp.S
-@@ -21,12 +21,6 @@
- #include <linux/linkage.h>
- #include <linux/init.h>
-
--/*
-- * At this stage the secondary CPUs don't have acces yet to the MMU, so
-- * we have to provide physical addresses
-- */
--#define ARMADA_XP_CFB_BASE 0xD0020200
--
- __CPUINIT
-
- /*
-@@ -35,15 +29,21 @@
- * startup
- */
- ENTRY(armada_xp_secondary_startup)
-+ /* Get coherency fabric base physical address */
-+ adr r0, 1f
-+ ldr r1, [r0]
-+ ldr r0, [r0, r1]
-
- /* Read CPU id */
- mrc p15, 0, r1, c0, c0, 5
- and r1, r1, #0xF
-
- /* Add CPU to coherency fabric */
-- ldr r0, =ARMADA_XP_CFB_BASE
--
- bl ll_set_cpu_coherent
- b secondary_startup
-
- ENDPROC(armada_xp_secondary_startup)
-+
-+ .align 2
-+1:
-+ .long coherency_phys_base - .
+++ /dev/null
-From 070469397154c87b14fab48d2fc231ba83007c1b Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 5 Jun 2013 09:04:59 +0200
-Subject: [PATCH 029/203] arm: mvebu: don't hardcode the physical address for
- mvebu-mbus
-
-Since the mvebu-mbus driver doesn't yet have a DT binding (and this DT
-binding may not necessarily be ready for 3.11), the physical address
-of the mvebu-mbus registers are currently hardcoded. This doesn't play
-well with the fact that the internal registers base address may be
-different depending on the bootloader.
-
-In order to have only one central place for the physical address of
-the internal registers, we now use of_translate_address() to translate
-the mvebu-mbus register offsets into the real physical address, by
-using DT-based address translation. This will go away once the
-mvebu-mbus driver gains a proper DT binding.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/mach-mvebu/armada-370-xp.c | 38 ++++++++++++++++++++++++++-----------
- arch/arm/mach-mvebu/armada-370-xp.h | 8 --------
- 2 files changed, 27 insertions(+), 19 deletions(-)
-
---- a/arch/arm/mach-mvebu/armada-370-xp.c
-+++ b/arch/arm/mach-mvebu/armada-370-xp.c
-@@ -14,6 +14,7 @@
-
- #include <linux/kernel.h>
- #include <linux/init.h>
-+#include <linux/of_address.h>
- #include <linux/of_platform.h>
- #include <linux/io.h>
- #include <linux/time-armada-370-xp.h>
-@@ -34,29 +35,44 @@ static void __init armada_370_xp_map_io(
- debug_ll_io_init();
- }
-
--static void __init armada_370_xp_timer_and_clk_init(void)
-+/*
-+ * This initialization will be replaced by a DT-based
-+ * initialization once the mvebu-mbus driver gains DT support.
-+ */
-+
-+#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000
-+#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
-+#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180
-+#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
-+
-+static void __init armada_370_xp_mbus_init(void)
- {
- char *mbus_soc_name;
-+ struct device_node *dn;
-+ const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
-+ const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
-
-- mvebu_clocks_init();
-- armada_370_xp_timer_init();
-- coherency_init();
--
-- /*
-- * This initialization will be replaced by a DT-based
-- * initialization once the mvebu-mbus driver gains DT support.
-- */
- if (of_machine_is_compatible("marvell,armada370"))
- mbus_soc_name = "marvell,armada370-mbus";
- else
- mbus_soc_name = "marvell,armadaxp-mbus";
-
-+ dn = of_find_node_by_name(NULL, "internal-regs");
-+ BUG_ON(!dn);
-+
- mvebu_mbus_init(mbus_soc_name,
-- ARMADA_370_XP_MBUS_WINS_BASE,
-+ of_translate_address(dn, &mbus_wins_offs),
- ARMADA_370_XP_MBUS_WINS_SIZE,
-- ARMADA_370_XP_SDRAM_WINS_BASE,
-+ of_translate_address(dn, &sdram_wins_offs),
- ARMADA_370_XP_SDRAM_WINS_SIZE);
-+}
-
-+static void __init armada_370_xp_timer_and_clk_init(void)
-+{
-+ mvebu_clocks_init();
-+ armada_370_xp_timer_init();
-+ coherency_init();
-+ armada_370_xp_mbus_init();
- #ifdef CONFIG_CACHE_L2X0
- l2x0_of_init(0, ~0UL);
- #endif
---- a/arch/arm/mach-mvebu/armada-370-xp.h
-+++ b/arch/arm/mach-mvebu/armada-370-xp.h
-@@ -15,14 +15,6 @@
- #ifndef __MACH_ARMADA_370_XP_H
- #define __MACH_ARMADA_370_XP_H
-
--#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
--
--/* These defines can go away once mvebu-mbus has a DT binding */
--#define ARMADA_370_XP_MBUS_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
--#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
--#define ARMADA_370_XP_SDRAM_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180)
--#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
--
- #ifdef CONFIG_SMP
- #include <linux/cpumask.h>
-
+++ /dev/null
-From 70c30ca997919a4b8c9051a3903f30c79c735f12 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 5 Jun 2013 09:05:00 +0200
-Subject: [PATCH 030/203] arm: mvebu: add another earlyprintk Kconfig option
-
-In order to support both old and new bootloaders, we add a new Kconfig
-option for the earlyprintk UART selection. The existing option allows
-to work with old bootloaders (that keep the internal registers mapped
-at 0xd0000000), while the newly introduced option allows to work with
-new bootloaders (that remap the internal registers at 0xf1000000).
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/Kconfig.debug | 30 ++++++++++++++++++++++++++++--
- arch/arm/include/debug/mvebu.S | 5 +++++
- 2 files changed, 33 insertions(+), 2 deletions(-)
-
---- a/arch/arm/Kconfig.debug
-+++ b/arch/arm/Kconfig.debug
-@@ -303,12 +303,37 @@ choice
- their output to the serial port on MSM 8960 devices.
-
- config DEBUG_MVEBU_UART
-- bool "Kernel low-level debugging messages via MVEBU UART"
-+ bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)"
- depends on ARCH_MVEBU
- help
- Say Y here if you want kernel low-level debugging support
- on MVEBU based platforms.
-
-+ This option should be used with the old bootloaders
-+ that left the internal registers mapped at
-+ 0xd0000000. As of today, this is the case on
-+ platforms such as the Globalscale Mirabox or the
-+ Plathome OpenBlocks AX3, when using the original
-+ bootloader.
-+
-+ If the wrong DEBUG_MVEBU_UART* option is selected,
-+ when u-boot hands over to the kernel, the system
-+ silently crashes, with no serial output at all.
-+
-+ config DEBUG_MVEBU_UART_ALTERNATE
-+ bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)"
-+ depends on ARCH_MVEBU
-+ help
-+ Say Y here if you want kernel low-level debugging support
-+ on MVEBU based platforms.
-+
-+ This option should be used with the new bootloaders
-+ that remap the internal registers at 0xf1000000.
-+
-+ If the wrong DEBUG_MVEBU_UART* option is selected,
-+ when u-boot hands over to the kernel, the system
-+ silently crashes, with no serial output at all.
-+
- config DEBUG_NOMADIK_UART
- bool "Kernel low-level debugging messages via NOMADIK UART"
- depends on ARCH_NOMADIK
-@@ -632,7 +657,8 @@ config DEBUG_LL_INCLUDE
- DEBUG_IMX51_UART || \
- DEBUG_IMX53_UART ||\
- DEBUG_IMX6Q_UART
-- default "debug/mvebu.S" if DEBUG_MVEBU_UART
-+ default "debug/mvebu.S" if DEBUG_MVEBU_UART || \
-+ DEBUG_MVEBU_UART_ALTERNATE
- default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
- default "debug/nomadik.S" if DEBUG_NOMADIK_UART
- default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
---- a/arch/arm/include/debug/mvebu.S
-+++ b/arch/arm/include/debug/mvebu.S
-@@ -11,7 +11,12 @@
- * published by the Free Software Foundation.
- */
-
-+#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE
-+#define ARMADA_370_XP_REGS_PHYS_BASE 0xf1000000
-+#else
- #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
-+#endif
-+
- #define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000
-
- .macro addruart, rp, rv, tmp
+++ /dev/null
-From 7a3b99b8d16f2eb9ae5ac4ddf5e201eacdfacbf4 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 5 Jun 2013 09:05:01 +0200
-Subject: [PATCH 031/203] arm: mvebu: disable DEBUG_LL/EARLY_PRINTK in
- defconfig
-
-Now that we have two different addresses for the UART, depending on
-which bootloader is used, it is no longer desirable to enable
-earlyprintk by default in the defconfig. Users who need earlyprintk
-support will have to enable it explicitly, and select the right UART
-configuration depending on their platform.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/configs/mvebu_defconfig | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/arch/arm/configs/mvebu_defconfig
-+++ b/arch/arm/configs/mvebu_defconfig
-@@ -100,5 +100,3 @@ CONFIG_TIMER_STATS=y
- # CONFIG_DEBUG_BUGVERBOSE is not set
- CONFIG_DEBUG_INFO=y
- CONFIG_DEBUG_USER=y
--CONFIG_DEBUG_LL=y
--CONFIG_EARLY_PRINTK=y
+++ /dev/null
-From e552d168344e941a1781682207269dbfd27850b1 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Tue, 18 Jun 2013 15:37:41 +0200
-Subject: [PATCH 032/203] arm: mvebu: enable mini-PCIe connectors on Armada 370
- RD
-
-The Armada 370 RD board has two internal mini-PCIe connectors. This
-commit adds the necessary Device Tree informations to enable the usage
-of those mini-PCIe connectors.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Cc: Florian Fainelli <florian@openwrt.org>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370-rd.dts | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/arch/arm/boot/dts/armada-370-rd.dts
-+++ b/arch/arm/boot/dts/armada-370-rd.dts
-@@ -85,6 +85,22 @@
- gpios = <&gpio0 6 1>;
- };
- };
-+
-+ pcie-controller {
-+ status = "okay";
-+
-+ /* Internal mini-PCIe connector */
-+ pcie@1,0 {
-+ /* Port 0, Lane 0 */
-+ status = "okay";
-+ };
-+
-+ /* Internal mini-PCIe connector */
-+ pcie@2,0 {
-+ /* Port 1, Lane 0 */
-+ status = "okay";
-+ };
-+ };
- };
- };
- };
+++ /dev/null
-From 3891658a01af7e875d4c176ebb5d713d74a6e998 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 20 Jun 2013 09:45:26 +0200
-Subject: [PATCH 033/203] arm: mvebu: fix coherency_late_init() for
- multiplatform
-
-As noticed by Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>, commit
-865e0527d2d7 ('arm: mvebu: avoid hardcoded virtual address in
-coherency code') added a postcore_initcall() to register the bus
-notifier that the mvebu code needs to apply correct DMA operations on
-its platform devices breaks the multiplatform boot on other platforms,
-because the bus notifier registration is unconditional.
-
-This commit fixes that by registering the bus notifier only if we have
-the mvebu coherency unit described in the Device Tree. The conditional
-used is exactly the same in which the bus_register_notifier() call was
-originally enclosed before 865e0527d2d7 ('arm: mvebu: avoid hardcoded
-virtual address in coherency code').
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Reported-by: Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
-Acked-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/mach-mvebu/coherency.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/arch/arm/mach-mvebu/coherency.c
-+++ b/arch/arm/mach-mvebu/coherency.c
-@@ -147,8 +147,9 @@ int __init coherency_init(void)
-
- static int __init coherency_late_init(void)
- {
-- bus_register_notifier(&platform_bus_type,
-- &mvebu_hwcc_platform_nb);
-+ if (of_find_matching_node(NULL, of_coherency_table))
-+ bus_register_notifier(&platform_bus_type,
-+ &mvebu_hwcc_platform_nb);
- return 0;
- }
-
+++ /dev/null
-From 4f6da1286d2602e00c049c29eb9e816587c752a5 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Sat, 22 Jun 2013 13:52:27 -0300
-Subject: [PATCH 034/203] ARM: mvebu: fix length of ethernet registers in
- mv78260 dtsi
-
-The length of the registers area for the Marvell 370/XP Ethernet controller
-was incorrect in the .dtsi: 0x2500, while it should have been 0x4000.
-This problem wasn't noticed because there used to be a static mapping for
-all the MMIO register region set up by ->map_io().
-
-The register length was fixed in all the other device tree files,
-except from the armada-xp-mv78260.dtsi, in the following commit:
-
- commit cf8088c5cac6ce20d914b9131533844b9291a054
- Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- Date: Tue May 21 12:33:27 2013 +0200
-
- arm: mvebu: fix length of Ethernet registers area in .dtsi
-
-This commit fixes a kernel panic in mvneta_probe(), when the kernel
-tries to access the unmapped registers:
-
-[ 163.639092] mvneta d0070000.ethernet eth0: mac: 6e:3c:4f:87:17:2e
-[ 163.646962] mvneta d0074000.ethernet eth1: mac: 6a:04:4e:6f:f5:ef
-[ 163.654853] mvneta d0030000.ethernet eth2: mac: 2a:99:19:19:fc:4c
-[ 163.661258] Unable to handle kernel paging request at virtual address f011bcf0
-[ 163.668523] pgd = c0004000
-[ 163.671237] [f011bcf0] *pgd=2f006811, *pte=00000000, *ppte=00000000
-[ 163.677565] Internal error: Oops: 807 [#1] SMP ARM
-[ 163.682370] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc6-01850-gba0682e #11
-[ 163.690046] task: ef04c000 ti: ef03e000 task.ti: ef03e000
-[ 163.695467] PC is at mvneta_probe+0x34c/0xabc
-[...]
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-@@ -92,7 +92,7 @@
-
- ethernet@34000 {
- compatible = "marvell,armada-370-neta";
-- reg = <0x34000 0x2500>;
-+ reg = <0x34000 0x4000>;
- interrupts = <14>;
- clocks = <&gateclk 1>;
- status = "disabled";
+++ /dev/null
-From 76de914223ec09274a7857e0d8cd7b739205dc3c Mon Sep 17 00:00:00 2001
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Fri, 21 Jun 2013 15:32:06 +0200
-Subject: [PATCH 035/203] i2c: mv64xxx: Set bus frequency to 100kHz if
- clock-frequency is not provided
-
-This commit adds checking whether clock-frequency property acquisition
-has succeeded. If not, the frequency is set to 100kHz by default.
-
-The Device Tree binding documentation is updated accordingly.
-
-Based on the intials patches from Zbigniew Bodek
-
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: Zbigniew Bodek <zbb@semihalf.com>
-Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
----
- Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt | 6 +++++-
- drivers/i2c/busses/i2c-mv64xxx.c | 6 +++++-
- 2 files changed, 10 insertions(+), 2 deletions(-)
-
---- a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
-+++ b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
-@@ -6,7 +6,11 @@ Required properties :
- - reg : Offset and length of the register set for the device
- - compatible : Should be "marvell,mv64xxx-i2c"
- - interrupts : The interrupt number
-- - clock-frequency : Desired I2C bus clock frequency in Hz.
-+
-+Optional properties :
-+
-+ - clock-frequency : Desired I2C bus clock frequency in Hz. If not set the
-+default frequency is 100kHz
-
- Examples:
-
---- a/drivers/i2c/busses/i2c-mv64xxx.c
-+++ b/drivers/i2c/busses/i2c-mv64xxx.c
-@@ -580,7 +580,11 @@ mv64xxx_of_config(struct mv64xxx_i2c_dat
- goto out;
- }
- tclk = clk_get_rate(drv_data->clk);
-- of_property_read_u32(np, "clock-frequency", &bus_freq);
-+
-+ rc = of_property_read_u32(np, "clock-frequency", &bus_freq);
-+ if (rc)
-+ bus_freq = 100000; /* 100kHz by default */
-+
- if (!mv64xxx_find_baud_factors(bus_freq, tclk,
- &drv_data->freq_n, &drv_data->freq_m)) {
- rc = -EINVAL;
+++ /dev/null
-From 71a32c9519ba223d1dafcbe58d1699710720c5a8 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 1 Aug 2013 15:44:19 +0200
-Subject: [PATCH 036/203] PCI: mvebu: Disable prefetchable memory support in
- PCI-to-PCI bridge
-
-The Marvell PCIe driver uses an emulated PCI-to-PCI bridge to be able
-to dynamically set up MBus address decoding windows for PCI I/O and
-memory regions depending on the PCI devices enumerated by Linux.
-
-However, this emulated PCI-to-PCI bridge logic makes the Linux PCI
-core believe that prefetchable memory regions are supported (because
-the registers are read/write), while in fact no adress decoding window
-is ever created for such regions. Since the Marvell MBus address
-decoding windows do not distinguish memory regions and prefetchable
-memory regions, this patch takes a simple approach: change the
-PCI-to-PCI bridge emulation to let the Linux PCI core know that we
-don't support prefetchable memory regions.
-
-To achieve this, we simply make the prefetchable memory base a
-read-only register that always returns 0. Reading/writing all the
-other prefetchable memory related registers has no effect.
-
-This problem was originally reported by Finn Hoffmann
-<finn@uni-bremen.de>, who couldn't get a RTL8111/8168B PCI NIC working
-on the NSA310 Kirkwood platform after updating to 3.11-rc. The problem
-was that the PCI-to-PCI bridge emulation was making the Linux PCI core
-believe that we support prefetchable memory, so the Linux PCI core was
-only filling the prefetchable memory base and limit registers, which
-does not lead to a MBus window being created. The below patch has been
-confirmed by Finn Hoffmann to fix his problem on Kirkwood, and has
-otherwise been successfully tested on the Armada XP GP platform with a
-e1000e PCIe NIC and a Marvell SATA PCIe card.
-
-Reported-by: Finn Hoffmann <finn@uni-bremen.de>
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
----
- drivers/pci/host/pci-mvebu.c | 27 +--------------------------
- 1 file changed, 1 insertion(+), 26 deletions(-)
-
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -86,10 +86,6 @@ struct mvebu_sw_pci_bridge {
- u16 secondary_status;
- u16 membase;
- u16 memlimit;
-- u16 prefmembase;
-- u16 prefmemlimit;
-- u32 prefbaseupper;
-- u32 preflimitupper;
- u16 iobaseupper;
- u16 iolimitupper;
- u8 cappointer;
-@@ -419,15 +415,7 @@ static int mvebu_sw_pci_bridge_read(stru
- break;
-
- case PCI_PREF_MEMORY_BASE:
-- *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
-- break;
--
-- case PCI_PREF_BASE_UPPER32:
-- *value = bridge->prefbaseupper;
-- break;
--
-- case PCI_PREF_LIMIT_UPPER32:
-- *value = bridge->preflimitupper;
-+ *value = 0;
- break;
-
- case PCI_IO_BASE_UPPER16:
-@@ -501,19 +489,6 @@ static int mvebu_sw_pci_bridge_write(str
- mvebu_pcie_handle_membase_change(port);
- break;
-
-- case PCI_PREF_MEMORY_BASE:
-- bridge->prefmembase = value & 0xffff;
-- bridge->prefmemlimit = value >> 16;
-- break;
--
-- case PCI_PREF_BASE_UPPER32:
-- bridge->prefbaseupper = value;
-- break;
--
-- case PCI_PREF_LIMIT_UPPER32:
-- bridge->preflimitupper = value;
-- break;
--
- case PCI_IO_BASE_UPPER16:
- bridge->iobaseupper = value & 0xffff;
- bridge->iolimitupper = value >> 16;
+++ /dev/null
-From 9760aafa716292050a96d71a4bd7bd4e66053975 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 21 May 2013 10:24:48 -0300
-Subject: [PATCH 037/203] memory: mvebu-devbus: Remove address decoding window
- workaround
-
-Now that mbus device tree binding has been introduced, remove the address
-decoding window management from this driver.
-A suitable 'ranges' entry should be added to the devbus-compatible node in
-the device tree, as described by the mbus binding documentation.
-
-Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/memory/mvebu-devbus.c | 64 ++-----------------------------------------
- 1 file changed, 2 insertions(+), 62 deletions(-)
-
---- a/drivers/memory/mvebu-devbus.c
-+++ b/drivers/memory/mvebu-devbus.c
-@@ -208,16 +208,11 @@ static int mvebu_devbus_probe(struct pla
- {
- struct device *dev = &pdev->dev;
- struct device_node *node = pdev->dev.of_node;
-- struct device_node *parent;
- struct devbus *devbus;
- struct resource *res;
- struct clk *clk;
- unsigned long rate;
-- const __be32 *ranges;
-- int err, cs;
-- int addr_cells, p_addr_cells, size_cells;
-- int ranges_len, tuple_len;
-- u32 base, size;
-+ int err;
-
- devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
- if (!devbus)
-@@ -248,68 +243,13 @@ static int mvebu_devbus_probe(struct pla
- return err;
-
- /*
-- * Allocate an address window for this device.
-- * If the device probing fails, then we won't be able to
-- * remove the allocated address decoding window.
-- *
-- * FIXME: This is only a temporary hack! We need to do this here
-- * because we still don't have device tree bindings for mbus.
-- * Once that support is added, we will declare these address windows
-- * statically in the device tree, and remove the window configuration
-- * from here.
-- */
--
-- /*
-- * Get the CS to choose the window string.
-- * This is a bit hacky, but it will be removed once the
-- * address windows are declared in the device tree.
-- */
-- cs = (((unsigned long)devbus->base) % 0x400) / 8;
--
-- /*
-- * Parse 'ranges' property to obtain a (base,size) window tuple.
-- * This will be removed once the address windows
-- * are declared in the device tree.
-- */
-- parent = of_get_parent(node);
-- if (!parent)
-- return -EINVAL;
--
-- p_addr_cells = of_n_addr_cells(parent);
-- of_node_put(parent);
--
-- addr_cells = of_n_addr_cells(node);
-- size_cells = of_n_size_cells(node);
-- tuple_len = (p_addr_cells + addr_cells + size_cells) * sizeof(__be32);
--
-- ranges = of_get_property(node, "ranges", &ranges_len);
-- if (ranges == NULL || ranges_len != tuple_len)
-- return -EINVAL;
--
-- base = of_translate_address(node, ranges + addr_cells);
-- if (base == OF_BAD_ADDR)
-- return -EINVAL;
-- size = of_read_number(ranges + addr_cells + p_addr_cells, size_cells);
--
-- /*
-- * Create an mbus address windows.
-- * FIXME: Remove this, together with the above code, once the
-- * address windows are declared in the device tree.
-- */
-- err = mvebu_mbus_add_window(devbus_wins[cs], base, size);
-- if (err < 0)
-- return err;
--
-- /*
- * We need to create a child device explicitly from here to
- * guarantee that the child will be probed after the timing
- * parameters for the bus are written.
- */
- err = of_platform_populate(node, NULL, NULL, dev);
-- if (err < 0) {
-- mvebu_mbus_del_window(base, size);
-+ if (err < 0)
- return err;
-- }
-
- return 0;
- }
+++ /dev/null
-From 93b6bd1bf81cffd3e5739478c4434bf25458ec7d Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 5 Jul 2013 14:54:16 +0200
-Subject: [PATCH 038/203] bus: mvebu-mbus: Add new API for window creation
-
-We add an API to create MBus address decoding windows from the target
-ID and attribute. This function will be used later and deprecate the
-current name based scheme.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/bus/mvebu-mbus.c | 33 +++++++++++++++++++++++++--------
- include/linux/mbus.h | 6 ++++++
- 2 files changed, 31 insertions(+), 8 deletions(-)
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -748,6 +748,22 @@ static const struct of_device_id of_mveb
- /*
- * Public API of the driver
- */
-+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
-+ unsigned int attribute,
-+ phys_addr_t base, size_t size,
-+ phys_addr_t remap)
-+{
-+ struct mvebu_mbus_state *s = &mbus_state;
-+
-+ if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
-+ pr_err("cannot add window '%x:%x', conflicts with another window\n",
-+ target, attribute);
-+ return -EINVAL;
-+ }
-+
-+ return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
-+}
-+
- int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
- size_t size, phys_addr_t remap,
- unsigned int flags)
-@@ -776,14 +792,8 @@ int mvebu_mbus_add_window_remap_flags(co
- else if (flags == MVEBU_MBUS_PCI_WA)
- attr |= 0x28;
-
-- if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) {
-- pr_err("cannot add window '%s', conflicts with another window\n",
-- devname);
-- return -EINVAL;
-- }
--
-- return mvebu_mbus_alloc_window(s, base, size, remap, target, attr);
--
-+ return mvebu_mbus_add_window_remap_by_id(target, attr, base,
-+ size, remap);
- }
-
- int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
-@@ -792,6 +802,13 @@ int mvebu_mbus_add_window(const char *de
- MVEBU_MBUS_NO_REMAP, 0);
- }
-
-+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
-+ phys_addr_t base, size_t size)
-+{
-+ return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
-+ size, MVEBU_MBUS_NO_REMAP);
-+}
-+
- int mvebu_mbus_del_window(phys_addr_t base, size_t size)
- {
- int win;
---- a/include/linux/mbus.h
-+++ b/include/linux/mbus.h
-@@ -62,8 +62,14 @@ static inline const struct mbus_dram_tar
- int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
- size_t size, phys_addr_t remap,
- unsigned int flags);
-+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
-+ unsigned int attribute,
-+ phys_addr_t base, size_t size,
-+ phys_addr_t remap);
- int mvebu_mbus_add_window(const char *devname, phys_addr_t base,
- size_t size);
-+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
-+ phys_addr_t base, size_t size);
- int mvebu_mbus_del_window(phys_addr_t base, size_t size);
- int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
- size_t mbus_size, phys_addr_t sdram_phys_base,
+++ /dev/null
-From 5be79ea0d2bcec8c7360cfe3e7a491e5f176fa84 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 21 May 2013 10:44:54 -0300
-Subject: [PATCH 043/203] bus: mvebu-mbus: Factor out initialization details
-
-We introduce a common initialization function mvebu_mbus_common_init()
-that will be used by both legacy and device-tree initialization code.
-This patch is an intermediate step, which will allow to introduce the
-DT binding for this driver in a less intrusive way.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/bus/mvebu-mbus.c | 47 ++++++++++++++++++++++++++++++-----------------
- 1 file changed, 30 insertions(+), 17 deletions(-)
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -847,26 +847,14 @@ static __init int mvebu_mbus_debugfs_ini
- }
- fs_initcall(mvebu_mbus_debugfs_init);
-
--int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
-- size_t mbuswins_size,
-- phys_addr_t sdramwins_phys_base,
-- size_t sdramwins_size)
-+static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
-+ phys_addr_t mbuswins_phys_base,
-+ size_t mbuswins_size,
-+ phys_addr_t sdramwins_phys_base,
-+ size_t sdramwins_size)
- {
-- struct mvebu_mbus_state *mbus = &mbus_state;
-- const struct of_device_id *of_id;
- int win;
-
-- for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
-- if (!strcmp(of_id->compatible, soc))
-- break;
--
-- if (!of_id->compatible) {
-- pr_err("could not find a matching SoC family\n");
-- return -ENODEV;
-- }
--
-- mbus->soc = of_id->data;
--
- mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
- if (!mbus->mbuswins_base)
- return -ENOMEM;
-@@ -887,3 +875,28 @@ int __init mvebu_mbus_init(const char *s
-
- return 0;
- }
-+
-+int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
-+ size_t mbuswins_size,
-+ phys_addr_t sdramwins_phys_base,
-+ size_t sdramwins_size)
-+{
-+ const struct of_device_id *of_id;
-+
-+ for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
-+ if (!strcmp(of_id->compatible, soc))
-+ break;
-+
-+ if (!of_id->compatible) {
-+ pr_err("could not find a matching SoC family\n");
-+ return -ENODEV;
-+ }
-+
-+ mbus_state.soc = of_id->data;
-+
-+ return mvebu_mbus_common_init(&mbus_state,
-+ mbuswins_phys_base,
-+ mbuswins_size,
-+ sdramwins_phys_base,
-+ sdramwins_size);
-+}
+++ /dev/null
-From e4123095febc94c547c0459db752e7879db79d76 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 21 May 2013 10:48:54 -0300
-Subject: [PATCH 044/203] bus: mvebu-mbus: Introduce device tree binding
-
-This patch adds the most fundamental device-tree initialization.
-We only introduce what's required to be able to probe the mvebu-mbus
-driver from the DT. Follow-up patches will extend the device tree binding,
-allowing to describe static address decoding windows.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/bus/mvebu-mbus.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++
- include/linux/mbus.h | 1 +
- 2 files changed, 50 insertions(+)
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -900,3 +900,52 @@ int __init mvebu_mbus_init(const char *s
- sdramwins_phys_base,
- sdramwins_size);
- }
-+
-+#ifdef CONFIG_OF
-+int __init mvebu_mbus_dt_init(void)
-+{
-+ struct resource mbuswins_res, sdramwins_res;
-+ struct device_node *np, *controller;
-+ const struct of_device_id *of_id;
-+ const __be32 *prop;
-+ int ret;
-+
-+ np = of_find_matching_node(NULL, of_mvebu_mbus_ids);
-+ if (!np) {
-+ pr_err("could not find a matching SoC family\n");
-+ return -ENODEV;
-+ }
-+
-+ of_id = of_match_node(of_mvebu_mbus_ids, np);
-+ mbus_state.soc = of_id->data;
-+
-+ prop = of_get_property(np, "controller", NULL);
-+ if (!prop) {
-+ pr_err("required 'controller' property missing\n");
-+ return -EINVAL;
-+ }
-+
-+ controller = of_find_node_by_phandle(be32_to_cpup(prop));
-+ if (!controller) {
-+ pr_err("could not find an 'mbus-controller' node\n");
-+ return -ENODEV;
-+ }
-+
-+ if (of_address_to_resource(controller, 0, &mbuswins_res)) {
-+ pr_err("cannot get MBUS register address\n");
-+ return -EINVAL;
-+ }
-+
-+ if (of_address_to_resource(controller, 1, &sdramwins_res)) {
-+ pr_err("cannot get SDRAM register address\n");
-+ return -EINVAL;
-+ }
-+
-+ ret = mvebu_mbus_common_init(&mbus_state,
-+ mbuswins_res.start,
-+ resource_size(&mbuswins_res),
-+ sdramwins_res.start,
-+ resource_size(&sdramwins_res));
-+ return ret;
-+}
-+#endif
---- a/include/linux/mbus.h
-+++ b/include/linux/mbus.h
-@@ -74,5 +74,6 @@ int mvebu_mbus_del_window(phys_addr_t ba
- int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
- size_t mbus_size, phys_addr_t sdram_phys_base,
- size_t sdram_size);
-+int mvebu_mbus_dt_init(void);
-
- #endif /* __LINUX_MBUS_H */
+++ /dev/null
-From ece28a7e105cedb5a9ebd2553aa41d965fb83b64 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 28 May 2013 07:58:31 -0300
-Subject: [PATCH 045/203] bus: mvebu-mbus: Add static window allocation to the
- DT binding
-
-This patch adds static window allocation to the device tree binding.
-Each first-child of the mbus-compatible node, with a suitable 'ranges'
-property, declaring an address translation, will trigger an address
-decoding window allocation.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/bus/mvebu-mbus.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 126 insertions(+), 1 deletion(-)
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -902,6 +902,127 @@ int __init mvebu_mbus_init(const char *s
- }
-
- #ifdef CONFIG_OF
-+/*
-+ * The window IDs in the ranges DT property have the following format:
-+ * - bits 28 to 31: MBus custom field
-+ * - bits 24 to 27: window target ID
-+ * - bits 16 to 23: window attribute ID
-+ * - bits 0 to 15: unused
-+ */
-+#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
-+#define TARGET(id) (((id) & 0x0F000000) >> 24)
-+#define ATTR(id) (((id) & 0x00FF0000) >> 16)
-+
-+static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
-+ u32 base, u32 size,
-+ u8 target, u8 attr)
-+{
-+ const struct mvebu_mbus_mapping *map = mbus->soc->map;
-+ const char *name;
-+ int i;
-+
-+ /* Search for a suitable window in the existing mappings */
-+ for (i = 0; map[i].name; i++)
-+ if (map[i].target == target &&
-+ map[i].attr == (attr & map[i].attrmask))
-+ break;
-+
-+ name = map[i].name;
-+ if (!name) {
-+ pr_err("window 0x%x:0x%x is unknown, skipping\n",
-+ target, attr);
-+ return -EINVAL;
-+ }
-+
-+ if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
-+ pr_err("cannot add window '%s', conflicts with another window\n",
-+ name);
-+ return -EBUSY;
-+ }
-+
-+ if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
-+ target, attr)) {
-+ pr_err("cannot add window '%s', too many windows\n",
-+ name);
-+ return -ENOMEM;
-+ }
-+ return 0;
-+}
-+
-+static int __init
-+mbus_parse_ranges(struct device_node *node,
-+ int *addr_cells, int *c_addr_cells, int *c_size_cells,
-+ int *cell_count, const __be32 **ranges_start,
-+ const __be32 **ranges_end)
-+{
-+ const __be32 *prop;
-+ int ranges_len, tuple_len;
-+
-+ /* Allow a node with no 'ranges' property */
-+ *ranges_start = of_get_property(node, "ranges", &ranges_len);
-+ if (*ranges_start == NULL) {
-+ *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
-+ *ranges_start = *ranges_end = NULL;
-+ return 0;
-+ }
-+ *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
-+
-+ *addr_cells = of_n_addr_cells(node);
-+
-+ prop = of_get_property(node, "#address-cells", NULL);
-+ *c_addr_cells = be32_to_cpup(prop);
-+
-+ prop = of_get_property(node, "#size-cells", NULL);
-+ *c_size_cells = be32_to_cpup(prop);
-+
-+ *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
-+ tuple_len = (*cell_count) * sizeof(__be32);
-+
-+ if (ranges_len % tuple_len) {
-+ pr_warn("malformed ranges entry '%s'\n", node->name);
-+ return -EINVAL;
-+ }
-+ return 0;
-+}
-+
-+static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
-+ struct device_node *np)
-+{
-+ int addr_cells, c_addr_cells, c_size_cells;
-+ int i, ret, cell_count;
-+ const __be32 *r, *ranges_start, *ranges_end;
-+
-+ ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
-+ &c_size_cells, &cell_count,
-+ &ranges_start, &ranges_end);
-+ if (ret < 0)
-+ return ret;
-+
-+ for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
-+ u32 windowid, base, size;
-+ u8 target, attr;
-+
-+ /*
-+ * An entry with a non-zero custom field do not
-+ * correspond to a static window, so skip it.
-+ */
-+ windowid = of_read_number(r, 1);
-+ if (CUSTOM(windowid))
-+ continue;
-+
-+ target = TARGET(windowid);
-+ attr = ATTR(windowid);
-+
-+ base = of_read_number(r + c_addr_cells, addr_cells);
-+ size = of_read_number(r + c_addr_cells + addr_cells,
-+ c_size_cells);
-+ ret = mbus_dt_setup_win(mbus, base, size, target, attr);
-+ if (ret < 0)
-+ return ret;
-+ }
-+ return 0;
-+}
-+
- int __init mvebu_mbus_dt_init(void)
- {
- struct resource mbuswins_res, sdramwins_res;
-@@ -946,6 +1067,10 @@ int __init mvebu_mbus_dt_init(void)
- resource_size(&mbuswins_res),
- sdramwins_res.start,
- resource_size(&sdramwins_res));
-- return ret;
-+ if (ret)
-+ return ret;
-+
-+ /* Setup statically declared windows in the DT */
-+ return mbus_dt_setup(&mbus_state, np);
- }
- #endif
+++ /dev/null
-From c9646c891dbd07061a9ff5e061f9f9e54c571349 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 9 Jul 2013 10:41:53 -0300
-Subject: [PATCH 046/203] bus: mvebu-mbus: Add new API for the PCIe memory and
- IO aperture
-
-We add two optional properties to the MBus DT binding, to encode
-the PCIe memory and IO aperture. This allows such information to
-be retrieved by -for instance- the pci driver to allocate the
-MBus decoding windows.
-
-Correspondingly, and in order to retrieve this information,
-we add two new APIs.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/bus/mvebu-mbus.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++
- include/linux/mbus.h | 4 ++++
- 2 files changed, 53 insertions(+)
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -142,6 +142,8 @@ struct mvebu_mbus_state {
- struct dentry *debugfs_root;
- struct dentry *debugfs_sdram;
- struct dentry *debugfs_devs;
-+ struct resource pcie_mem_aperture;
-+ struct resource pcie_io_aperture;
- const struct mvebu_mbus_soc_data *soc;
- int hw_io_coherency;
- };
-@@ -821,6 +823,20 @@ int mvebu_mbus_del_window(phys_addr_t ba
- return 0;
- }
-
-+void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
-+{
-+ if (!res)
-+ return;
-+ *res = mbus_state.pcie_mem_aperture;
-+}
-+
-+void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
-+{
-+ if (!res)
-+ return;
-+ *res = mbus_state.pcie_io_aperture;
-+}
-+
- static __init int mvebu_mbus_debugfs_init(void)
- {
- struct mvebu_mbus_state *s = &mbus_state;
-@@ -1023,6 +1039,35 @@ static int __init mbus_dt_setup(struct m
- return 0;
- }
-
-+static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
-+ struct resource *mem,
-+ struct resource *io)
-+{
-+ u32 reg[2];
-+ int ret;
-+
-+ /*
-+ * These are optional, so we clear them and they'll
-+ * be zero if they are missing from the DT.
-+ */
-+ memset(mem, 0, sizeof(struct resource));
-+ memset(io, 0, sizeof(struct resource));
-+
-+ ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
-+ if (!ret) {
-+ mem->start = reg[0];
-+ mem->end = mem->start + reg[1];
-+ mem->flags = IORESOURCE_MEM;
-+ }
-+
-+ ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
-+ if (!ret) {
-+ io->start = reg[0];
-+ io->end = io->start + reg[1];
-+ io->flags = IORESOURCE_IO;
-+ }
-+}
-+
- int __init mvebu_mbus_dt_init(void)
- {
- struct resource mbuswins_res, sdramwins_res;
-@@ -1062,6 +1107,10 @@ int __init mvebu_mbus_dt_init(void)
- return -EINVAL;
- }
-
-+ /* Get optional pcie-{mem,io}-aperture properties */
-+ mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
-+ &mbus_state.pcie_io_aperture);
-+
- ret = mvebu_mbus_common_init(&mbus_state,
- mbuswins_res.start,
- resource_size(&mbuswins_res),
---- a/include/linux/mbus.h
-+++ b/include/linux/mbus.h
-@@ -11,6 +11,8 @@
- #ifndef __LINUX_MBUS_H
- #define __LINUX_MBUS_H
-
-+struct resource;
-+
- struct mbus_dram_target_info
- {
- /*
-@@ -59,6 +61,8 @@ static inline const struct mbus_dram_tar
- }
- #endif
-
-+void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
-+void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
- int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
- size_t size, phys_addr_t remap,
- unsigned int flags);
+++ /dev/null
-From 90b1f963b07d05e8243e5053a910e8a47222f7a1 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 5 Jul 2013 14:54:17 +0200
-Subject: [PATCH 047/203] PCI: mvebu: Adapt to the new device tree layout
-
-The new device tree layout encodes the window's target ID and attribute
-in the PCIe controller node's ranges property. This allows to parse
-such entries to obtain such information and use the recently introduced
-MBus API to create the windows, instead of using the current name based
-scheme.
-
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/pci/host/pci-mvebu.c | 113 ++++++++++++++++++++++++++++++++-----------
- 1 file changed, 84 insertions(+), 29 deletions(-)
-
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -119,6 +119,10 @@ struct mvebu_pcie_port {
- u32 port;
- u32 lane;
- int devfn;
-+ unsigned int mem_target;
-+ unsigned int mem_attr;
-+ unsigned int io_target;
-+ unsigned int io_attr;
- struct clk *clk;
- struct mvebu_sw_pci_bridge bridge;
- struct device_node *dn;
-@@ -303,10 +307,9 @@ static void mvebu_pcie_handle_iobase_cha
- (port->bridge.iolimitupper << 16)) -
- iobase);
-
-- mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
-- port->iowin_size,
-- iobase,
-- MVEBU_MBUS_PCI_IO);
-+ mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
-+ port->iowin_base, port->iowin_size,
-+ iobase);
-
- pci_ioremap_io(iobase, port->iowin_base);
- }
-@@ -338,10 +341,8 @@ static void mvebu_pcie_handle_membase_ch
- (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
- port->memwin_base;
-
-- mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
-- port->memwin_size,
-- MVEBU_MBUS_NO_REMAP,
-- MVEBU_MBUS_PCI_MEM);
-+ mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
-+ port->memwin_base, port->memwin_size);
- }
-
- /*
-@@ -730,12 +731,54 @@ mvebu_pcie_map_registers(struct platform
- return devm_request_and_ioremap(&pdev->dev, ®s);
- }
-
-+#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
-+#define DT_TYPE_IO 0x1
-+#define DT_TYPE_MEM32 0x2
-+#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
-+#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
-+
-+static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
-+ unsigned long type, int *tgt, int *attr)
-+{
-+ const int na = 3, ns = 2;
-+ const __be32 *range;
-+ int rlen, nranges, rangesz, pna, i;
-+
-+ range = of_get_property(np, "ranges", &rlen);
-+ if (!range)
-+ return -EINVAL;
-+
-+ pna = of_n_addr_cells(np);
-+ rangesz = pna + na + ns;
-+ nranges = rlen / sizeof(__be32) / rangesz;
-+
-+ for (i = 0; i < nranges; i++) {
-+ u32 flags = of_read_number(range, 1);
-+ u32 slot = of_read_number(range, 2);
-+ u64 cpuaddr = of_read_number(range + na, pna);
-+ unsigned long rtype;
-+
-+ if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
-+ rtype = IORESOURCE_IO;
-+ else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
-+ rtype = IORESOURCE_MEM;
-+
-+ if (slot == PCI_SLOT(devfn) && type == rtype) {
-+ *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
-+ *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
-+ return 0;
-+ }
-+
-+ range += rangesz;
-+ }
-+
-+ return -ENOENT;
-+}
-+
- static int __init mvebu_pcie_probe(struct platform_device *pdev)
- {
- struct mvebu_pcie *pcie;
- struct device_node *np = pdev->dev.of_node;
-- struct of_pci_range range;
-- struct of_pci_range_parser parser;
- struct device_node *child;
- int i, ret;
-
-@@ -746,29 +789,25 @@ static int __init mvebu_pcie_probe(struc
-
- pcie->pdev = pdev;
-
-- if (of_pci_range_parser_init(&parser, np))
-+ /* Get the PCIe memory and I/O aperture */
-+ mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
-+ if (resource_size(&pcie->mem) == 0) {
-+ dev_err(&pdev->dev, "invalid memory aperture size\n");
- return -EINVAL;
-+ }
-
-- /* Get the I/O and memory ranges from DT */
-- for_each_of_pci_range(&parser, &range) {
-- unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
-- if (restype == IORESOURCE_IO) {
-- of_pci_range_to_resource(&range, np, &pcie->io);
-- of_pci_range_to_resource(&range, np, &pcie->realio);
-- pcie->io.name = "I/O";
-- pcie->realio.start = max_t(resource_size_t,
-- PCIBIOS_MIN_IO,
-- range.pci_addr);
-- pcie->realio.end = min_t(resource_size_t,
-- IO_SPACE_LIMIT,
-- range.pci_addr + range.size);
-- }
-- if (restype == IORESOURCE_MEM) {
-- of_pci_range_to_resource(&range, np, &pcie->mem);
-- pcie->mem.name = "MEM";
-- }
-+ mvebu_mbus_get_pcie_io_aperture(&pcie->io);
-+ if (resource_size(&pcie->io) == 0) {
-+ dev_err(&pdev->dev, "invalid I/O aperture size\n");
-+ return -EINVAL;
- }
-
-+ pcie->realio.flags = pcie->io.flags;
-+ pcie->realio.start = PCIBIOS_MIN_IO;
-+ pcie->realio.end = min_t(resource_size_t,
-+ IO_SPACE_LIMIT,
-+ resource_size(&pcie->io));
-+
- /* Get the bus range */
- ret = of_pci_parse_bus_range(np, &pcie->busn);
- if (ret) {
-@@ -816,6 +855,22 @@ static int __init mvebu_pcie_probe(struc
- if (port->devfn < 0)
- continue;
-
-+ ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
-+ &port->mem_target, &port->mem_attr);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
-+ port->port, port->lane);
-+ continue;
-+ }
-+
-+ ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
-+ &port->io_target, &port->io_attr);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
-+ port->port, port->lane);
-+ continue;
-+ }
-+
- port->base = mvebu_pcie_map_registers(pdev, child, port);
- if (!port->base) {
- dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
+++ /dev/null
-From 3dc077a80c71050e198e7884707ece042443fe3c Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 23 Jul 2013 07:36:00 -0300
-Subject: [PATCH 048/203] PCI: mvebu: Check valid base address before port
- setup
-
-This driver does not fail to probe when it cannot obtain
-a port base address. Therefore, add a check for NULL base address
-before setting up the port, which prevents a kernel panic in such
-cases.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/pci/host/pci-mvebu.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -637,6 +637,8 @@ static int __init mvebu_pcie_setup(int n
-
- for (i = 0; i < pcie->nports; i++) {
- struct mvebu_pcie_port *port = &pcie->ports[i];
-+ if (!port->base)
-+ continue;
- mvebu_pcie_setup_hw(port);
- }
-
+++ /dev/null
-From 1e94a8740cb1f9c328a3ae8ec4727d90bfb2d7f7 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 5 Jul 2013 14:54:23 +0200
-Subject: [PATCH 049/203] bus: mvebu-mbus: Remove the no longer used name-based
- API
-
-Now that every user of the deprecated name-based API has been
-converted to using the ID-based API, let's remove the former one.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/bus/mvebu-mbus.c | 38 --------------------------------------
- include/linux/mbus.h | 5 -----
- 2 files changed, 43 deletions(-)
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -766,44 +766,6 @@ int mvebu_mbus_add_window_remap_by_id(un
- return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
- }
-
--int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
-- size_t size, phys_addr_t remap,
-- unsigned int flags)
--{
-- struct mvebu_mbus_state *s = &mbus_state;
-- u8 target, attr;
-- int i;
--
-- if (!s->soc->map)
-- return -ENODEV;
--
-- for (i = 0; s->soc->map[i].name; i++)
-- if (!strcmp(s->soc->map[i].name, devname))
-- break;
--
-- if (!s->soc->map[i].name) {
-- pr_err("unknown device '%s'\n", devname);
-- return -ENODEV;
-- }
--
-- target = s->soc->map[i].target;
-- attr = s->soc->map[i].attr;
--
-- if (flags == MVEBU_MBUS_PCI_MEM)
-- attr |= 0x8;
-- else if (flags == MVEBU_MBUS_PCI_WA)
-- attr |= 0x28;
--
-- return mvebu_mbus_add_window_remap_by_id(target, attr, base,
-- size, remap);
--}
--
--int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
--{
-- return mvebu_mbus_add_window_remap_flags(devname, base, size,
-- MVEBU_MBUS_NO_REMAP, 0);
--}
--
- int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
- phys_addr_t base, size_t size)
- {
---- a/include/linux/mbus.h
-+++ b/include/linux/mbus.h
-@@ -63,15 +63,10 @@ static inline const struct mbus_dram_tar
-
- void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
- void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
--int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
-- size_t size, phys_addr_t remap,
-- unsigned int flags);
- int mvebu_mbus_add_window_remap_by_id(unsigned int target,
- unsigned int attribute,
- phys_addr_t base, size_t size,
- phys_addr_t remap);
--int mvebu_mbus_add_window(const char *devname, phys_addr_t base,
-- size_t size);
- int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
- phys_addr_t base, size_t size);
- int mvebu_mbus_del_window(phys_addr_t base, size_t size);
+++ /dev/null
-From 08c3b38a75ca47b74c81d14e1715ab9dc7b0e5cb Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 5 Jul 2013 14:54:24 +0200
-Subject: [PATCH 050/203] bus: mvebu-mbus: Remove name -> target, attribute
- mapping tables
-
-This tables were used together with the name-based MBus window
-creation API. Since that's has been removed, we can also remove
-the tables.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/bus/mvebu-mbus.c | 150 +++--------------------------------------------
- 1 file changed, 7 insertions(+), 143 deletions(-)
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -97,33 +97,6 @@
-
- #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
-
--struct mvebu_mbus_mapping {
-- const char *name;
-- u8 target;
-- u8 attr;
-- u8 attrmask;
--};
--
--/*
-- * Masks used for the 'attrmask' field of mvebu_mbus_mapping. They
-- * allow to get the real attribute value, discarding the special bits
-- * used to select a PCI MEM region or a PCI WA region. This allows the
-- * debugfs code to reverse-match the name of a device from its
-- * target/attr values.
-- *
-- * For all devices except PCI, all bits of 'attr' must be
-- * considered. For most SoCs, only bit 3 should be ignored (it allows
-- * to select between PCI MEM and PCI I/O). On Orion5x however, there
-- * is the special bit 5 to select a PCI WA region.
-- */
--#define MAPDEF_NOMASK 0xff
--#define MAPDEF_PCIMASK 0xf7
--#define MAPDEF_ORIONPCIMASK 0xd7
--
--/* Macro used to define one mvebu_mbus_mapping entry */
--#define MAPDEF(__n, __t, __a, __m) \
-- { .name = __n, .target = __t, .attr = __a, .attrmask = __m }
--
- struct mvebu_mbus_state;
-
- struct mvebu_mbus_soc_data {
-@@ -133,7 +106,6 @@ struct mvebu_mbus_soc_data {
- void (*setup_cpu_target)(struct mvebu_mbus_state *s);
- int (*show_cpu_target)(struct mvebu_mbus_state *s,
- struct seq_file *seq, void *v);
-- const struct mvebu_mbus_mapping *map;
- };
-
- struct mvebu_mbus_state {
-@@ -430,8 +402,7 @@ static int mvebu_devs_debug_show(struct
- u64 wbase, wremap;
- u32 wsize;
- u8 wtarget, wattr;
-- int enabled, i;
-- const char *name;
-+ int enabled;
-
- mvebu_mbus_read_window(mbus, win,
- &enabled, &wbase, &wsize,
-@@ -442,18 +413,9 @@ static int mvebu_devs_debug_show(struct
- continue;
- }
-
--
-- for (i = 0; mbus->soc->map[i].name; i++)
-- if (mbus->soc->map[i].target == wtarget &&
-- mbus->soc->map[i].attr ==
-- (wattr & mbus->soc->map[i].attrmask))
-- break;
--
-- name = mbus->soc->map[i].name ?: "unknown";
--
-- seq_printf(seq, "[%02d] %016llx - %016llx : %s",
-+ seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
- win, (unsigned long long)wbase,
-- (unsigned long long)(wbase + wsize), name);
-+ (unsigned long long)(wbase + wsize), wtarget, wattr);
-
- if (win < mbus->soc->num_remappable_wins) {
- seq_printf(seq, " (remap %016llx)\n",
-@@ -578,45 +540,12 @@ mvebu_mbus_dove_setup_cpu_target(struct
- mvebu_mbus_dram_info.num_cs = cs;
- }
-
--static const struct mvebu_mbus_mapping armada_370_map[] = {
-- MAPDEF("bootrom", 1, 0xe0, MAPDEF_NOMASK),
-- MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
-- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
-- {},
--};
--
- static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
- .num_wins = 20,
- .num_remappable_wins = 8,
- .win_cfg_offset = armada_370_xp_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
- .show_cpu_target = mvebu_sdram_debug_show_orion,
-- .map = armada_370_map,
--};
--
--static const struct mvebu_mbus_mapping armada_xp_map[] = {
-- MAPDEF("bootrom", 1, 0x1d, MAPDEF_NOMASK),
-- MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
-- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
-- MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
-- MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
-- MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
-- MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
-- MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
-- {},
- };
-
- static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
-@@ -625,15 +554,6 @@ static const struct mvebu_mbus_soc_data
- .win_cfg_offset = armada_370_xp_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
- .show_cpu_target = mvebu_sdram_debug_show_orion,
-- .map = armada_xp_map,
--};
--
--static const struct mvebu_mbus_mapping kirkwood_map[] = {
-- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK),
-- MAPDEF("sram", 3, 0x01, MAPDEF_NOMASK),
-- MAPDEF("nand", 1, 0x2f, MAPDEF_NOMASK),
-- {},
- };
-
- static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
-@@ -642,16 +562,6 @@ static const struct mvebu_mbus_soc_data
- .win_cfg_offset = orion_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
- .show_cpu_target = mvebu_sdram_debug_show_orion,
-- .map = kirkwood_map,
--};
--
--static const struct mvebu_mbus_mapping dove_map[] = {
-- MAPDEF("pcie0.0", 0x4, 0xe0, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.0", 0x8, 0xe0, MAPDEF_PCIMASK),
-- MAPDEF("cesa", 0x3, 0x01, MAPDEF_NOMASK),
-- MAPDEF("bootrom", 0x1, 0xfd, MAPDEF_NOMASK),
-- MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK),
-- {},
- };
-
- static const struct mvebu_mbus_soc_data dove_mbus_data = {
-@@ -660,18 +570,6 @@ static const struct mvebu_mbus_soc_data
- .win_cfg_offset = orion_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
- .show_cpu_target = mvebu_sdram_debug_show_dove,
-- .map = dove_map,
--};
--
--static const struct mvebu_mbus_mapping orion5x_map[] = {
-- MAPDEF("pcie0.0", 4, 0x51, MAPDEF_ORIONPCIMASK),
-- MAPDEF("pci0.0", 3, 0x51, MAPDEF_ORIONPCIMASK),
-- MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs0", 1, 0x1e, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs1", 1, 0x1d, MAPDEF_NOMASK),
-- MAPDEF("devbus-cs2", 1, 0x1b, MAPDEF_NOMASK),
-- MAPDEF("sram", 0, 0x00, MAPDEF_NOMASK),
-- {},
- };
-
- /*
-@@ -684,7 +582,6 @@ static const struct mvebu_mbus_soc_data
- .win_cfg_offset = orion_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
- .show_cpu_target = mvebu_sdram_debug_show_orion,
-- .map = orion5x_map,
- };
-
- static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
-@@ -693,21 +590,6 @@ static const struct mvebu_mbus_soc_data
- .win_cfg_offset = orion_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
- .show_cpu_target = mvebu_sdram_debug_show_orion,
-- .map = orion5x_map,
--};
--
--static const struct mvebu_mbus_mapping mv78xx0_map[] = {
-- MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
-- MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
-- MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
-- MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
-- MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
-- MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
-- MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
-- {},
- };
-
- static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
-@@ -716,7 +598,6 @@ static const struct mvebu_mbus_soc_data
- .win_cfg_offset = mv78xx0_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
- .show_cpu_target = mvebu_sdram_debug_show_orion,
-- .map = mv78xx0_map,
- };
-
- /*
-@@ -895,33 +776,16 @@ static int __init mbus_dt_setup_win(stru
- u32 base, u32 size,
- u8 target, u8 attr)
- {
-- const struct mvebu_mbus_mapping *map = mbus->soc->map;
-- const char *name;
-- int i;
--
-- /* Search for a suitable window in the existing mappings */
-- for (i = 0; map[i].name; i++)
-- if (map[i].target == target &&
-- map[i].attr == (attr & map[i].attrmask))
-- break;
--
-- name = map[i].name;
-- if (!name) {
-- pr_err("window 0x%x:0x%x is unknown, skipping\n",
-- target, attr);
-- return -EINVAL;
-- }
--
- if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
-- pr_err("cannot add window '%s', conflicts with another window\n",
-- name);
-+ pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
-+ target, attr);
- return -EBUSY;
- }
-
- if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
- target, attr)) {
-- pr_err("cannot add window '%s', too many windows\n",
-- name);
-+ pr_err("cannot add window '%04x:%04x', too many windows\n",
-+ target, attr);
- return -ENOMEM;
- }
- return 0;
+++ /dev/null
-From 8f14bc2a883316dfd95383900c61d7d9183e8eaf Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 5 Jul 2013 14:54:25 +0200
-Subject: [PATCH 051/203] bus: mvebu-mbus: Update main description
-
-After replacing the MBus name-based by the new ID-based API
-let's fix the general description of the driver at the beginning
-of the file.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/bus/mvebu-mbus.c | 10 +++-------
- 1 file changed, 3 insertions(+), 7 deletions(-)
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -35,13 +35,9 @@
- *
- * - Provides an API for platform code or device drivers to
- * dynamically add or remove address decoding windows for the CPU ->
-- * device accesses. This API is mvebu_mbus_add_window(),
-- * mvebu_mbus_add_window_remap_flags() and
-- * mvebu_mbus_del_window(). Since the (target, attribute) values
-- * differ from one SoC family to another, the API uses a 'const char
-- * *' string to identify devices, and this driver is responsible for
-- * knowing the mapping between the name of a device and its
-- * corresponding (target, attribute) in the current SoC family.
-+ * device accesses. This API is mvebu_mbus_add_window_by_id(),
-+ * mvebu_mbus_add_window_remap_by_id() and
-+ * mvebu_mbus_del_window().
- *
- * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
- * see the list of CPU -> SDRAM windows and their configuration
+++ /dev/null
-From 2c8f0b1810ff9cd45ed2055441b4c43afcfb7d2a Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 5 Jul 2013 14:54:26 +0200
-Subject: [PATCH 052/203] bus: mvebu-mbus: Factorize Armada 370/XP data
- structures
-
-These structures were only different in the mapping tables.
-Now that those tables have been removed, it doesn't make any sense
-to keep different structures.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- drivers/bus/mvebu-mbus.c | 14 +++-----------
- 1 file changed, 3 insertions(+), 11 deletions(-)
-
---- a/drivers/bus/mvebu-mbus.c
-+++ b/drivers/bus/mvebu-mbus.c
-@@ -536,15 +536,7 @@ mvebu_mbus_dove_setup_cpu_target(struct
- mvebu_mbus_dram_info.num_cs = cs;
- }
-
--static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
-- .num_wins = 20,
-- .num_remappable_wins = 8,
-- .win_cfg_offset = armada_370_xp_mbus_win_offset,
-- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
-- .show_cpu_target = mvebu_sdram_debug_show_orion,
--};
--
--static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
-+static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
- .num_wins = 20,
- .num_remappable_wins = 8,
- .win_cfg_offset = armada_370_xp_mbus_win_offset,
-@@ -604,9 +596,9 @@ static const struct mvebu_mbus_soc_data
- */
- static const struct of_device_id of_mvebu_mbus_ids[] = {
- { .compatible = "marvell,armada370-mbus",
-- .data = &armada_370_mbus_data, },
-+ .data = &armada_370_xp_mbus_data, },
- { .compatible = "marvell,armadaxp-mbus",
-- .data = &armada_xp_mbus_data, },
-+ .data = &armada_370_xp_mbus_data, },
- { .compatible = "marvell,kirkwood-mbus",
- .data = &kirkwood_mbus_data, },
- { .compatible = "marvell,dove-mbus",
+++ /dev/null
-From 23a9b291a7b9ba28b31da56e6ced7a8168baa3de Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 21 May 2013 11:01:33 -0300
-Subject: [PATCH 053/203] ARM: mvebu: Remove the harcoded BootROM window
- allocation
-
-The address decoding window to access the BootROM should not be
-allocated programatically, but instead declared in the device tree.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/mach-mvebu/platsmp.c | 25 ++++++++++++++++++++++++-
- 1 file changed, 24 insertions(+), 1 deletion(-)
-
---- a/arch/arm/mach-mvebu/platsmp.c
-+++ b/arch/arm/mach-mvebu/platsmp.c
-@@ -21,6 +21,7 @@
- #include <linux/smp.h>
- #include <linux/clk.h>
- #include <linux/of.h>
-+#include <linux/of_address.h>
- #include <linux/mbus.h>
- #include <asm/cacheflush.h>
- #include <asm/smp_plat.h>
-@@ -29,6 +30,9 @@
- #include "pmsu.h"
- #include "coherency.h"
-
-+#define AXP_BOOTROM_BASE 0xfff00000
-+#define AXP_BOOTROM_SIZE 0x100000
-+
- void __init set_secondary_cpus_clock(void)
- {
- int thiscpu;
-@@ -115,10 +119,29 @@ static void __init armada_xp_smp_init_cp
-
- void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
- {
-+ struct device_node *node;
-+ struct resource res;
-+ int err;
-+
- set_secondary_cpus_clock();
- flush_cache_all();
- set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
-- mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
-+
-+ /*
-+ * In order to boot the secondary CPUs we need to ensure
-+ * the bootROM is mapped at the correct address.
-+ */
-+ node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
-+ if (!node)
-+ panic("Cannot find 'marvell,bootrom' compatible node");
-+
-+ err = of_address_to_resource(node, 0, &res);
-+ if (err < 0)
-+ panic("Cannot get 'bootrom' node address");
-+
-+ if (res.start != AXP_BOOTROM_BASE ||
-+ resource_size(&res) != AXP_BOOTROM_SIZE)
-+ panic("The address for the BootROM is incorrect");
- }
-
- struct smp_operations armada_xp_smp_ops __initdata = {
+++ /dev/null
-From 08fe0e166c06fd86d6c8eed145d6508c3e5efaac Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 21 May 2013 11:12:00 -0300
-Subject: [PATCH 054/203] ARM: mvebu: Initialize MBus using the DT binding
-
-Now that the mbus device tree binding has been introduced, we can
-switch over to it.
-
-Also, and since the initialization of the mbus driver is quite
-fundamental for the system to work properly, this patch adds a BUG()
-in case mbus fails to initialize.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/mach-mvebu/armada-370-xp.c | 34 +---------------------------------
- 1 file changed, 1 insertion(+), 33 deletions(-)
-
---- a/arch/arm/mach-mvebu/armada-370-xp.c
-+++ b/arch/arm/mach-mvebu/armada-370-xp.c
-@@ -35,44 +35,12 @@ static void __init armada_370_xp_map_io(
- debug_ll_io_init();
- }
-
--/*
-- * This initialization will be replaced by a DT-based
-- * initialization once the mvebu-mbus driver gains DT support.
-- */
--
--#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000
--#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
--#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180
--#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
--
--static void __init armada_370_xp_mbus_init(void)
--{
-- char *mbus_soc_name;
-- struct device_node *dn;
-- const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
-- const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
--
-- if (of_machine_is_compatible("marvell,armada370"))
-- mbus_soc_name = "marvell,armada370-mbus";
-- else
-- mbus_soc_name = "marvell,armadaxp-mbus";
--
-- dn = of_find_node_by_name(NULL, "internal-regs");
-- BUG_ON(!dn);
--
-- mvebu_mbus_init(mbus_soc_name,
-- of_translate_address(dn, &mbus_wins_offs),
-- ARMADA_370_XP_MBUS_WINS_SIZE,
-- of_translate_address(dn, &sdram_wins_offs),
-- ARMADA_370_XP_SDRAM_WINS_SIZE);
--}
--
- static void __init armada_370_xp_timer_and_clk_init(void)
- {
- mvebu_clocks_init();
- armada_370_xp_timer_init();
- coherency_init();
-- armada_370_xp_mbus_init();
-+ BUG_ON(mvebu_mbus_dt_init());
- #ifdef CONFIG_CACHE_L2X0
- l2x0_of_init(0, ~0UL);
- #endif
+++ /dev/null
-From 09aa74a11d05763043b1925628f65a5ac0d42237 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 12 Jun 2013 15:42:00 -0300
-Subject: [PATCH 055/203] ARM: mvebu: Use the preprocessor on Armada 370/XP
- device tree files
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/boot/dts/armada-370-db.dts | 2 +-
- arch/arm/boot/dts/armada-370-mirabox.dts | 2 +-
- arch/arm/boot/dts/armada-370-rd.dts | 2 +-
- arch/arm/boot/dts/armada-370.dtsi | 2 +-
- arch/arm/boot/dts/armada-xp-db.dts | 2 +-
- arch/arm/boot/dts/armada-xp-gp.dts | 2 +-
- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 2 +-
- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 2 +-
- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 2 +-
- arch/arm/boot/dts/armada-xp.dtsi | 2 +-
- 10 files changed, 10 insertions(+), 10 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370-db.dts
-+++ b/arch/arm/boot/dts/armada-370-db.dts
-@@ -14,7 +14,7 @@
- */
-
- /dts-v1/;
--/include/ "armada-370.dtsi"
-+#include "armada-370.dtsi"
-
- / {
- model = "Marvell Armada 370 Evaluation Board";
---- a/arch/arm/boot/dts/armada-370-mirabox.dts
-+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
-@@ -9,7 +9,7 @@
- */
-
- /dts-v1/;
--/include/ "armada-370.dtsi"
-+#include "armada-370.dtsi"
-
- / {
- model = "Globalscale Mirabox";
---- a/arch/arm/boot/dts/armada-370-rd.dts
-+++ b/arch/arm/boot/dts/armada-370-rd.dts
-@@ -12,7 +12,7 @@
- */
-
- /dts-v1/;
--/include/ "armada-370.dtsi"
-+#include "armada-370.dtsi"
-
- / {
- model = "Marvell Armada 370 Reference Design";
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -15,7 +15,7 @@
- * common to all Armada SoCs.
- */
-
--/include/ "armada-370-xp.dtsi"
-+#include "armada-370-xp.dtsi"
- /include/ "skeleton.dtsi"
-
- / {
---- a/arch/arm/boot/dts/armada-xp-db.dts
-+++ b/arch/arm/boot/dts/armada-xp-db.dts
-@@ -14,7 +14,7 @@
- */
-
- /dts-v1/;
--/include/ "armada-xp-mv78460.dtsi"
-+#include "armada-xp-mv78460.dtsi"
-
- / {
- model = "Marvell Armada XP Evaluation Board";
---- a/arch/arm/boot/dts/armada-xp-gp.dts
-+++ b/arch/arm/boot/dts/armada-xp-gp.dts
-@@ -14,7 +14,7 @@
- */
-
- /dts-v1/;
--/include/ "armada-xp-mv78460.dtsi"
-+#include "armada-xp-mv78460.dtsi"
-
- / {
- model = "Marvell Armada XP Development Board DB-MV784MP-GP";
---- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-@@ -13,7 +13,7 @@
- * common to all Armada XP SoCs.
- */
-
--/include/ "armada-xp.dtsi"
-+#include "armada-xp.dtsi"
-
- / {
- model = "Marvell Armada XP MV78260 SoC";
---- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-@@ -13,7 +13,7 @@
- * common to all Armada XP SoCs.
- */
-
--/include/ "armada-xp.dtsi"
-+#include "armada-xp.dtsi"
-
- / {
- model = "Marvell Armada XP MV78460 SoC";
---- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
-+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
-@@ -11,7 +11,7 @@
- */
-
- /dts-v1/;
--/include/ "armada-xp-mv78260.dtsi"
-+#include "armada-xp-mv78260.dtsi"
-
- / {
- model = "PlatHome OpenBlocks AX3-4 board";
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -16,7 +16,7 @@
- * common to all Armada SoCs.
- */
-
--/include/ "armada-370-xp.dtsi"
-+#include "armada-370-xp.dtsi"
-
- / {
- model = "Marvell Armada XP family SoC";
+++ /dev/null
-From 8298866bfa7fe9c1e33055322c415f612c16a477 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 28 May 2013 08:56:04 -0300
-Subject: [PATCH 056/203] ARM: mvebu: Add MBus to Armada 370/XP device tree
-
-The Armada 370/XP SoC family has a completely configurable address
-space handled by the MBus controller.
-
-This patch introduces the device tree layout of MBus, making the
-'soc' node as mbus-compatible.
-Since every peripheral/controller is a child of this 'soc' node,
-this makes all of them sit behind the mbus, thus describing the
-hardware accurately.
-
-A translation entry has been added for the internal-regs mapping.
-This can't be done in the common armada-370-xp.dtsi because A370
-and AXP have different addressing width.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/boot/dts/armada-370-db.dts | 2 ++
- arch/arm/boot/dts/armada-370-mirabox.dts | 2 ++
- arch/arm/boot/dts/armada-370-rd.dts | 2 ++
- arch/arm/boot/dts/armada-370-xp.dtsi | 15 ++++++++++-----
- arch/arm/boot/dts/armada-370.dtsi | 4 ++--
- arch/arm/boot/dts/armada-xp-db.dts | 4 +---
- arch/arm/boot/dts/armada-xp-gp.dts | 4 +---
- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 4 +---
- arch/arm/boot/dts/armada-xp.dtsi | 2 ++
- 9 files changed, 23 insertions(+), 16 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370-db.dts
-+++ b/arch/arm/boot/dts/armada-370-db.dts
-@@ -30,6 +30,8 @@
- };
-
- soc {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
-+
- internal-regs {
- serial@12000 {
- clock-frequency = <200000000>;
---- a/arch/arm/boot/dts/armada-370-mirabox.dts
-+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
-@@ -25,6 +25,8 @@
- };
-
- soc {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
-+
- internal-regs {
- serial@12000 {
- clock-frequency = <200000000>;
---- a/arch/arm/boot/dts/armada-370-rd.dts
-+++ b/arch/arm/boot/dts/armada-370-rd.dts
-@@ -28,6 +28,8 @@
- };
-
- soc {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
-+
- internal-regs {
- serial@12000 {
- clock-frequency = <200000000>;
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -18,6 +18,8 @@
-
- /include/ "skeleton64.dtsi"
-
-+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
-+
- / {
- model = "Marvell Armada 370 and XP SoC";
- compatible = "marvell,armada-370-xp";
-@@ -29,18 +31,21 @@
- };
-
- soc {
-- #address-cells = <1>;
-+ #address-cells = <2>;
- #size-cells = <1>;
-- compatible = "simple-bus";
-+ controller = <&mbusc>;
- interrupt-parent = <&mpic>;
-- ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
-- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
-
- internal-regs {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
-- ranges;
-+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
-+
-+ mbusc: mbus-controller@20000 {
-+ compatible = "marvell,mbus-controller";
-+ reg = <0x20000 0x100>, <0x20180 0x20>;
-+ };
-
- mpic: interrupt-controller@20000 {
- compatible = "marvell,mpic";
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -29,8 +29,8 @@
- };
-
- soc {
-- ranges = <0 0xd0000000 0x0100000 /* internal registers */
-- 0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
-+ compatible = "marvell,armada370-mbus", "simple-bus";
-+
- internal-regs {
- system-controller@18200 {
- compatible = "marvell,armada-370-xp-system-controller";
---- a/arch/arm/boot/dts/armada-xp-db.dts
-+++ b/arch/arm/boot/dts/armada-xp-db.dts
-@@ -30,9 +30,7 @@
- };
-
- soc {
-- ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
-- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
-- 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
-
- internal-regs {
- serial@12000 {
---- a/arch/arm/boot/dts/armada-xp-gp.dts
-+++ b/arch/arm/boot/dts/armada-xp-gp.dts
-@@ -39,9 +39,7 @@
- };
-
- soc {
-- ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
-- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
-- 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>;
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
-
- internal-regs {
- serial@12000 {
---- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
-+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
-@@ -27,9 +27,7 @@
- };
-
- soc {
-- ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
-- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
-- 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>;
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
-
- internal-regs {
- serial@12000 {
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -23,6 +23,8 @@
- compatible = "marvell,armadaxp", "marvell,armada-370-xp";
-
- soc {
-+ compatible = "marvell,armadaxp-mbus", "simple-bus";
-+
- internal-regs {
- L2: l2-cache {
- compatible = "marvell,aurora-system-cache";
+++ /dev/null
-From 1028055490cf9d6e146f57d920e8cfff4eda37e2 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Fri, 14 Jun 2013 10:34:45 -0300
-Subject: [PATCH 057/203] ARM: mvebu: Add BootROM to Armada 370/XP device tree
-
-In order to access the SoC BootROM, we need to declare a mapping
-(through a ranges property). The mbus driver will use this property
-to allocate a suitable address decoding window.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/boot/dts/armada-370-db.dts | 3 ++-
- arch/arm/boot/dts/armada-370-mirabox.dts | 3 ++-
- arch/arm/boot/dts/armada-370-rd.dts | 3 ++-
- arch/arm/boot/dts/armada-370.dtsi | 5 +++++
- arch/arm/boot/dts/armada-xp-db.dts | 3 ++-
- arch/arm/boot/dts/armada-xp-gp.dts | 3 ++-
- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 3 ++-
- arch/arm/boot/dts/armada-xp.dtsi | 5 +++++
- 8 files changed, 22 insertions(+), 6 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370-db.dts
-+++ b/arch/arm/boot/dts/armada-370-db.dts
-@@ -30,7 +30,8 @@
- };
-
- soc {
-- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
-+ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
-
- internal-regs {
- serial@12000 {
---- a/arch/arm/boot/dts/armada-370-mirabox.dts
-+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
-@@ -25,7 +25,8 @@
- };
-
- soc {
-- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
-+ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
-
- internal-regs {
- serial@12000 {
---- a/arch/arm/boot/dts/armada-370-rd.dts
-+++ b/arch/arm/boot/dts/armada-370-rd.dts
-@@ -28,7 +28,8 @@
- };
-
- soc {
-- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
-+ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
-
- internal-regs {
- serial@12000 {
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -31,6 +31,11 @@
- soc {
- compatible = "marvell,armada370-mbus", "simple-bus";
-
-+ bootrom {
-+ compatible = "marvell,bootrom";
-+ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
-+ };
-+
- internal-regs {
- system-controller@18200 {
- compatible = "marvell,armada-370-xp-system-controller";
---- a/arch/arm/boot/dts/armada-xp-db.dts
-+++ b/arch/arm/boot/dts/armada-xp-db.dts
-@@ -30,7 +30,8 @@
- };
-
- soc {
-- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
-
- internal-regs {
- serial@12000 {
---- a/arch/arm/boot/dts/armada-xp-gp.dts
-+++ b/arch/arm/boot/dts/armada-xp-gp.dts
-@@ -39,7 +39,8 @@
- };
-
- soc {
-- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
-
- internal-regs {
- serial@12000 {
---- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
-+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
-@@ -27,7 +27,8 @@
- };
-
- soc {
-- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
-
- internal-regs {
- serial@12000 {
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -25,6 +25,11 @@
- soc {
- compatible = "marvell,armadaxp-mbus", "simple-bus";
-
-+ bootrom {
-+ compatible = "marvell,bootrom";
-+ reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
-+ };
-+
- internal-regs {
- L2: l2-cache {
- compatible = "marvell,aurora-system-cache";
+++ /dev/null
-From bcb0e54d62804f1f986ad478a11235dadb1b61bb Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Fri, 14 Jun 2013 10:44:57 -0300
-Subject: [PATCH 058/203] ARM: mvebu: Relocate Armada 370/XP DeviceBus device
- tree nodes
-
-Now that mbus has been added to the device tree, it's possible to
-move the DeviceBus out of internal registers, placing it directly
-below the mbus. This is a more accurate representation of the hardware.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/boot/dts/armada-370-xp.dtsi | 94 +++++++++++++-----------
- arch/arm/boot/dts/armada-xp-db.dts | 59 +++++++--------
- arch/arm/boot/dts/armada-xp-gp.dts | 60 +++++++--------
- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 60 +++++++--------
- 4 files changed, 140 insertions(+), 133 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -36,6 +36,56 @@
- controller = <&mbusc>;
- interrupt-parent = <&mpic>;
-
-+ devbus-bootcs {
-+ compatible = "marvell,mvebu-devbus";
-+ reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
-+ ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ clocks = <&coreclk 0>;
-+ status = "disabled";
-+ };
-+
-+ devbus-cs0 {
-+ compatible = "marvell,mvebu-devbus";
-+ reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
-+ ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ clocks = <&coreclk 0>;
-+ status = "disabled";
-+ };
-+
-+ devbus-cs1 {
-+ compatible = "marvell,mvebu-devbus";
-+ reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
-+ ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ clocks = <&coreclk 0>;
-+ status = "disabled";
-+ };
-+
-+ devbus-cs2 {
-+ compatible = "marvell,mvebu-devbus";
-+ reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
-+ ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ clocks = <&coreclk 0>;
-+ status = "disabled";
-+ };
-+
-+ devbus-cs3 {
-+ compatible = "marvell,mvebu-devbus";
-+ reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
-+ ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ clocks = <&coreclk 0>;
-+ status = "disabled";
-+ };
-+
- internal-regs {
- compatible = "simple-bus";
- #address-cells = <1>;
-@@ -191,50 +241,6 @@
- status = "disabled";
- };
-
-- devbus-bootcs@10400 {
-- compatible = "marvell,mvebu-devbus";
-- reg = <0x10400 0x8>;
-- #address-cells = <1>;
-- #size-cells = <1>;
-- clocks = <&coreclk 0>;
-- status = "disabled";
-- };
--
-- devbus-cs0@10408 {
-- compatible = "marvell,mvebu-devbus";
-- reg = <0x10408 0x8>;
-- #address-cells = <1>;
-- #size-cells = <1>;
-- clocks = <&coreclk 0>;
-- status = "disabled";
-- };
--
-- devbus-cs1@10410 {
-- compatible = "marvell,mvebu-devbus";
-- reg = <0x10410 0x8>;
-- #address-cells = <1>;
-- #size-cells = <1>;
-- clocks = <&coreclk 0>;
-- status = "disabled";
-- };
--
-- devbus-cs2@10418 {
-- compatible = "marvell,mvebu-devbus";
-- reg = <0x10418 0x8>;
-- #address-cells = <1>;
-- #size-cells = <1>;
-- clocks = <&coreclk 0>;
-- status = "disabled";
-- };
--
-- devbus-cs3@10420 {
-- compatible = "marvell,mvebu-devbus";
-- reg = <0x10420 0x8>;
-- #address-cells = <1>;
-- #size-cells = <1>;
-- clocks = <&coreclk 0>;
-- status = "disabled";
-- };
- };
- };
- };
---- a/arch/arm/boot/dts/armada-xp-db.dts
-+++ b/arch/arm/boot/dts/armada-xp-db.dts
-@@ -31,7 +31,36 @@
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
-- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
-+
-+ devbus-bootcs {
-+ status = "okay";
-+
-+ /* Device Bus parameters are required */
-+
-+ /* Read parameters */
-+ devbus,bus-width = <8>;
-+ devbus,turn-off-ps = <60000>;
-+ devbus,badr-skew-ps = <0>;
-+ devbus,acc-first-ps = <124000>;
-+ devbus,acc-next-ps = <248000>;
-+ devbus,rd-setup-ps = <0>;
-+ devbus,rd-hold-ps = <0>;
-+
-+ /* Write parameters */
-+ devbus,sync-enable = <0>;
-+ devbus,wr-high-ps = <60000>;
-+ devbus,wr-low-ps = <60000>;
-+ devbus,ale-wr-ps = <60000>;
-+
-+ /* NOR 16 MiB */
-+ nor@0 {
-+ compatible = "cfi-flash";
-+ reg = <0 0x1000000>;
-+ bank-width = <2>;
-+ };
-+ };
-
- internal-regs {
- serial@12000 {
-@@ -160,34 +189,6 @@
- };
- };
-
-- devbus-bootcs@10400 {
-- status = "okay";
-- ranges = <0 0xf0000000 0x1000000>;
--
-- /* Device Bus parameters are required */
--
-- /* Read parameters */
-- devbus,bus-width = <8>;
-- devbus,turn-off-ps = <60000>;
-- devbus,badr-skew-ps = <0>;
-- devbus,acc-first-ps = <124000>;
-- devbus,acc-next-ps = <248000>;
-- devbus,rd-setup-ps = <0>;
-- devbus,rd-hold-ps = <0>;
--
-- /* Write parameters */
-- devbus,sync-enable = <0>;
-- devbus,wr-high-ps = <60000>;
-- devbus,wr-low-ps = <60000>;
-- devbus,ale-wr-ps = <60000>;
--
-- /* NOR 16 MiB */
-- nor@0 {
-- compatible = "cfi-flash";
-- reg = <0 0x1000000>;
-- bank-width = <2>;
-- };
-- };
- };
- };
- };
---- a/arch/arm/boot/dts/armada-xp-gp.dts
-+++ b/arch/arm/boot/dts/armada-xp-gp.dts
-@@ -40,7 +40,36 @@
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
-- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
-+
-+ devbus-bootcs {
-+ status = "okay";
-+
-+ /* Device Bus parameters are required */
-+
-+ /* Read parameters */
-+ devbus,bus-width = <8>;
-+ devbus,turn-off-ps = <60000>;
-+ devbus,badr-skew-ps = <0>;
-+ devbus,acc-first-ps = <124000>;
-+ devbus,acc-next-ps = <248000>;
-+ devbus,rd-setup-ps = <0>;
-+ devbus,rd-hold-ps = <0>;
-+
-+ /* Write parameters */
-+ devbus,sync-enable = <0>;
-+ devbus,wr-high-ps = <60000>;
-+ devbus,wr-low-ps = <60000>;
-+ devbus,ale-wr-ps = <60000>;
-+
-+ /* NOR 16 MiB */
-+ nor@0 {
-+ compatible = "cfi-flash";
-+ reg = <0 0x1000000>;
-+ bank-width = <2>;
-+ };
-+ };
-
- internal-regs {
- serial@12000 {
-@@ -126,35 +155,6 @@
- };
- };
-
-- devbus-bootcs@10400 {
-- status = "okay";
-- ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
--
-- /* Device Bus parameters are required */
--
-- /* Read parameters */
-- devbus,bus-width = <8>;
-- devbus,turn-off-ps = <60000>;
-- devbus,badr-skew-ps = <0>;
-- devbus,acc-first-ps = <124000>;
-- devbus,acc-next-ps = <248000>;
-- devbus,rd-setup-ps = <0>;
-- devbus,rd-hold-ps = <0>;
--
-- /* Write parameters */
-- devbus,sync-enable = <0>;
-- devbus,wr-high-ps = <60000>;
-- devbus,wr-low-ps = <60000>;
-- devbus,ale-wr-ps = <60000>;
--
-- /* NOR 16 MiB */
-- nor@0 {
-- compatible = "cfi-flash";
-- reg = <0 0x1000000>;
-- bank-width = <2>;
-- };
-- };
--
- pcie-controller {
- status = "okay";
-
---- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
-+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
-@@ -28,7 +28,36 @@
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
-- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
-+
-+ devbus-bootcs {
-+ status = "okay";
-+
-+ /* Device Bus parameters are required */
-+
-+ /* Read parameters */
-+ devbus,bus-width = <8>;
-+ devbus,turn-off-ps = <60000>;
-+ devbus,badr-skew-ps = <0>;
-+ devbus,acc-first-ps = <124000>;
-+ devbus,acc-next-ps = <248000>;
-+ devbus,rd-setup-ps = <0>;
-+ devbus,rd-hold-ps = <0>;
-+
-+ /* Write parameters */
-+ devbus,sync-enable = <0>;
-+ devbus,wr-high-ps = <60000>;
-+ devbus,wr-low-ps = <60000>;
-+ devbus,ale-wr-ps = <60000>;
-+
-+ /* NOR 128 MiB */
-+ nor@0 {
-+ compatible = "cfi-flash";
-+ reg = <0 0x8000000>;
-+ bank-width = <2>;
-+ };
-+ };
-
- internal-regs {
- serial@12000 {
-@@ -144,35 +173,6 @@
- status = "okay";
- };
-
-- devbus-bootcs@10400 {
-- status = "okay";
-- ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
--
-- /* Device Bus parameters are required */
--
-- /* Read parameters */
-- devbus,bus-width = <8>;
-- devbus,turn-off-ps = <60000>;
-- devbus,badr-skew-ps = <0>;
-- devbus,acc-first-ps = <124000>;
-- devbus,acc-next-ps = <248000>;
-- devbus,rd-setup-ps = <0>;
-- devbus,rd-hold-ps = <0>;
--
-- /* Write parameters */
-- devbus,sync-enable = <0>;
-- devbus,wr-high-ps = <60000>;
-- devbus,wr-low-ps = <60000>;
-- devbus,ale-wr-ps = <60000>;
--
-- /* NOR 128 MiB */
-- nor@0 {
-- compatible = "cfi-flash";
-- reg = <0 0x8000000>;
-- bank-width = <2>;
-- };
-- };
--
- pcie-controller {
- status = "okay";
- /* Internal mini-PCIe connector */
+++ /dev/null
-From db5029d82c4f0685438ea38eb3fbaadac46a22ba Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 12 Jun 2013 18:02:19 -0300
-Subject: [PATCH 059/203] ARM: mvebu: Relocate Armada 370/XP PCIe device tree
- nodes
-
-Now that mbus has been added to the device tree, it's possible to
-move the PCIe nodes out of internal registers, placing it directly
-below the mbus. This is a more accurate representation of the
-hardware.
-
-Moving the PCIe nodes, we now need to introduce an extra cell to
-encode the window target ID and attribute. Since this depends on
-the PCIe port, we split the ranges translation entries, to correspond
-to each MBus window.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/boot/dts/armada-370-mirabox.dts | 32 +-
- arch/arm/boot/dts/armada-370-xp.dtsi | 2 +
- arch/arm/boot/dts/armada-370.dtsi | 101 +++---
- arch/arm/boot/dts/armada-xp-db.dts | 67 ++--
- arch/arm/boot/dts/armada-xp-gp.dts | 42 +--
- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 222 ++++++------
- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 261 ++++++++-------
- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 409 ++++++++++++-----------
- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 18 +-
- 9 files changed, 612 insertions(+), 542 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370-mirabox.dts
-+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
-@@ -28,6 +28,22 @@
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
-
-+ pcie-controller {
-+ status = "okay";
-+
-+ /* Internal mini-PCIe connector */
-+ pcie@1,0 {
-+ /* Port 0, Lane 0 */
-+ status = "okay";
-+ };
-+
-+ /* Connected on the PCB to a USB 3.0 XHCI controller */
-+ pcie@2,0 {
-+ /* Port 1, Lane 0 */
-+ status = "okay";
-+ };
-+ };
-+
- internal-regs {
- serial@12000 {
- clock-frequency = <200000000>;
-@@ -123,22 +139,6 @@
- reg = <0x25>;
- };
- };
--
-- pcie-controller {
-- status = "okay";
--
-- /* Internal mini-PCIe connector */
-- pcie@1,0 {
-- /* Port 0, Lane 0 */
-- status = "okay";
-- };
--
-- /* Connected on the PCB to a USB 3.0 XHCI controller */
-- pcie@2,0 {
-- /* Port 1, Lane 0 */
-- status = "okay";
-- };
-- };
- };
- };
- };
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -35,6 +35,8 @@
- #size-cells = <1>;
- controller = <&mbusc>;
- interrupt-parent = <&mpic>;
-+ pcie-mem-aperture = <0xe0000000 0x8000000>;
-+ pcie-io-aperture = <0xe8000000 0x100000>;
-
- devbus-bootcs {
- compatible = "marvell,mvebu-devbus";
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -36,6 +36,59 @@
- reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
- };
-
-+ pcie-controller {
-+ compatible = "marvell,armada-370-pcie";
-+ status = "disabled";
-+ device_type = "pci";
-+
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ bus-range = <0x00 0xff>;
-+
-+ ranges =
-+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
-+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
-+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
-+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
-+ 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
-+ 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
-+
-+ pcie@1,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-+ reg = <0x0800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
-+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 58>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 5>;
-+ status = "disabled";
-+ };
-+
-+ pcie@2,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
-+ reg = <0x1000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
-+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 62>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 9>;
-+ status = "disabled";
-+ };
-+ };
-+
- internal-regs {
- system-controller@18200 {
- compatible = "marvell,armada-370-xp-system-controller";
-@@ -174,54 +227,6 @@
- 0x18304 0x4>;
- status = "okay";
- };
--
-- pcie-controller {
-- compatible = "marvell,armada-370-pcie";
-- status = "disabled";
-- device_type = "pci";
--
-- #address-cells = <3>;
-- #size-cells = <2>;
--
-- bus-range = <0x00 0xff>;
--
-- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
-- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
-- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
-- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
--
-- pcie@1,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-- reg = <0x0800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 58>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 5>;
-- status = "disabled";
-- };
--
-- pcie@2,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
-- reg = <0x1000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 62>;
-- marvell,pcie-port = <1>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 9>;
-- status = "disabled";
-- };
-- };
- };
- };
- };
---- a/arch/arm/boot/dts/armada-xp-db.dts
-+++ b/arch/arm/boot/dts/armada-xp-db.dts
-@@ -62,6 +62,39 @@
- };
- };
-
-+ pcie-controller {
-+ status = "okay";
-+
-+ /*
-+ * All 6 slots are physically present as
-+ * standard PCIe slots on the board.
-+ */
-+ pcie@1,0 {
-+ /* Port 0, Lane 0 */
-+ status = "okay";
-+ };
-+ pcie@2,0 {
-+ /* Port 0, Lane 1 */
-+ status = "okay";
-+ };
-+ pcie@3,0 {
-+ /* Port 0, Lane 2 */
-+ status = "okay";
-+ };
-+ pcie@4,0 {
-+ /* Port 0, Lane 3 */
-+ status = "okay";
-+ };
-+ pcie@9,0 {
-+ /* Port 2, Lane 0 */
-+ status = "okay";
-+ };
-+ pcie@10,0 {
-+ /* Port 3, Lane 0 */
-+ status = "okay";
-+ };
-+ };
-+
- internal-regs {
- serial@12000 {
- clock-frequency = <250000000>;
-@@ -155,40 +188,6 @@
- spi-max-frequency = <20000000>;
- };
- };
--
-- pcie-controller {
-- status = "okay";
--
-- /*
-- * All 6 slots are physically present as
-- * standard PCIe slots on the board.
-- */
-- pcie@1,0 {
-- /* Port 0, Lane 0 */
-- status = "okay";
-- };
-- pcie@2,0 {
-- /* Port 0, Lane 1 */
-- status = "okay";
-- };
-- pcie@3,0 {
-- /* Port 0, Lane 2 */
-- status = "okay";
-- };
-- pcie@4,0 {
-- /* Port 0, Lane 3 */
-- status = "okay";
-- };
-- pcie@9,0 {
-- /* Port 2, Lane 0 */
-- status = "okay";
-- };
-- pcie@10,0 {
-- /* Port 3, Lane 0 */
-- status = "okay";
-- };
-- };
--
- };
- };
- };
---- a/arch/arm/boot/dts/armada-xp-gp.dts
-+++ b/arch/arm/boot/dts/armada-xp-gp.dts
-@@ -71,6 +71,27 @@
- };
- };
-
-+ pcie-controller {
-+ status = "okay";
-+
-+ /*
-+ * The 3 slots are physically present as
-+ * standard PCIe slots on the board.
-+ */
-+ pcie@1,0 {
-+ /* Port 0, Lane 0 */
-+ status = "okay";
-+ };
-+ pcie@9,0 {
-+ /* Port 2, Lane 0 */
-+ status = "okay";
-+ };
-+ pcie@10,0 {
-+ /* Port 3, Lane 0 */
-+ status = "okay";
-+ };
-+ };
-+
- internal-regs {
- serial@12000 {
- clock-frequency = <250000000>;
-@@ -154,27 +175,6 @@
- spi-max-frequency = <108000000>;
- };
- };
--
-- pcie-controller {
-- status = "okay";
--
-- /*
-- * The 3 slots are physically present as
-- * standard PCIe slots on the board.
-- */
-- pcie@1,0 {
-- /* Port 0, Lane 0 */
-- status = "okay";
-- };
-- pcie@9,0 {
-- /* Port 2, Lane 0 */
-- status = "okay";
-- };
-- pcie@10,0 {
-- /* Port 3, Lane 0 */
-- status = "okay";
-- };
-- };
- };
- };
- };
---- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-@@ -44,6 +44,124 @@
- };
-
- soc {
-+ /*
-+ * MV78230 has 2 PCIe units Gen2.0: One unit can be
-+ * configured as x4 or quad x1 lanes. One unit is
-+ * x4/x1.
-+ */
-+ pcie-controller {
-+ compatible = "marvell,armada-xp-pcie";
-+ status = "disabled";
-+ device_type = "pci";
-+
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ bus-range = <0x00 0xff>;
-+
-+ ranges =
-+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
-+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
-+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
-+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
-+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
-+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
-+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
-+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
-+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
-+ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
-+ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
-+ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
-+ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
-+ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
-+ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
-+
-+ pcie@1,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-+ reg = <0x0800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
-+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 58>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 5>;
-+ status = "disabled";
-+ };
-+
-+ pcie@2,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-+ reg = <0x1000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
-+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 59>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <1>;
-+ clocks = <&gateclk 6>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-+ reg = <0x1800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
-+ 0x81000000 0 0 0x81000000 0x3 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 60>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <2>;
-+ clocks = <&gateclk 7>;
-+ status = "disabled";
-+ };
-+
-+ pcie@4,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
-+ reg = <0x2000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
-+ 0x81000000 0 0 0x81000000 0x4 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 61>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <3>;
-+ clocks = <&gateclk 8>;
-+ status = "disabled";
-+ };
-+
-+ pcie@9,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-+ reg = <0x4800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
-+ 0x81000000 0 0 0x81000000 0x9 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 99>;
-+ marvell,pcie-port = <2>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 26>;
-+ status = "disabled";
-+ };
-+ };
-+
- internal-regs {
- pinctrl {
- compatible = "marvell,mv78230-pinctrl";
-@@ -79,108 +197,6 @@
- };
-
- /*
-- * MV78230 has 2 PCIe units Gen2.0: One unit can be
-- * configured as x4 or quad x1 lanes. One unit is
-- * x1 only.
-- */
-- pcie-controller {
-- compatible = "marvell,armada-xp-pcie";
-- status = "disabled";
-- device_type = "pci";
--
--#address-cells = <3>;
--#size-cells = <2>;
--
-- bus-range = <0x00 0xff>;
--
-- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
-- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
-- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
-- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
-- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
-- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
-- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
--
-- pcie@1,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-- reg = <0x0800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 58>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 5>;
-- status = "disabled";
-- };
--
-- pcie@2,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-- reg = <0x1000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 59>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <1>;
-- clocks = <&gateclk 6>;
-- status = "disabled";
-- };
--
-- pcie@3,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-- reg = <0x1800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 60>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <2>;
-- clocks = <&gateclk 7>;
-- status = "disabled";
-- };
--
-- pcie@4,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
-- reg = <0x2000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 61>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <3>;
-- clocks = <&gateclk 8>;
-- status = "disabled";
-- };
--
-- pcie@5,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
-- reg = <0x2800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 62>;
-- marvell,pcie-port = <1>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 9>;
-- status = "disabled";
-- };
-- };
- };
- };
- };
---- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-@@ -45,6 +45,145 @@
- };
-
- soc {
-+ /*
-+ * MV78260 has 3 PCIe units Gen2.0: Two units can be
-+ * configured as x4 or quad x1 lanes. One unit is
-+ * x4/x1.
-+ */
-+ pcie-controller {
-+ compatible = "marvell,armada-xp-pcie";
-+ status = "disabled";
-+ device_type = "pci";
-+
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ bus-range = <0x00 0xff>;
-+
-+ ranges =
-+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
-+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
-+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
-+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
-+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
-+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
-+ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
-+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
-+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
-+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
-+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
-+ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
-+ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
-+ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
-+ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
-+ 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
-+ 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
-+ 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
-+ 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
-+
-+ pcie@1,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-+ reg = <0x0800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
-+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 58>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 5>;
-+ status = "disabled";
-+ };
-+
-+ pcie@2,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-+ reg = <0x1000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
-+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 59>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <1>;
-+ clocks = <&gateclk 6>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-+ reg = <0x1800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
-+ 0x81000000 0 0 0x81000000 0x3 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 60>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <2>;
-+ clocks = <&gateclk 7>;
-+ status = "disabled";
-+ };
-+
-+ pcie@4,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
-+ reg = <0x2000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
-+ 0x81000000 0 0 0x81000000 0x4 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 61>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <3>;
-+ clocks = <&gateclk 8>;
-+ status = "disabled";
-+ };
-+
-+ pcie@9,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-+ reg = <0x4800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
-+ 0x81000000 0 0 0x81000000 0x9 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 99>;
-+ marvell,pcie-port = <2>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 26>;
-+ status = "disabled";
-+ };
-+
-+ pcie@10,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
-+ reg = <0x5000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
-+ 0x81000000 0 0 0x81000000 0xa 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 103>;
-+ marvell,pcie-port = <3>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 27>;
-+ status = "disabled";
-+ };
-+ };
-+
- internal-regs {
- pinctrl {
- compatible = "marvell,mv78260-pinctrl";
-@@ -98,177 +237,6 @@
- status = "disabled";
- };
-
-- /*
-- * MV78260 has 3 PCIe units Gen2.0: Two units can be
-- * configured as x4 or quad x1 lanes. One unit is
-- * x4 only.
-- */
-- pcie-controller {
-- compatible = "marvell,armada-xp-pcie";
-- status = "disabled";
-- device_type = "pci";
--
-- #address-cells = <3>;
-- #size-cells = <2>;
--
-- bus-range = <0x00 0xff>;
--
-- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
-- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
-- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
-- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
-- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
-- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
-- 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
-- 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
-- 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
-- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
-- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
--
-- pcie@1,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-- reg = <0x0800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 58>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 5>;
-- status = "disabled";
-- };
--
-- pcie@2,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-- reg = <0x1000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 59>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <1>;
-- clocks = <&gateclk 6>;
-- status = "disabled";
-- };
--
-- pcie@3,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-- reg = <0x1800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 60>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <2>;
-- clocks = <&gateclk 7>;
-- status = "disabled";
-- };
--
-- pcie@4,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
-- reg = <0x2000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 61>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <3>;
-- clocks = <&gateclk 8>;
-- status = "disabled";
-- };
--
-- pcie@5,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
-- reg = <0x2800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 62>;
-- marvell,pcie-port = <1>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 9>;
-- status = "disabled";
-- };
--
-- pcie@6,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
-- reg = <0x3000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 63>;
-- marvell,pcie-port = <1>;
-- marvell,pcie-lane = <1>;
-- clocks = <&gateclk 10>;
-- status = "disabled";
-- };
--
-- pcie@7,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
-- reg = <0x3800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 64>;
-- marvell,pcie-port = <1>;
-- marvell,pcie-lane = <2>;
-- clocks = <&gateclk 11>;
-- status = "disabled";
-- };
--
-- pcie@8,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
-- reg = <0x4000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 65>;
-- marvell,pcie-port = <1>;
-- marvell,pcie-lane = <3>;
-- clocks = <&gateclk 12>;
-- status = "disabled";
-- };
--
-- pcie@9,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-- reg = <0x4800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 99>;
-- marvell,pcie-port = <2>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 26>;
-- status = "disabled";
-- };
-- };
- };
- };
- };
---- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-@@ -60,6 +60,227 @@
- };
-
- soc {
-+ /*
-+ * MV78460 has 4 PCIe units Gen2.0: Two units can be
-+ * configured as x4 or quad x1 lanes. Two units are
-+ * x4/x1.
-+ */
-+ pcie-controller {
-+ compatible = "marvell,armada-xp-pcie";
-+ status = "disabled";
-+ device_type = "pci";
-+
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ bus-range = <0x00 0xff>;
-+
-+ ranges =
-+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
-+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
-+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
-+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
-+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
-+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
-+ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
-+ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
-+ 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
-+ 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
-+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
-+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
-+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
-+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
-+ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
-+ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
-+ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
-+ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
-+
-+ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
-+ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
-+ 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
-+ 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
-+ 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
-+ 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
-+ 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
-+ 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
-+
-+ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
-+ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
-+
-+ 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
-+ 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
-+
-+ pcie@1,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-+ reg = <0x0800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
-+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 58>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 5>;
-+ status = "disabled";
-+ };
-+
-+ pcie@2,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
-+ reg = <0x1000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
-+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 59>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <1>;
-+ clocks = <&gateclk 6>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
-+ reg = <0x1800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
-+ 0x81000000 0 0 0x81000000 0x3 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 60>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <2>;
-+ clocks = <&gateclk 7>;
-+ status = "disabled";
-+ };
-+
-+ pcie@4,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
-+ reg = <0x2000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
-+ 0x81000000 0 0 0x81000000 0x4 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 61>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <3>;
-+ clocks = <&gateclk 8>;
-+ status = "disabled";
-+ };
-+
-+ pcie@5,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
-+ reg = <0x2800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
-+ 0x81000000 0 0 0x81000000 0x5 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 62>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 9>;
-+ status = "disabled";
-+ };
-+
-+ pcie@6,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
-+ reg = <0x3000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
-+ 0x81000000 0 0 0x81000000 0x6 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 63>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <1>;
-+ clocks = <&gateclk 10>;
-+ status = "disabled";
-+ };
-+
-+ pcie@7,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
-+ reg = <0x3800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
-+ 0x81000000 0 0 0x81000000 0x7 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 64>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <2>;
-+ clocks = <&gateclk 11>;
-+ status = "disabled";
-+ };
-+
-+ pcie@8,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
-+ reg = <0x4000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
-+ 0x81000000 0 0 0x81000000 0x8 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 65>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <3>;
-+ clocks = <&gateclk 12>;
-+ status = "disabled";
-+ };
-+
-+ pcie@9,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
-+ reg = <0x4800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
-+ 0x81000000 0 0 0x81000000 0x9 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 99>;
-+ marvell,pcie-port = <2>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 26>;
-+ status = "disabled";
-+ };
-+
-+ pcie@10,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
-+ reg = <0x5000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
-+ 0x81000000 0 0 0x81000000 0xa 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 103>;
-+ marvell,pcie-port = <3>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gateclk 27>;
-+ status = "disabled";
-+ };
-+ };
-+
- internal-regs {
- pinctrl {
- compatible = "marvell,mv78460-pinctrl";
-@@ -112,194 +333,6 @@
- clocks = <&gateclk 1>;
- status = "disabled";
- };
--
-- /*
-- * MV78460 has 4 PCIe units Gen2.0: Two units can be
-- * configured as x4 or quad x1 lanes. Two units are
-- * x4/x1.
-- */
-- pcie-controller {
-- compatible = "marvell,armada-xp-pcie";
-- status = "disabled";
-- device_type = "pci";
--
-- #address-cells = <3>;
-- #size-cells = <2>;
--
-- bus-range = <0x00 0xff>;
--
-- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
-- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
-- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
-- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
-- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
-- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
-- 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
-- 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
-- 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
-- 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
-- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
-- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
--
-- pcie@1,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-- reg = <0x0800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 58>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 5>;
-- status = "disabled";
-- };
--
-- pcie@2,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
-- reg = <0x1000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 59>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <1>;
-- clocks = <&gateclk 6>;
-- status = "disabled";
-- };
--
-- pcie@3,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
-- reg = <0x1800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 60>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <2>;
-- clocks = <&gateclk 7>;
-- status = "disabled";
-- };
--
-- pcie@4,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
-- reg = <0x2000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 61>;
-- marvell,pcie-port = <0>;
-- marvell,pcie-lane = <3>;
-- clocks = <&gateclk 8>;
-- status = "disabled";
-- };
--
-- pcie@5,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
-- reg = <0x2800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 62>;
-- marvell,pcie-port = <1>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 9>;
-- status = "disabled";
-- };
--
-- pcie@6,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
-- reg = <0x3000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 63>;
-- marvell,pcie-port = <1>;
-- marvell,pcie-lane = <1>;
-- clocks = <&gateclk 10>;
-- status = "disabled";
-- };
--
-- pcie@7,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
-- reg = <0x3800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 64>;
-- marvell,pcie-port = <1>;
-- marvell,pcie-lane = <2>;
-- clocks = <&gateclk 11>;
-- status = "disabled";
-- };
--
-- pcie@8,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
-- reg = <0x4000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 65>;
-- marvell,pcie-port = <1>;
-- marvell,pcie-lane = <3>;
-- clocks = <&gateclk 12>;
-- status = "disabled";
-- };
-- pcie@9,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
-- reg = <0x4800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 99>;
-- marvell,pcie-port = <2>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 26>;
-- status = "disabled";
-- };
--
-- pcie@10,0 {
-- device_type = "pci";
-- assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
-- reg = <0x5000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 103>;
-- marvell,pcie-port = <3>;
-- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 27>;
-- status = "disabled";
-- };
-- };
- };
- };
- };
---- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
-+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
-@@ -59,6 +59,15 @@
- };
- };
-
-+ pcie-controller {
-+ status = "okay";
-+ /* Internal mini-PCIe connector */
-+ pcie@1,0 {
-+ /* Port 0, Lane 0 */
-+ status = "okay";
-+ };
-+ };
-+
- internal-regs {
- serial@12000 {
- clock-frequency = <250000000>;
-@@ -172,15 +181,6 @@
- usb@51000 {
- status = "okay";
- };
--
-- pcie-controller {
-- status = "okay";
-- /* Internal mini-PCIe connector */
-- pcie@1,0 {
-- /* Port 0, Lane 0 */
-- status = "okay";
-- };
-- };
- };
- };
- };
+++ /dev/null
-From d1989c73eb770891635cc644f091d7524bbfd696 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 23 Jul 2013 07:42:09 -0300
-Subject: [PATCH 060/203] ARM: kirkwood: Split DT and legacy MBus
- initialization
-
-This commit replaces the legacy MBus initialization with the new
-DT-based in Kirkwood. For boards that are not yet converted to DT,
-we keep the legacy initialization.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/mach-kirkwood/board-dt.c | 1 +
- arch/arm/mach-kirkwood/common.c | 8 ++++----
- 2 files changed, 5 insertions(+), 4 deletions(-)
-
---- a/arch/arm/mach-kirkwood/board-dt.c
-+++ b/arch/arm/mach-kirkwood/board-dt.c
-@@ -93,6 +93,7 @@ static void __init kirkwood_dt_init(void
- */
- writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
-
-+ BUG_ON(mvebu_mbus_dt_init());
- kirkwood_setup_wins();
-
- kirkwood_l2_init();
---- a/arch/arm/mach-kirkwood/common.c
-+++ b/arch/arm/mach-kirkwood/common.c
-@@ -527,10 +527,6 @@ void __init kirkwood_cpuidle_init(void)
- void __init kirkwood_init_early(void)
- {
- orion_time_set_base(TIMER_VIRT_BASE);
--
-- mvebu_mbus_init("marvell,kirkwood-mbus",
-- BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
-- DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
- }
-
- int kirkwood_tclk;
-@@ -703,6 +699,10 @@ void __init kirkwood_init(void)
- */
- writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
-
-+ BUG_ON(mvebu_mbus_init("marvell,kirkwood-mbus",
-+ BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
-+ DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ));
-+
- kirkwood_setup_wins();
-
- kirkwood_l2_init();
+++ /dev/null
-From 67bbed6edc12a5f239435c182d9c56ce2c930d87 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 23 Jul 2013 07:45:49 -0300
-Subject: [PATCH 061/203] ARM: kirkwood: Use the preprocessor on device tree
- files
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/boot/dts/kirkwood-cloudbox.dts | 4 +--
- arch/arm/boot/dts/kirkwood-dns320.dts | 2 +-
- arch/arm/boot/dts/kirkwood-dns325.dts | 2 +-
- arch/arm/boot/dts/kirkwood-dnskw.dtsi | 4 +--
- arch/arm/boot/dts/kirkwood-dockstar.dts | 4 +--
- arch/arm/boot/dts/kirkwood-dreamplug.dts | 4 +--
- arch/arm/boot/dts/kirkwood-goflexnet.dts | 4 +--
- .../arm/boot/dts/kirkwood-guruplug-server-plus.dts | 4 +--
- arch/arm/boot/dts/kirkwood-ib62x0.dts | 4 +--
- arch/arm/boot/dts/kirkwood-iconnect.dts | 4 +--
- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 4 +--
- arch/arm/boot/dts/kirkwood-is2.dts | 2 +-
- arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 4 +--
- arch/arm/boot/dts/kirkwood-lschlv2.dts | 2 +-
- arch/arm/boot/dts/kirkwood-lsxhl.dts | 2 +-
- arch/arm/boot/dts/kirkwood-lsxl.dtsi | 4 +--
- arch/arm/boot/dts/kirkwood-mplcec4.dts | 4 +--
- .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 4 +--
- arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 4 +--
- arch/arm/boot/dts/kirkwood-ns2.dts | 2 +-
- arch/arm/boot/dts/kirkwood-ns2lite.dts | 2 +-
- arch/arm/boot/dts/kirkwood-ns2max.dts | 2 +-
- arch/arm/boot/dts/kirkwood-ns2mini.dts | 2 +-
- arch/arm/boot/dts/kirkwood-nsa310.dts | 40 +++++++++++++---------
- arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 4 +--
- arch/arm/boot/dts/kirkwood-topkick.dts | 4 +--
- arch/arm/boot/dts/kirkwood-ts219-6281.dts | 13 +++----
- arch/arm/boot/dts/kirkwood-ts219-6282.dts | 21 ++++++++----
- 28 files changed, 86 insertions(+), 70 deletions(-)
-
---- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
-+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "LaCie CloudBox";
---- a/arch/arm/boot/dts/kirkwood-dns320.dts
-+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
-@@ -1,6 +1,6 @@
- /dts-v1/;
-
--/include/ "kirkwood-dnskw.dtsi"
-+#include "kirkwood-dnskw.dtsi"
-
- / {
- model = "D-Link DNS-320 NAS (Rev A1)";
---- a/arch/arm/boot/dts/kirkwood-dns325.dts
-+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
-@@ -1,6 +1,6 @@
- /dts-v1/;
-
--/include/ "kirkwood-dnskw.dtsi"
-+#include "kirkwood-dnskw.dtsi"
-
- / {
- model = "D-Link DNS-325 NAS (Rev A1)";
---- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
-+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
-@@ -1,5 +1,5 @@
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "D-Link DNS NASes (kirkwood-based)";
---- a/arch/arm/boot/dts/kirkwood-dockstar.dts
-+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "Seagate FreeAgent Dockstar";
---- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
-+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "Globalscale Technologies Dreamplug";
---- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
-+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "Seagate GoFlex Net";
---- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
-+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "Globalscale Technologies Guruplug Server Plus";
---- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
-+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
---- a/arch/arm/boot/dts/kirkwood-iconnect.dts
-+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "Iomega Iconnect";
---- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
-+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "Iomega StorCenter ix2-200";
---- a/arch/arm/boot/dts/kirkwood-is2.dts
-+++ b/arch/arm/boot/dts/kirkwood-is2.dts
-@@ -1,6 +1,6 @@
- /dts-v1/;
-
--/include/ "kirkwood-ns2-common.dtsi"
-+#include "kirkwood-ns2-common.dtsi"
-
- / {
- model = "LaCie Internet Space v2";
---- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
-+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-98dx4122.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-98dx4122.dtsi"
-
- / {
- model = "Keymile Kirkwood Reference Design";
---- a/arch/arm/boot/dts/kirkwood-lschlv2.dts
-+++ b/arch/arm/boot/dts/kirkwood-lschlv2.dts
-@@ -1,6 +1,6 @@
- /dts-v1/;
-
--/include/ "kirkwood-lsxl.dtsi"
-+#include "kirkwood-lsxl.dtsi"
-
- / {
- model = "Buffalo Linkstation LS-CHLv2";
---- a/arch/arm/boot/dts/kirkwood-lsxhl.dts
-+++ b/arch/arm/boot/dts/kirkwood-lsxhl.dts
-@@ -1,6 +1,6 @@
- /dts-v1/;
-
--/include/ "kirkwood-lsxl.dtsi"
-+#include "kirkwood-lsxl.dtsi"
-
- / {
- model = "Buffalo Linkstation LS-XHL";
---- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
-+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
-@@ -1,5 +1,5 @@
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- chosen {
---- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
-+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "MPL CEC4";
---- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
-+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6282.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6282.dtsi"
-
- / {
- model = "NETGEAR ReadyNAS Duo v2";
---- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
-+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
-@@ -1,5 +1,5 @@
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- chosen {
---- a/arch/arm/boot/dts/kirkwood-ns2.dts
-+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
-@@ -1,6 +1,6 @@
- /dts-v1/;
-
--/include/ "kirkwood-ns2-common.dtsi"
-+#include "kirkwood-ns2-common.dtsi"
-
- / {
- model = "LaCie Network Space v2";
---- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
-+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
-@@ -1,6 +1,6 @@
- /dts-v1/;
-
--/include/ "kirkwood-ns2-common.dtsi"
-+#include "kirkwood-ns2-common.dtsi"
-
- / {
- model = "LaCie Network Space Lite v2";
---- a/arch/arm/boot/dts/kirkwood-ns2max.dts
-+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
-@@ -1,6 +1,6 @@
- /dts-v1/;
-
--/include/ "kirkwood-ns2-common.dtsi"
-+#include "kirkwood-ns2-common.dtsi"
-
- / {
- model = "LaCie Network Space Max v2";
---- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
-+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
-@@ -1,6 +1,6 @@
- /dts-v1/;
-
--/include/ "kirkwood-ns2-common.dtsi"
-+#include "kirkwood-ns2-common.dtsi"
-
- / {
- /* This machine is embedded in the first LaCie CloudBox product. */
---- a/arch/arm/boot/dts/kirkwood-nsa310.dts
-+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
-@@ -1,6 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-
- / {
- model = "ZyXEL NSA310";
-@@ -17,22 +18,7 @@
-
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
-- pinctrl-0 = < &pmx_led_esata_green
-- &pmx_led_esata_red
-- &pmx_led_usb_green
-- &pmx_led_usb_red
-- &pmx_usb_power_off
-- &pmx_led_sys_green
-- &pmx_led_sys_red
-- &pmx_btn_reset
-- &pmx_btn_copy
-- &pmx_led_copy_green
-- &pmx_led_copy_red
-- &pmx_led_hdd_green
-- &pmx_led_hdd_red
-- &pmx_unknown
-- &pmx_btn_power
-- &pmx_pwr_off >;
-+ pinctrl-0 = <&pmx_unknown>;
- pinctrl-names = "default";
-
- pmx_led_esata_green: pmx-led-esata-green {
-@@ -176,12 +162,22 @@
- reg = <0x5040000 0x2fc0000>;
- };
- };
-+
-+ pcie-controller {
-+ status = "okay";
-+
-+ pcie@1,0 {
-+ status = "okay";
-+ };
-+ };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-+ pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
-+ pinctrl-names = "default";
-
- button@1 {
- label = "Power Button";
-@@ -202,6 +198,12 @@
-
- gpio-leds {
- compatible = "gpio-leds";
-+ pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red
-+ &pmx_led_usb_green &pmx_led_usb_red
-+ &pmx_led_sys_green &pmx_led_sys_red
-+ &pmx_led_copy_green &pmx_led_copy_red
-+ &pmx_led_hdd_green &pmx_led_hdd_red>;
-+ pinctrl-names = "default";
-
- green-sys {
- label = "nsa310:green:sys";
-@@ -247,6 +249,8 @@
-
- gpio_poweroff {
- compatible = "gpio-poweroff";
-+ pinctrl-0 = <&pmx_pwr_off>;
-+ pinctrl-names = "default";
- gpios = <&gpio1 16 0>;
- };
-
-@@ -254,6 +258,8 @@
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-+ pinctrl-0 = <&pmx_usb_power_off>;
-+ pinctrl-names = "default";
-
- usb0_power_off: regulator@1 {
- compatible = "regulator-fixed";
---- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
-+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6282.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6282.dtsi"
-
- / {
- model = "Plat'Home OpenBlocksA6";
---- a/arch/arm/boot/dts/kirkwood-topkick.dts
-+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
-@@ -1,7 +1,7 @@
- /dts-v1/;
-
--/include/ "kirkwood.dtsi"
--/include/ "kirkwood-6282.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6282.dtsi"
-
- / {
- model = "Univeral Scientific Industrial Co. Topkick-1281P2";
---- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
-+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
-@@ -1,16 +1,14 @@
- /dts-v1/;
-
--/include/ "kirkwood-ts219.dtsi"
--/include/ "kirkwood-6281.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6281.dtsi"
-+#include "kirkwood-ts219.dtsi"
-
- / {
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
-
-- pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
-- &pmx_twsi0 &pmx_sata0 &pmx_sata1
-- &pmx_ram_size &pmx_reset_button
-- &pmx_USB_copy_button &pmx_board_id>;
-+ pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
- pinctrl-names = "default";
-
- pmx_ram_size: pmx-ram-size {
-@@ -38,6 +36,9 @@
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-+ pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
-+ pinctrl-names = "default";
-+
- button@1 {
- label = "USB Copy";
- linux,code = <133>;
---- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
-+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
-@@ -1,16 +1,14 @@
- /dts-v1/;
-
--/include/ "kirkwood-ts219.dtsi"
--/include/ "kirkwood-6282.dtsi"
-+#include "kirkwood.dtsi"
-+#include "kirkwood-6282.dtsi"
-+#include "kirkwood-ts219.dtsi"
-
- / {
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
-
-- pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
-- &pmx_twsi0 &pmx_sata0 &pmx_sata1
-- &pmx_ram_size &pmx_reset_button
-- &pmx_USB_copy_button &pmx_board_id>;
-+ pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
- pinctrl-names = "default";
-
- pmx_ram_size: pmx-ram-size {
-@@ -32,12 +30,23 @@
- marvell,function = "gpio";
- };
- };
-+ pcie-controller {
-+ status = "okay";
-+
-+ pcie@2,0 {
-+ status = "okay";
-+ };
-+ };
-+
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-+ pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
-+ pinctrl-names = "default";
-+
- button@1 {
- label = "USB Copy";
- linux,code = <133>;
+++ /dev/null
-From 9d4a304873c9f6a8bbf78cba329985768a1c6c93 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 23 Jul 2013 07:48:04 -0300
-Subject: [PATCH 062/203] ARM: kirkwood: Introduce MBus DT node
-
-Add a minimal MBus node, just to allow the MBus driver to probe.
-Follow-up patches will migrate the rest of the nodes appropriately.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/boot/dts/kirkwood.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm/boot/dts/kirkwood.dtsi
-+++ b/arch/arm/boot/dts/kirkwood.dtsi
-@@ -16,6 +16,11 @@
- <0xf1020214 0x04>;
- };
-
-+ mbus {
-+ compatible = "marvell,kirkwood-mbus", "simple-bus";
-+ controller = <&mbusc>;
-+ };
-+
- ocp@f1000000 {
- compatible = "simple-bus";
- ranges = <0x00000000 0xf1000000 0x4000000
-@@ -23,6 +28,11 @@
- #address-cells = <1>;
- #size-cells = <1>;
-
-+ mbusc: mbus-controller@20000 {
-+ compatible = "marvell,mbus-controller";
-+ reg = <0x20000 0x80>, <0x1500 0x20>;
-+ };
-+
- core_clk: core-clocks@10030 {
- compatible = "marvell,kirkwood-core-clock";
- reg = <0x10030 0x4>;
+++ /dev/null
-From 32016796bb28ebf748851c166b03159600aa9a00 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 23 Jul 2013 08:33:39 -0300
-Subject: [PATCH 063/203] ARM: kirkwood: Introduce MBUS_ID
-
-This macro is used to define window's target ID and attribute cells
-for the MBus ranges entries.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/boot/dts/kirkwood.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/boot/dts/kirkwood.dtsi
-+++ b/arch/arm/boot/dts/kirkwood.dtsi
-@@ -1,5 +1,7 @@
- /include/ "skeleton.dtsi"
-
-+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
-+
- / {
- compatible = "marvell,kirkwood";
- interrupt-parent = <&intc>;
+++ /dev/null
-From ae23894bcb163d1f91483b9566dc077f1e863af6 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 23 Jul 2013 08:44:00 -0300
-Subject: [PATCH 064/203] ARM: kirkwood: Relocate PCIe device tree nodes
-
-Now that mbus has been added to the device tree, it's possible to
-move the PCIe nodes out of the ocp node, placing it directly
-below the mbus. This is a more accurate representation of the hardware.
-
-Moving the PCIe nodes, we now need to introduce an extra cell to
-encode the window target ID and attribute. Since this depends on
-the PCIe port, we split the ranges translation entries, to
-correspond to each MBus window.
-
-In addition, we encode the PCIe memory and I/O apertures in the MBus
-node, according to the MBus DT binding specification. The choice made
-is 0xe0000000-0xf0000000 for memory space, and 0xf200000-0xf2100000 for
-I/O space. These apertures can be changed in each per-board DT file.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- arch/arm/boot/dts/kirkwood-6281.dtsi | 35 ++++++++++++++
- arch/arm/boot/dts/kirkwood-6282.dtsi | 55 ++++++++++++++++++++++
- arch/arm/boot/dts/kirkwood-iconnect.dts | 11 +++++
- arch/arm/boot/dts/kirkwood-mplcec4.dts | 11 +++++
- .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 11 +++++
- arch/arm/boot/dts/kirkwood-nsa310.dts | 19 ++++----
- arch/arm/boot/dts/kirkwood-ts219-6282.dts | 19 ++++----
- arch/arm/boot/dts/kirkwood-ts219.dtsi | 10 ++++
- arch/arm/boot/dts/kirkwood.dtsi | 4 ++
- 9 files changed, 159 insertions(+), 16 deletions(-)
-
---- a/arch/arm/boot/dts/kirkwood-6281.dtsi
-+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
-@@ -1,4 +1,39 @@
- / {
-+ mbus {
-+ pcie-controller {
-+ compatible = "marvell,kirkwood-pcie";
-+ status = "disabled";
-+ device_type = "pci";
-+
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ bus-range = <0x00 0xff>;
-+
-+ ranges =
-+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
-+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
-+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
-+
-+ pcie@1,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
-+ reg = <0x0800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
-+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &intc 9>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gate_clk 2>;
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
- compatible = "marvell,88f6281-pinctrl";
---- a/arch/arm/boot/dts/kirkwood-6282.dtsi
-+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
-@@ -1,4 +1,59 @@
- / {
-+ mbus {
-+ pcie-controller {
-+ compatible = "marvell,kirkwood-pcie";
-+ status = "disabled";
-+ device_type = "pci";
-+
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ bus-range = <0x00 0xff>;
-+
-+ ranges =
-+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
-+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
-+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
-+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
-+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
-+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
-+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
-+
-+ pcie@1,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
-+ reg = <0x0800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
-+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &intc 9>;
-+ marvell,pcie-port = <0>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gate_clk 2>;
-+ status = "disabled";
-+ };
-+
-+ pcie@2,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
-+ reg = <0x1000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
-+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &intc 10>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <0>;
-+ clocks = <&gate_clk 18>;
-+ status = "disabled";
-+ };
-+ };
-+ };
- ocp@f1000000 {
-
- pinctrl: pinctrl@10000 {
---- a/arch/arm/boot/dts/kirkwood-iconnect.dts
-+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
-@@ -18,6 +18,17 @@
- linux,initrd-end = <0x4800000>;
- };
-
-+ mbus {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
-+ pcie-controller {
-+ status = "okay";
-+
-+ pcie@1,0 {
-+ status = "okay";
-+ };
-+ };
-+ };
-+
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
-
---- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
-+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
-@@ -16,6 +16,17 @@
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- };
-
-+ mbus {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
-+ pcie-controller {
-+ status = "okay";
-+
-+ pcie@1,0 {
-+ status = "okay";
-+ };
-+ };
-+ };
-+
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
-
---- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
-+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
-@@ -16,6 +16,17 @@
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- };
-
-+ mbus {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
-+ pcie-controller {
-+ status = "okay";
-+
-+ pcie@1,0 {
-+ status = "okay";
-+ };
-+ };
-+ };
-+
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
-
---- a/arch/arm/boot/dts/kirkwood-nsa310.dts
-+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
-@@ -16,6 +16,17 @@
- bootargs = "console=ttyS0,115200";
- };
-
-+ mbus {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
-+ pcie-controller {
-+ status = "okay";
-+
-+ pcie@1,0 {
-+ status = "okay";
-+ };
-+ };
-+ };
-+
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
- pinctrl-0 = <&pmx_unknown>;
-@@ -162,14 +173,6 @@
- reg = <0x5040000 0x2fc0000>;
- };
- };
--
-- pcie-controller {
-- status = "okay";
--
-- pcie@1,0 {
-- status = "okay";
-- };
-- };
- };
-
- gpio_keys {
---- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
-+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
-@@ -5,6 +5,17 @@
- #include "kirkwood-ts219.dtsi"
-
- / {
-+ mbus {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
-+ pcie-controller {
-+ status = "okay";
-+
-+ pcie@2,0 {
-+ status = "okay";
-+ };
-+ };
-+ };
-+
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
-
-@@ -30,14 +41,6 @@
- marvell,function = "gpio";
- };
- };
-- pcie-controller {
-- status = "okay";
--
-- pcie@2,0 {
-- status = "okay";
-- };
-- };
--
- };
-
- gpio_keys {
---- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
-+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
-@@ -13,6 +13,16 @@
- bootargs = "console=ttyS0,115200n8";
- };
-
-+ mbus {
-+ pcie-controller {
-+ status = "okay";
-+
-+ pcie@1,0 {
-+ status = "okay";
-+ };
-+ };
-+ };
-+
- ocp@f1000000 {
- i2c@11000 {
- status = "okay";
---- a/arch/arm/boot/dts/kirkwood.dtsi
-+++ b/arch/arm/boot/dts/kirkwood.dtsi
-@@ -20,7 +20,11 @@
-
- mbus {
- compatible = "marvell,kirkwood-mbus", "simple-bus";
-+ #address-cells = <2>;
-+ #size-cells = <1>;
- controller = <&mbusc>;
-+ pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
-+ pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
- };
-
- ocp@f1000000 {
+++ /dev/null
-From 442681ff6aca5e839fe41378ff919df1c340dc62 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 28 May 2013 07:58:31 -0300
-Subject: [PATCH 065/203] bus: mvebu-mbus: Add devicetree binding
-
-Introduce the devicetree binding for the mvebu MBus driver
-avaiable in the mvebu SoCs (Armada 370/XP, Kirkwood, Dove, ...).
-
-This binding provides an accurate model of the SoC address space,
-and allows to declare the address and size of the decoding windows the MBus
-needs to access the peripherals, together with the target ID and attribute
-for those windows.
-
-The binding is composed of two required nodes: one for the MBus bus
-and one for the MBus controller.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- .../devicetree/bindings/bus/mvebu-mbus.txt | 276 +++++++++++++++++++++
- 1 file changed, 276 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/bus/mvebu-mbus.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
-@@ -0,0 +1,276 @@
-+
-+* Marvell MBus
-+
-+Required properties:
-+
-+- compatible: Should be set to one of the following:
-+ marvell,armada370-mbus
-+ marvell,armadaxp-mbus
-+ marvell,armada370-mbus
-+ marvell,armadaxp-mbus
-+ marvell,kirkwood-mbus
-+ marvell,dove-mbus
-+ marvell,orion5x-88f5281-mbus
-+ marvell,orion5x-88f5182-mbus
-+ marvell,orion5x-88f5181-mbus
-+ marvell,orion5x-88f6183-mbus
-+ marvell,mv78xx0-mbus
-+
-+- address-cells: Must be '2'. The first cell for the MBus ID encoding,
-+ the second cell for the address offset within the window.
-+
-+- size-cells: Must be '1'.
-+
-+- ranges: Must be set up to provide a proper translation for each child.
-+ See the examples below.
-+
-+- controller: Contains a single phandle referring to the MBus controller
-+ node. This allows to specify the node that contains the
-+ registers that control the MBus, which is typically contained
-+ within the internal register window (see below).
-+
-+Optional properties:
-+
-+- pcie-mem-aperture: This optional property contains the aperture for
-+ the memory region of the PCIe driver.
-+ If it's defined, it must encode the base address and
-+ size for the address decoding windows allocated for
-+ the PCIe memory region.
-+
-+- pcie-io-aperture: Just as explained for the above property, this
-+ optional property contains the aperture for the
-+ I/O region of the PCIe driver.
-+
-+* Marvell MBus controller
-+
-+Required properties:
-+
-+- compatible: Should be set to "marvell,mbus-controller".
-+
-+- reg: Device's register space.
-+ Two entries are expected (see the examples below):
-+ the first one controls the devices decoding window and
-+ the second one controls the SDRAM decoding window.
-+
-+Example:
-+
-+ soc {
-+ compatible = "marvell,armada370-mbus", "simple-bus";
-+ #address-cells = <2>;
-+ #size-cells = <1>;
-+ controller = <&mbusc>;
-+ pcie-mem-aperture = <0xe0000000 0x8000000>;
-+ pcie-io-aperture = <0xe8000000 0x100000>;
-+
-+ internal-regs {
-+ compatible = "simple-bus";
-+
-+ mbusc: mbus-controller@20000 {
-+ compatible = "marvell,mbus-controller";
-+ reg = <0x20000 0x100>, <0x20180 0x20>;
-+ };
-+
-+ /* more children ...*/
-+ };
-+ };
-+
-+** MBus address decoding window specification
-+
-+The MBus children address space is comprised of two cells: the first one for
-+the window ID and the second one for the offset within the window.
-+In order to allow to describe valid and non-valid window entries, the
-+following encoding is used:
-+
-+ 0xSIAA0000 0x00oooooo
-+
-+Where:
-+
-+ S = 0x0 for a MBus valid window
-+ S = 0xf for a non-valid window (see below)
-+
-+If S = 0x0, then:
-+
-+ I = 4-bit window target ID
-+ AA = windpw attribute
-+
-+If S = 0xf, then:
-+
-+ I = don't care
-+ AA = 1 for internal register
-+
-+Following the above encoding, for each ranges entry for a MBus valid window
-+(S = 0x0), an address decoding window is allocated. On the other side,
-+entries for translation that do not correspond to valid windows (S = 0xf)
-+are skipped.
-+
-+ soc {
-+ compatible = "marvell,armada370-mbus", "simple-bus";
-+ #address-cells = <2>;
-+ #size-cells = <1>;
-+ controller = <&mbusc>;
-+
-+ ranges = <0xf0010000 0 0 0xd0000000 0x100000
-+ 0x01e00000 0 0 0xfff00000 0x100000>;
-+
-+ bootrom {
-+ compatible = "marvell,bootrom";
-+ reg = <0x01e00000 0 0x100000>;
-+ };
-+
-+ /* other children */
-+ ...
-+
-+ internal-regs {
-+ compatible = "simple-bus";
-+ ranges = <0 0xf0010000 0 0x100000>;
-+
-+ mbusc: mbus-controller@20000 {
-+ compatible = "marvell,mbus-controller";
-+ reg = <0x20000 0x100>, <0x20180 0x20>;
-+ };
-+
-+ /* more children ...*/
-+ };
-+ };
-+
-+In the shown example, the translation entry in the 'ranges' property is what
-+makes the MBus driver create a static decoding window for the corresponding
-+given child device. Note that the binding does not require child nodes to be
-+present. Of course, child nodes are needed to probe the devices.
-+
-+Since each window is identified by its target ID and attribute ID there's
-+a special macro that can be use to simplify the translation entries:
-+
-+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
-+
-+Using this macro, the above example would be:
-+
-+ soc {
-+ compatible = "marvell,armada370-mbus", "simple-bus";
-+ #address-cells = <2>;
-+ #size-cells = <1>;
-+ controller = <&mbusc>;
-+
-+ ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
-+ MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
-+
-+ bootrom {
-+ compatible = "marvell,bootrom";
-+ reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
-+ };
-+
-+ /* other children */
-+ ...
-+
-+ internal-regs {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
-+
-+ mbusc: mbus-controller@20000 {
-+ compatible = "marvell,mbus-controller";
-+ reg = <0x20000 0x100>, <0x20180 0x20>;
-+ };
-+
-+ /* other children */
-+ ...
-+ };
-+ };
-+
-+
-+** About the window base address
-+
-+Remember the MBus controller allows a great deal of flexibility for choosing
-+the decoding window base address. When planning the device tree layout it's
-+possible to choose any address as the base address, provided of course there's
-+a region large enough available, and with the required alignment.
-+
-+Yet in other words: there's nothing preventing us from setting a base address
-+of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
-+unused.
-+
-+** Window allocation policy
-+
-+The mbus-node ranges property defines a set of mbus windows that are expected
-+to be set by the operating system and that are guaranteed to be free of overlaps
-+with one another or with the system memory ranges.
-+
-+Each entry in the property refers to exactly one window. If the operating system
-+choses to use a different set of mbus windows, it must ensure that any address
-+translations performed from downstream devices are adapted accordingly.
-+
-+The operating system may insert additional mbus windows that do not conflict
-+with the ones listed in the ranges, e.g. for mapping PCIe devices.
-+As a special case, the internal register window must be set up by the boot
-+loader at the address listed in the ranges property, since access to that region
-+is needed to set up the other windows.
-+
-+** Example
-+
-+See the example below, where a more complete device tree is shown:
-+
-+ soc {
-+ compatible = "marvell,armadaxp-mbus", "simple-bus";
-+ controller = <&mbusc>;
-+
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
-+
-+ bootrom {
-+ compatible = "marvell,bootrom";
-+ reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
-+ };
-+
-+ devbus-bootcs {
-+ status = "okay";
-+ ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
-+
-+ /* NOR */
-+ nor {
-+ compatible = "cfi-flash";
-+ reg = <0 0x8000000>;
-+ bank-width = <2>;
-+ };
-+ };
-+
-+ pcie-controller {
-+ compatible = "marvell,armada-xp-pcie";
-+ status = "okay";
-+ device_type = "pci";
-+
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ ranges =
-+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
-+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
-+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
-+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
-+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
-+ 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
-+ 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
-+
-+
-+ pcie@1,0 {
-+ /* Port 0, Lane 0 */
-+ status = "okay";
-+ };
-+ };
-+
-+ internal-regs {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
-+
-+ mbusc: mbus-controller@20000 {
-+ reg = <0x20000 0x100>, <0x20180 0x20>;
-+ };
-+
-+ interrupt-controller@20000 {
-+ reg = <0x20a00 0x2d0>, <0x21070 0x58>;
-+ };
-+ };
-+ };
+++ /dev/null
-From 60538f9841697cd4539d353afd8a7f51cd17e4af Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 5 Jul 2013 14:54:17 +0200
-Subject: [PATCH 066/203] PCI: mvebu: Adapt to the new device tree layout
-
-The new device tree layout encodes the window's target ID and attribute
-in the PCIe controller node's ranges property. This allows to parse
-such entries to obtain such information and use the recently introduced
-MBus API to create the windows, instead of using the current name based
-scheme.
-
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- .../devicetree/bindings/pci/mvebu-pci.txt | 145 ++++++++++++++++-----
- 1 file changed, 109 insertions(+), 36 deletions(-)
-
---- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
-+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
-@@ -1,6 +1,7 @@
- * Marvell EBU PCIe interfaces
-
- Mandatory properties:
-+
- - compatible: one of the following values:
- marvell,armada-370-pcie
- marvell,armada-xp-pcie
-@@ -9,11 +10,49 @@ Mandatory properties:
- - #interrupt-cells, set to <1>
- - bus-range: PCI bus numbers covered
- - device_type, set to "pci"
--- ranges: ranges for the PCI memory and I/O regions, as well as the
-- MMIO registers to control the PCIe interfaces.
-+- ranges: ranges describing the MMIO registers to control the PCIe
-+ interfaces, and ranges describing the MBus windows needed to access
-+ the memory and I/O regions of each PCIe interface.
-+
-+The ranges describing the MMIO registers have the following layout:
-+
-+ 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
-+
-+where:
-+
-+ * r is a 32-bits value that gives the offset of the MMIO
-+ registers of this PCIe interface, from the base of the internal
-+ registers.
-+
-+ * s is a 32-bits value that give the size of this MMIO
-+ registers area. This range entry translates the '0x82000000 0 r' PCI
-+ address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
-+ of the internal register window (as identified by MBUS_ID(0xf0,
-+ 0x01)).
-+
-+The ranges describing the MBus windows have the following layout:
-+
-+ 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
-+
-+where:
-
--In addition, the Device Tree node must have sub-nodes describing each
-+ * t is the type of the MBus window (as defined by the standard PCI DT
-+ bindings), 1 for I/O and 2 for memory.
-+
-+ * s is the PCI slot that corresponds to this PCIe interface
-+
-+ * w is the 'target ID' value for the MBus window
-+
-+ * a the 'attribute' value for the MBus window.
-+
-+Since the location and size of the different MBus windows is not fixed in
-+hardware, and only determined in runtime, those ranges cover the full first
-+4 GB of the physical address space, and do not translate into a valid CPU
-+address.
-+
-+In addition, the device tree node must have sub-nodes describing each
- PCIe interface, having the following mandatory properties:
-+
- - reg: used only for interrupt mapping, so only the first four bytes
- are used to refer to the correct bus number and device number.
- - assigned-addresses: reference to the MMIO registers used to control
-@@ -25,7 +64,8 @@ PCIe interface, having the following man
- - #address-cells, set to <3>
- - #size-cells, set to <2>
- - #interrupt-cells, set to <1>
--- ranges, empty property.
-+- ranges, translating the MBus windows ranges of the parent node into
-+ standard PCI addresses.
- - interrupt-map-mask and interrupt-map, standard PCI properties to
- define the mapping of the PCIe interface to interrupt numbers.
-
-@@ -46,27 +86,50 @@ pcie-controller {
-
- bus-range = <0x00 0xff>;
-
-- ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
-- 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
-- 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
-- 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
-- 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
-- 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
-- 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
-- 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
-- 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
-- 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
-- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
-- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-+ ranges =
-+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
-+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
-+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
-+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
-+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
-+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
-+ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
-+ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
-+ 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
-+ 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
-+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
-+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
-+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
-+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
-+ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
-+ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
-+ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
-+ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
-+
-+ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
-+ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
-+ 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
-+ 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
-+ 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
-+ 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
-+ 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
-+ 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
-+
-+ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
-+ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
-+
-+ 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
-+ 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
-
- pcie@1,0 {
- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
-+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
-+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
- marvell,pcie-port = <0>;
-@@ -77,12 +140,13 @@ pcie-controller {
-
- pcie@2,0 {
- device_type = "pci";
-- assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
-+ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
-+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
- marvell,pcie-port = <0>;
-@@ -93,12 +157,13 @@ pcie-controller {
-
- pcie@3,0 {
- device_type = "pci";
-- assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
-+ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
-+ 0x81000000 0 0 0x81000000 0x3 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
- marvell,pcie-port = <0>;
-@@ -109,12 +174,13 @@ pcie-controller {
-
- pcie@4,0 {
- device_type = "pci";
-- assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
-+ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
- reg = <0x2000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
-+ 0x81000000 0 0 0x81000000 0x4 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
- marvell,pcie-port = <0>;
-@@ -125,12 +191,13 @@ pcie-controller {
-
- pcie@5,0 {
- device_type = "pci";
-- assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
-+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
- reg = <0x2800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
-+ 0x81000000 0 0 0x81000000 0x5 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
- marvell,pcie-port = <1>;
-@@ -141,12 +208,13 @@ pcie-controller {
-
- pcie@6,0 {
- device_type = "pci";
-- assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
-+ assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
- reg = <0x3000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
-+ 0x81000000 0 0 0x81000000 0x6 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 63>;
- marvell,pcie-port = <1>;
-@@ -157,12 +225,13 @@ pcie-controller {
-
- pcie@7,0 {
- device_type = "pci";
-- assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
-+ assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
- reg = <0x3800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
-+ 0x81000000 0 0 0x81000000 0x7 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 64>;
- marvell,pcie-port = <1>;
-@@ -173,12 +242,13 @@ pcie-controller {
-
- pcie@8,0 {
- device_type = "pci";
-- assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
-+ assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
- reg = <0x4000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
-+ 0x81000000 0 0 0x81000000 0x8 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 65>;
- marvell,pcie-port = <1>;
-@@ -186,14 +256,16 @@ pcie-controller {
- clocks = <&gateclk 12>;
- status = "disabled";
- };
-+
- pcie@9,0 {
- device_type = "pci";
-- assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
-+ assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
- reg = <0x4800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
-+ 0x81000000 0 0 0x81000000 0x9 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
- marvell,pcie-port = <2>;
-@@ -204,12 +276,13 @@ pcie-controller {
-
- pcie@10,0 {
- device_type = "pci";
-- assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
-+ assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
- reg = <0x5000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
-+ 0x81000000 0 0 0x81000000 0xa 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 103>;
- marvell,pcie-port = <3>;
+++ /dev/null
-From cc4fb487fbf95c97b40e1e8e5b8b2ddabc8d124d Mon Sep 17 00:00:00 2001
-From: Willy Tarreau <w@1wt.eu>
-Date: Mon, 3 Jun 2013 18:47:36 +0200
-Subject: [PATCH 067/203] ARM: mvebu: set aliases for ethernet controllers
-
-These aliases are used when feeding the DT from ATAGS to set the
-devices MAC addresses.
-
-Signed-off-by: Willy Tarreau <w@1wt.eu>
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370-xp.dtsi | 9 +++++++--
- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 3 ++-
- arch/arm/boot/dts/armada-xp.dtsi | 6 +++++-
- 3 files changed, 14 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -24,6 +24,11 @@
- model = "Marvell Armada 370 and XP SoC";
- compatible = "marvell,armada-370-xp";
-
-+ aliases {
-+ eth0 = ð0;
-+ eth1 = ð1;
-+ };
-+
- cpus {
- cpu@0 {
- compatible = "marvell,sheeva-v7";
-@@ -151,7 +156,7 @@
- reg = <0x72004 0x4>;
- };
-
-- ethernet@70000 {
-+ eth0: ethernet@70000 {
- compatible = "marvell,armada-370-neta";
- reg = <0x70000 0x4000>;
- interrupts = <8>;
-@@ -159,7 +164,7 @@
- status = "disabled";
- };
-
-- ethernet@74000 {
-+ eth1: ethernet@74000 {
- compatible = "marvell,armada-370-neta";
- reg = <0x74000 0x4000>;
- interrupts = <10>;
---- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-@@ -23,6 +23,7 @@
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
-+ eth3 = ð3;
- };
-
-
-@@ -326,7 +327,7 @@
- interrupts = <91>;
- };
-
-- ethernet@34000 {
-+ eth3: ethernet@34000 {
- compatible = "marvell,armada-370-neta";
- reg = <0x34000 0x4000>;
- interrupts = <14>;
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -22,6 +22,10 @@
- model = "Marvell Armada XP family SoC";
- compatible = "marvell,armadaxp", "marvell,armada-370-xp";
-
-+ aliases {
-+ eth2 = ð2;
-+ };
-+
- soc {
- compatible = "marvell,armadaxp-mbus", "simple-bus";
-
-@@ -93,7 +97,7 @@
- reg = <0x18200 0x500>;
- };
-
-- ethernet@30000 {
-+ eth2: ethernet@30000 {
- compatible = "marvell,armada-370-neta";
- reg = <0x30000 0x4000>;
- interrupts = <12>;
+++ /dev/null
-From d967b31469239f610ea84b0a54ce296c15d860e9 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Tue, 30 Jul 2013 16:59:02 +0200
-Subject: [PATCH 068/203] ARM: mvebu: use correct #interrupt-cells instead of
- #interrupts-cells
-
-The Device Tree information for the GPIO banks of the Armada 370 and
-Armada XP SOCs was incorrectly using #interrupts-cells instead of
-controller when using GPIO interrupts, since the GPIO bank DT node
-wasn't recognized as a valid interrupt controller by the OF code.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370.dtsi | 6 +++---
- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 4 ++--
- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 6 +++---
- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 6 +++---
- 4 files changed, 11 insertions(+), 11 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -136,7 +136,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <82>, <83>, <84>, <85>;
- };
-
-@@ -147,7 +147,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <87>, <88>, <89>, <90>;
- };
-
-@@ -158,7 +158,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <91>;
- };
-
---- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-@@ -181,7 +181,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <82>, <83>, <84>, <85>;
- };
-
-@@ -192,7 +192,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <87>, <88>, <89>;
- };
-
---- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-@@ -203,7 +203,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <82>, <83>, <84>, <85>;
- };
-
-@@ -214,7 +214,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <87>, <88>, <89>, <90>;
- };
-
-@@ -225,7 +225,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <91>;
- };
-
---- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-@@ -301,7 +301,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <82>, <83>, <84>, <85>;
- };
-
-@@ -312,7 +312,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <87>, <88>, <89>, <90>;
- };
-
-@@ -323,7 +323,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupts-cells = <2>;
-+ #interrupt-cells = <2>;
- interrupts = <91>;
- };
-
+++ /dev/null
-From 3953e4230483d6ce51b9f7e3b20db30e5ca6f4da Mon Sep 17 00:00:00 2001
-From: Jason Cooper <jason@lakedaemon.net>
-Date: Wed, 7 Aug 2013 20:04:21 +0000
-Subject: [PATCH 069/203] ARM: mvebu: use dts pre-processor for mv78230
-
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-@@ -13,7 +13,7 @@
- * common to all Armada XP SoCs.
- */
-
--/include/ "armada-xp.dtsi"
-+#include "armada-xp.dtsi"
-
- / {
- model = "Marvell Armada XP MV78230 SoC";
+++ /dev/null
-From 4fb403ed86e78027a5b85333fa1491d5a0e68ae9 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 19 Jun 2013 09:42:32 +0200
-Subject: [PATCH 070/203] PCI: use weak functions for MSI arch-specific
- functions
-
-Until now, the MSI architecture-specific functions could be overloaded
-using a fairly complex set of #define and compile-time
-conditionals. In order to prepare for the introduction of the msi_chip
-infrastructure, it is desirable to switch all those functions to use
-the 'weak' mechanism. This commit converts all the architectures that
-were overidding those MSI functions to use the new strategy.
-
-Note that we keep two separate, non-weak, functions
-default_teardown_msi_irqs() and default_restore_msi_irqs() for the
-default behavior of the arch_teardown_msi_irqs() and
-arch_restore_msi_irqs(), as the default behavior is needed by x86 PCI
-code.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
-Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-Tested-by: Daniel Price <daniel.price@gmail.com>
-Tested-by: Thierry Reding <thierry.reding@gmail.com>
-Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-Cc: Paul Mackerras <paulus@samba.org>
-Cc: linuxppc-dev@lists.ozlabs.org
-Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
-Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
-Cc: linux390@de.ibm.com
-Cc: linux-s390@vger.kernel.org
-Cc: Thomas Gleixner <tglx@linutronix.de>
-Cc: Ingo Molnar <mingo@redhat.com>
-Cc: H. Peter Anvin <hpa@zytor.com>
-Cc: x86@kernel.org
-Cc: Russell King <linux@arm.linux.org.uk>
-Cc: Tony Luck <tony.luck@intel.com>
-Cc: Fenghua Yu <fenghua.yu@intel.com>
-Cc: linux-ia64@vger.kernel.org
-Cc: Ralf Baechle <ralf@linux-mips.org>
-Cc: linux-mips@linux-mips.org
-Cc: David S. Miller <davem@davemloft.net>
-Cc: sparclinux@vger.kernel.org
-Cc: Chris Metcalf <cmetcalf@tilera.com>
----
- arch/mips/include/asm/pci.h | 5 -----
- arch/powerpc/include/asm/pci.h | 5 -----
- arch/s390/include/asm/pci.h | 4 ----
- arch/x86/include/asm/pci.h | 30 --------------------------
- arch/x86/kernel/x86_init.c | 24 +++++++++++++++++++++
- drivers/pci/msi.c | 48 +++++++++++++++++++++---------------------
- include/linux/msi.h | 8 ++++++-
- 7 files changed, 55 insertions(+), 69 deletions(-)
-
---- a/arch/mips/include/asm/pci.h
-+++ b/arch/mips/include/asm/pci.h
-@@ -137,11 +137,6 @@ static inline int pci_get_legacy_ide_irq
- return channel ? 15 : 14;
- }
-
--#ifdef CONFIG_CPU_CAVIUM_OCTEON
--/* MSI arch hook for OCTEON */
--#define arch_setup_msi_irqs arch_setup_msi_irqs
--#endif
--
- extern char * (*pcibios_plat_setup)(char *str);
-
- #ifdef CONFIG_OF
---- a/arch/powerpc/include/asm/pci.h
-+++ b/arch/powerpc/include/asm/pci.h
-@@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus
- /* Decide whether to display the domain number in /proc */
- extern int pci_proc_domain(struct pci_bus *bus);
-
--/* MSI arch hooks */
--#define arch_setup_msi_irqs arch_setup_msi_irqs
--#define arch_teardown_msi_irqs arch_teardown_msi_irqs
--#define arch_msi_check_device arch_msi_check_device
--
- struct vm_area_struct;
- /* Map a range of PCI memory or I/O space for a device into user space */
- int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
---- a/arch/s390/include/asm/pci.h
-+++ b/arch/s390/include/asm/pci.h
-@@ -21,10 +21,6 @@ void pci_iounmap(struct pci_dev *, void
- int pci_domain_nr(struct pci_bus *);
- int pci_proc_domain(struct pci_bus *);
-
--/* MSI arch hooks */
--#define arch_setup_msi_irqs arch_setup_msi_irqs
--#define arch_teardown_msi_irqs arch_teardown_msi_irqs
--
- #define ZPCI_BUS_NR 0 /* default bus number */
- #define ZPCI_DEVFN 0 /* default device number */
-
---- a/arch/x86/include/asm/pci.h
-+++ b/arch/x86/include/asm/pci.h
-@@ -100,29 +100,6 @@ static inline void early_quirks(void) {
- extern void pci_iommu_alloc(void);
-
- #ifdef CONFIG_PCI_MSI
--/* MSI arch specific hooks */
--static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
--{
-- return x86_msi.setup_msi_irqs(dev, nvec, type);
--}
--
--static inline void x86_teardown_msi_irqs(struct pci_dev *dev)
--{
-- x86_msi.teardown_msi_irqs(dev);
--}
--
--static inline void x86_teardown_msi_irq(unsigned int irq)
--{
-- x86_msi.teardown_msi_irq(irq);
--}
--static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq)
--{
-- x86_msi.restore_msi_irqs(dev, irq);
--}
--#define arch_setup_msi_irqs x86_setup_msi_irqs
--#define arch_teardown_msi_irqs x86_teardown_msi_irqs
--#define arch_teardown_msi_irq x86_teardown_msi_irq
--#define arch_restore_msi_irqs x86_restore_msi_irqs
- /* implemented in arch/x86/kernel/apic/io_apic. */
- struct msi_desc;
- int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
-@@ -130,16 +107,9 @@ void native_teardown_msi_irq(unsigned in
- void native_restore_msi_irqs(struct pci_dev *dev, int irq);
- int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
- unsigned int irq_base, unsigned int irq_offset);
--/* default to the implementation in drivers/lib/msi.c */
--#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
--#define HAVE_DEFAULT_MSI_RESTORE_IRQS
--void default_teardown_msi_irqs(struct pci_dev *dev);
--void default_restore_msi_irqs(struct pci_dev *dev, int irq);
- #else
- #define native_setup_msi_irqs NULL
- #define native_teardown_msi_irq NULL
--#define default_teardown_msi_irqs NULL
--#define default_restore_msi_irqs NULL
- #endif
-
- #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
---- a/arch/x86/kernel/x86_init.c
-+++ b/arch/x86/kernel/x86_init.c
-@@ -107,6 +107,8 @@ struct x86_platform_ops x86_platform = {
- };
-
- EXPORT_SYMBOL_GPL(x86_platform);
-+
-+#if defined(CONFIG_PCI_MSI)
- struct x86_msi_ops x86_msi = {
- .setup_msi_irqs = native_setup_msi_irqs,
- .compose_msi_msg = native_compose_msi_msg,
-@@ -116,6 +118,28 @@ struct x86_msi_ops x86_msi = {
- .setup_hpet_msi = default_setup_hpet_msi,
- };
-
-+/* MSI arch specific hooks */
-+int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
-+{
-+ return x86_msi.setup_msi_irqs(dev, nvec, type);
-+}
-+
-+void arch_teardown_msi_irqs(struct pci_dev *dev)
-+{
-+ x86_msi.teardown_msi_irqs(dev);
-+}
-+
-+void arch_teardown_msi_irq(unsigned int irq)
-+{
-+ x86_msi.teardown_msi_irq(irq);
-+}
-+
-+void arch_restore_msi_irqs(struct pci_dev *dev, int irq)
-+{
-+ x86_msi.restore_msi_irqs(dev, irq);
-+}
-+#endif
-+
- struct x86_io_apic_ops x86_io_apic_ops = {
- .init = native_io_apic_init_mappings,
- .read = native_io_apic_read,
---- a/drivers/pci/msi.c
-+++ b/drivers/pci/msi.c
-@@ -30,20 +30,21 @@ static int pci_msi_enable = 1;
-
- /* Arch hooks */
-
--#ifndef arch_msi_check_device
--int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
-+int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
-+{
-+ return -EINVAL;
-+}
-+
-+void __weak arch_teardown_msi_irq(unsigned int irq)
- {
-- return 0;
- }
--#endif
-
--#ifndef arch_setup_msi_irqs
--# define arch_setup_msi_irqs default_setup_msi_irqs
--# define HAVE_DEFAULT_MSI_SETUP_IRQS
--#endif
-+int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
-+{
-+ return 0;
-+}
-
--#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
--int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
-+int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
- {
- struct msi_desc *entry;
- int ret;
-@@ -65,14 +66,11 @@ int default_setup_msi_irqs(struct pci_de
-
- return 0;
- }
--#endif
-
--#ifndef arch_teardown_msi_irqs
--# define arch_teardown_msi_irqs default_teardown_msi_irqs
--# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
--#endif
--
--#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
-+/*
-+ * We have a default implementation available as a separate non-weak
-+ * function, as it is used by the Xen x86 PCI code
-+ */
- void default_teardown_msi_irqs(struct pci_dev *dev)
- {
- struct msi_desc *entry;
-@@ -86,14 +84,12 @@ void default_teardown_msi_irqs(struct pc
- arch_teardown_msi_irq(entry->irq + i);
- }
- }
--#endif
-
--#ifndef arch_restore_msi_irqs
--# define arch_restore_msi_irqs default_restore_msi_irqs
--# define HAVE_DEFAULT_MSI_RESTORE_IRQS
--#endif
-+void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
-+{
-+ return default_teardown_msi_irqs(dev);
-+}
-
--#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
- void default_restore_msi_irqs(struct pci_dev *dev, int irq)
- {
- struct msi_desc *entry;
-@@ -111,7 +107,11 @@ void default_restore_msi_irqs(struct pci
- if (entry)
- write_msi_msg(irq, &entry->msg);
- }
--#endif
-+
-+void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq)
-+{
-+ return default_restore_msi_irqs(dev, irq);
-+}
-
- static void msi_set_enable(struct pci_dev *dev, int enable)
- {
---- a/include/linux/msi.h
-+++ b/include/linux/msi.h
-@@ -50,12 +50,18 @@ struct msi_desc {
- };
-
- /*
-- * The arch hook for setup up msi irqs
-+ * The arch hooks to setup up msi irqs. Those functions are
-+ * implemented as weak symbols so that they /can/ be overriden by
-+ * architecture specific code if needed.
- */
- int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
- void arch_teardown_msi_irq(unsigned int irq);
- int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
- void arch_teardown_msi_irqs(struct pci_dev *dev);
- int arch_msi_check_device(struct pci_dev* dev, int nvec, int type);
-+void arch_restore_msi_irqs(struct pci_dev *dev, int irq);
-+
-+void default_teardown_msi_irqs(struct pci_dev *dev);
-+void default_restore_msi_irqs(struct pci_dev *dev, int irq);
-
- #endif /* LINUX_MSI_H */
+++ /dev/null
-From c819a1b0907257d73de96af33d557668a5c0c895 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Mon, 1 Jul 2013 14:26:57 +0200
-Subject: [PATCH 071/203] PCI: remove ARCH_SUPPORTS_MSI kconfig option
-
-Now that we have weak versions for each of the PCI MSI architecture
-functions, we can actually build the MSI support for all platforms,
-regardless of whether they provide or not architecture-specific
-versions of those functions. For this reason, the ARCH_SUPPORTS_MSI
-hidden kconfig boolean becomes useless, and this patch gets rid of it.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
-Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-Tested-by: Daniel Price <daniel.price@gmail.com>
-Tested-by: Thierry Reding <thierry.reding@gmail.com>
-Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-Cc: Paul Mackerras <paulus@samba.org>
-Cc: linuxppc-dev@lists.ozlabs.org
-Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
-Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
-Cc: linux390@de.ibm.com
-Cc: linux-s390@vger.kernel.org
-Cc: Thomas Gleixner <tglx@linutronix.de>
-Cc: Ingo Molnar <mingo@redhat.com>
-Cc: H. Peter Anvin <hpa@zytor.com>
-Cc: x86@kernel.org
-Cc: Russell King <linux@arm.linux.org.uk>
-Cc: Tony Luck <tony.luck@intel.com>
-Cc: Fenghua Yu <fenghua.yu@intel.com>
-Cc: linux-ia64@vger.kernel.org
-Cc: Ralf Baechle <ralf@linux-mips.org>
-Cc: linux-mips@linux-mips.org
-Cc: David S. Miller <davem@davemloft.net>
-Cc: sparclinux@vger.kernel.org
-Cc: Chris Metcalf <cmetcalf@tilera.com>
----
- arch/arm/Kconfig | 1 -
- arch/ia64/Kconfig | 1 -
- arch/mips/Kconfig | 2 --
- arch/powerpc/Kconfig | 1 -
- arch/s390/Kconfig | 1 -
- arch/sparc/Kconfig | 1 -
- arch/tile/Kconfig | 1 -
- arch/x86/Kconfig | 1 -
- drivers/pci/Kconfig | 4 ----
- 9 files changed, 13 deletions(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -435,7 +435,6 @@ config ARCH_NETX
- config ARCH_IOP13XX
- bool "IOP13xx-based"
- depends on MMU
-- select ARCH_SUPPORTS_MSI
- select CPU_XSC3
- select NEED_MACH_MEMORY_H
- select NEED_RET_TO_USER
---- a/arch/ia64/Kconfig
-+++ b/arch/ia64/Kconfig
-@@ -9,7 +9,6 @@ config IA64
- select PCI if (!IA64_HP_SIM)
- select ACPI if (!IA64_HP_SIM)
- select PM if (!IA64_HP_SIM)
-- select ARCH_SUPPORTS_MSI
- select HAVE_UNSTABLE_SCHED_CLOCK
- select HAVE_IDE
- select HAVE_OPROFILE
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -764,7 +764,6 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
- select SYS_HAS_CPU_CAVIUM_OCTEON
- select SWAP_IO_SPACE
- select HW_HAS_PCI
-- select ARCH_SUPPORTS_MSI
- select ZONE_DMA32
- select USB_ARCH_HAS_OHCI
- select USB_ARCH_HAS_EHCI
-@@ -800,7 +799,6 @@ config NLM_XLR_BOARD
- select CEVT_R4K
- select CSRC_R4K
- select IRQ_CPU
-- select ARCH_SUPPORTS_MSI
- select ZONE_DMA32 if 64BIT
- select SYNC_R4K
- select SYS_HAS_EARLY_PRINTK
---- a/arch/powerpc/Kconfig
-+++ b/arch/powerpc/Kconfig
-@@ -734,7 +734,6 @@ config PCI
- default y if !40x && !CPM2 && !8xx && !PPC_83xx \
- && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON
- default PCI_QSPAN if !4xx && !CPM2 && 8xx
-- select ARCH_SUPPORTS_MSI
- select GENERIC_PCI_IOMAP
- help
- Find out whether your system includes a PCI bus. PCI is the name of
---- a/arch/s390/Kconfig
-+++ b/arch/s390/Kconfig
-@@ -430,7 +430,6 @@ menuconfig PCI
- bool "PCI support"
- default n
- depends on 64BIT
-- select ARCH_SUPPORTS_MSI
- select PCI_MSI
- help
- Enable PCI support.
---- a/arch/sparc/Kconfig
-+++ b/arch/sparc/Kconfig
-@@ -52,7 +52,6 @@ config SPARC32
-
- config SPARC64
- def_bool 64BIT
-- select ARCH_SUPPORTS_MSI
- select HAVE_FUNCTION_TRACER
- select HAVE_FUNCTION_GRAPH_TRACER
- select HAVE_FUNCTION_GRAPH_FP_TEST
---- a/arch/tile/Kconfig
-+++ b/arch/tile/Kconfig
-@@ -379,7 +379,6 @@ config PCI
- select PCI_DOMAINS
- select GENERIC_PCI_IOMAP
- select TILE_GXIO_TRIO if TILEGX
-- select ARCH_SUPPORTS_MSI if TILEGX
- select PCI_MSI if TILEGX
- ---help---
- Enable PCI root complex support, so PCIe endpoint devices can
---- a/arch/x86/Kconfig
-+++ b/arch/x86/Kconfig
-@@ -1999,7 +1999,6 @@ menu "Bus options (PCI etc.)"
- config PCI
- bool "PCI support"
- default y
-- select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC)
- ---help---
- Find out whether you have a PCI motherboard. PCI is the name of a
- bus system, i.e. the way the CPU talks to the other stuff inside
---- a/drivers/pci/Kconfig
-+++ b/drivers/pci/Kconfig
-@@ -1,13 +1,9 @@
- #
- # PCI configuration
- #
--config ARCH_SUPPORTS_MSI
-- bool
--
- config PCI_MSI
- bool "Message Signaled Interrupts (MSI and MSI-X)"
- depends on PCI
-- depends on ARCH_SUPPORTS_MSI
- help
- This allows device drivers to enable MSI (Message Signaled
- Interrupts). Message Signaled Interrupts enable a device to
+++ /dev/null
-From 9c6ddccbbfaf789beccc6a1d87abe9bc60dc570f Mon Sep 17 00:00:00 2001
-From: Thierry Reding <thierry.reding@avionic-design.de>
-Date: Thu, 6 Jun 2013 18:20:29 +0200
-Subject: [PATCH 072/203] PCI: Introduce new MSI chip infrastructure
-
-The new struct msi_chip is used to associated an MSI controller with a
-PCI bus. It is automatically handed down from the root to its children
-during bus enumeration.
-
-This patch provides default (weak) implementations for the architecture-
-specific MSI functions (arch_setup_msi_irq(), arch_teardown_msi_irq()
-and arch_msi_check_device()) which check if a PCI device's bus has an
-attached MSI chip and forward the call appropriately.
-
-Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
-Tested-by: Daniel Price <daniel.price@gmail.com>
-Tested-by: Thierry Reding <thierry.reding@gmail.com>
----
- drivers/pci/msi.c | 27 +++++++++++++++++++++++++--
- drivers/pci/probe.c | 1 +
- include/linux/msi.h | 11 +++++++++++
- include/linux/pci.h | 1 +
- 4 files changed, 38 insertions(+), 2 deletions(-)
-
---- a/drivers/pci/msi.c
-+++ b/drivers/pci/msi.c
-@@ -32,16 +32,39 @@ static int pci_msi_enable = 1;
-
- int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
- {
-- return -EINVAL;
-+ struct msi_chip *chip = dev->bus->msi;
-+ int err;
-+
-+ if (!chip || !chip->setup_irq)
-+ return -EINVAL;
-+
-+ err = chip->setup_irq(chip, dev, desc);
-+ if (err < 0)
-+ return err;
-+
-+ irq_set_chip_data(desc->irq, chip);
-+
-+ return 0;
- }
-
- void __weak arch_teardown_msi_irq(unsigned int irq)
- {
-+ struct msi_chip *chip = irq_get_chip_data(irq);
-+
-+ if (!chip || !chip->teardown_irq)
-+ return;
-+
-+ chip->teardown_irq(chip, irq);
- }
-
- int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
- {
-- return 0;
-+ struct msi_chip *chip = dev->bus->msi;
-+
-+ if (!chip || !chip->check_device)
-+ return 0;
-+
-+ return chip->check_device(chip, dev, nvec, type);
- }
-
- int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
---- a/drivers/pci/probe.c
-+++ b/drivers/pci/probe.c
-@@ -634,6 +634,7 @@ static struct pci_bus *pci_alloc_child_b
-
- child->parent = parent;
- child->ops = parent->ops;
-+ child->msi = parent->msi;
- child->sysdata = parent->sysdata;
- child->bus_flags = parent->bus_flags;
-
---- a/include/linux/msi.h
-+++ b/include/linux/msi.h
-@@ -64,4 +64,15 @@ void arch_restore_msi_irqs(struct pci_de
- void default_teardown_msi_irqs(struct pci_dev *dev);
- void default_restore_msi_irqs(struct pci_dev *dev, int irq);
-
-+struct msi_chip {
-+ struct module *owner;
-+ struct device *dev;
-+
-+ int (*setup_irq)(struct msi_chip *chip, struct pci_dev *dev,
-+ struct msi_desc *desc);
-+ void (*teardown_irq)(struct msi_chip *chip, unsigned int irq);
-+ int (*check_device)(struct msi_chip *chip, struct pci_dev *dev,
-+ int nvec, int type);
-+};
-+
- #endif /* LINUX_MSI_H */
---- a/include/linux/pci.h
-+++ b/include/linux/pci.h
-@@ -432,6 +432,7 @@ struct pci_bus {
- struct resource busn_res; /* bus numbers routed to this bus */
-
- struct pci_ops *ops; /* configuration access functions */
-+ struct msi_chip *msi; /* MSI controller */
- void *sysdata; /* hook for sys-specific extension */
- struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
-
+++ /dev/null
-From a05852e828063b6731fcac543b87367c137c16f8 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 6 Jun 2013 18:21:18 +0200
-Subject: [PATCH 073/203] of: pci: add registry of MSI chips
-
-This commit adds a very basic registry of msi_chip structures, so that
-an IRQ controller driver can register an msi_chip, and a PCIe host
-controller can find it, based on a 'struct device_node'.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-Acked-by: Rob Herring <rob.herring@calxeda.com>
----
- drivers/of/of_pci.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
- include/linux/msi.h | 2 ++
- include/linux/of_pci.h | 12 ++++++++++++
- 3 files changed, 59 insertions(+)
-
---- a/drivers/of/of_pci.c
-+++ b/drivers/of/of_pci.c
-@@ -89,3 +89,48 @@ int of_pci_parse_bus_range(struct device
- return 0;
- }
- EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
-+
-+#ifdef CONFIG_PCI_MSI
-+
-+static LIST_HEAD(of_pci_msi_chip_list);
-+static DEFINE_MUTEX(of_pci_msi_chip_mutex);
-+
-+int of_pci_msi_chip_add(struct msi_chip *chip)
-+{
-+ if (!of_property_read_bool(chip->of_node, "msi-controller"))
-+ return -EINVAL;
-+
-+ mutex_lock(&of_pci_msi_chip_mutex);
-+ list_add(&chip->list, &of_pci_msi_chip_list);
-+ mutex_unlock(&of_pci_msi_chip_mutex);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(of_pci_msi_chip_add);
-+
-+void of_pci_msi_chip_remove(struct msi_chip *chip)
-+{
-+ mutex_lock(&of_pci_msi_chip_mutex);
-+ list_del(&chip->list);
-+ mutex_unlock(&of_pci_msi_chip_mutex);
-+}
-+EXPORT_SYMBOL_GPL(of_pci_msi_chip_remove);
-+
-+struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node *of_node)
-+{
-+ struct msi_chip *c;
-+
-+ mutex_lock(&of_pci_msi_chip_mutex);
-+ list_for_each_entry(c, &of_pci_msi_chip_list, list) {
-+ if (c->of_node == of_node) {
-+ mutex_unlock(&of_pci_msi_chip_mutex);
-+ return c;
-+ }
-+ }
-+ mutex_unlock(&of_pci_msi_chip_mutex);
-+
-+ return NULL;
-+}
-+EXPORT_SYMBOL_GPL(of_pci_find_msi_chip_by_node);
-+
-+#endif /* CONFIG_PCI_MSI */
---- a/include/linux/msi.h
-+++ b/include/linux/msi.h
-@@ -67,6 +67,8 @@ void default_restore_msi_irqs(struct pci
- struct msi_chip {
- struct module *owner;
- struct device *dev;
-+ struct device_node *of_node;
-+ struct list_head list;
-
- int (*setup_irq)(struct msi_chip *chip, struct pci_dev *dev,
- struct msi_desc *desc);
---- a/include/linux/of_pci.h
-+++ b/include/linux/of_pci.h
-@@ -2,6 +2,7 @@
- #define __OF_PCI_H
-
- #include <linux/pci.h>
-+#include <linux/msi.h>
-
- struct pci_dev;
- struct of_irq;
-@@ -13,4 +14,15 @@ struct device_node *of_pci_find_child_de
- int of_pci_get_devfn(struct device_node *np);
- int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
-
-+#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI)
-+int of_pci_msi_chip_add(struct msi_chip *chip);
-+void of_pci_msi_chip_remove(struct msi_chip *chip);
-+struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node *of_node);
-+#else
-+static inline int of_pci_msi_chip_add(struct msi_chip *chip) { return -EINVAL; }
-+static inline void of_pci_msi_chip_remove(struct msi_chip *chip) { }
-+static inline struct msi_chip *
-+of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL; }
-+#endif
-+
- #endif
+++ /dev/null
-From c8efa45217cbd780dafe12d87b61554c2e19a010 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 6 Jun 2013 18:22:51 +0200
-Subject: [PATCH 074/203] irqchip: armada-370-xp: properly request resources
-
-Instead of using of_iomap(), we now use of_address_to_resource(),
-request_mem_region() and ioremap(). This allows the corresponding I/O
-regions to be properly requested and visible in /proc/iomem.
-
-The main motivation for this change is that the introduction of the
-MSI support requires us to get the physical address of the main
-interrupt controller registers, so we will need the corresponding
-'struct resource' anyway.
-
-We also take this opportunity to change a panic() to BUG_ON(), in
-order to be consistent with the rest of the driver.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Daniel Price <daniel.price@gmail.com>
-Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
----
- drivers/irqchip/irq-armada-370-xp.c | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/drivers/irqchip/irq-armada-370-xp.c
-+++ b/drivers/irqchip/irq-armada-370-xp.c
-@@ -248,12 +248,25 @@ armada_370_xp_handle_irq(struct pt_regs
- static int __init armada_370_xp_mpic_of_init(struct device_node *node,
- struct device_node *parent)
- {
-+ struct resource main_int_res, per_cpu_int_res;
- u32 control;
-
-- main_int_base = of_iomap(node, 0);
-- per_cpu_int_base = of_iomap(node, 1);
-+ BUG_ON(of_address_to_resource(node, 0, &main_int_res));
-+ BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
-
-+ BUG_ON(!request_mem_region(main_int_res.start,
-+ resource_size(&main_int_res),
-+ node->full_name));
-+ BUG_ON(!request_mem_region(per_cpu_int_res.start,
-+ resource_size(&per_cpu_int_res),
-+ node->full_name));
-+
-+ main_int_base = ioremap(main_int_res.start,
-+ resource_size(&main_int_res));
- BUG_ON(!main_int_base);
-+
-+ per_cpu_int_base = ioremap(per_cpu_int_res.start,
-+ resource_size(&per_cpu_int_res));
- BUG_ON(!per_cpu_int_base);
-
- control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
-@@ -262,8 +275,7 @@ static int __init armada_370_xp_mpic_of_
- irq_domain_add_linear(node, (control >> 2) & 0x3ff,
- &armada_370_xp_mpic_irq_ops, NULL);
-
-- if (!armada_370_xp_mpic_domain)
-- panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
-+ BUG_ON(!armada_370_xp_mpic_domain);
-
- irq_set_default_host(armada_370_xp_mpic_domain);
-
+++ /dev/null
-From eaa70d53f6b827f147d775a3de7ff3ef27d0fae6 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 6 Jun 2013 18:25:16 +0200
-Subject: [PATCH 075/203] irqchip: armada-370-xp: implement MSI support
-
-This commit introduces the support for the MSI interrupts in the
-armada-370-xp interrupt controller driver. It registers an MSI chip to
-the MSI chip registry, which will be used by the Marvell PCIe host
-controller driver.
-
-The MSI interrupts use the 16 high doorbells, and are therefore
-notified using IRQ1 of the main interrupt controller.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
----
- .../devicetree/bindings/arm/armada-370-xp-mpic.txt | 3 +
- drivers/irqchip/irq-armada-370-xp.c | 182 ++++++++++++++++++++-
- 2 files changed, 184 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
-+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
-@@ -4,6 +4,8 @@ Marvell Armada 370 and Armada XP Interru
- Required properties:
- - compatible: Should be "marvell,mpic"
- - interrupt-controller: Identifies the node as an interrupt controller.
-+- msi-controller: Identifies the node as an PCI Message Signaled
-+ Interrupt controller.
- - #interrupt-cells: The number of cells to define the interrupts. Should be 1.
- The cell is the IRQ number
-
-@@ -24,6 +26,7 @@ Example:
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-controller;
-+ msi-controller;
- reg = <0xd0020a00 0x1d0>,
- <0xd0021070 0x58>;
- };
---- a/drivers/irqchip/irq-armada-370-xp.c
-+++ b/drivers/irqchip/irq-armada-370-xp.c
-@@ -21,7 +21,10 @@
- #include <linux/io.h>
- #include <linux/of_address.h>
- #include <linux/of_irq.h>
-+#include <linux/of_pci.h>
- #include <linux/irqdomain.h>
-+#include <linux/slab.h>
-+#include <linux/msi.h>
- #include <asm/mach/arch.h>
- #include <asm/exception.h>
- #include <asm/smp_plat.h>
-@@ -51,12 +54,22 @@
- #define IPI_DOORBELL_START (0)
- #define IPI_DOORBELL_END (8)
- #define IPI_DOORBELL_MASK 0xFF
-+#define PCI_MSI_DOORBELL_START (16)
-+#define PCI_MSI_DOORBELL_NR (16)
-+#define PCI_MSI_DOORBELL_END (32)
-+#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
-
- static DEFINE_RAW_SPINLOCK(irq_controller_lock);
-
- static void __iomem *per_cpu_int_base;
- static void __iomem *main_int_base;
- static struct irq_domain *armada_370_xp_mpic_domain;
-+#ifdef CONFIG_PCI_MSI
-+static struct irq_domain *armada_370_xp_msi_domain;
-+static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
-+static DEFINE_MUTEX(msi_used_lock);
-+static phys_addr_t msi_doorbell_addr;
-+#endif
-
- /*
- * In SMP mode:
-@@ -87,6 +100,144 @@ static void armada_370_xp_irq_unmask(str
- ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
- }
-
-+#ifdef CONFIG_PCI_MSI
-+
-+static int armada_370_xp_alloc_msi(void)
-+{
-+ int hwirq;
-+
-+ mutex_lock(&msi_used_lock);
-+ hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
-+ if (hwirq >= PCI_MSI_DOORBELL_NR)
-+ hwirq = -ENOSPC;
-+ else
-+ set_bit(hwirq, msi_used);
-+ mutex_unlock(&msi_used_lock);
-+
-+ return hwirq;
-+}
-+
-+static void armada_370_xp_free_msi(int hwirq)
-+{
-+ mutex_lock(&msi_used_lock);
-+ if (!test_bit(hwirq, msi_used))
-+ pr_err("trying to free unused MSI#%d\n", hwirq);
-+ else
-+ clear_bit(hwirq, msi_used);
-+ mutex_unlock(&msi_used_lock);
-+}
-+
-+static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
-+ struct pci_dev *pdev,
-+ struct msi_desc *desc)
-+{
-+ struct msi_msg msg;
-+ irq_hw_number_t hwirq;
-+ int virq;
-+
-+ hwirq = armada_370_xp_alloc_msi();
-+ if (hwirq < 0)
-+ return hwirq;
-+
-+ virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
-+ if (!virq) {
-+ armada_370_xp_free_msi(hwirq);
-+ return -EINVAL;
-+ }
-+
-+ irq_set_msi_desc(virq, desc);
-+
-+ msg.address_lo = msi_doorbell_addr;
-+ msg.address_hi = 0;
-+ msg.data = 0xf00 | (hwirq + 16);
-+
-+ write_msi_msg(virq, &msg);
-+ return 0;
-+}
-+
-+static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
-+ unsigned int irq)
-+{
-+ struct irq_data *d = irq_get_irq_data(irq);
-+ irq_dispose_mapping(irq);
-+ armada_370_xp_free_msi(d->hwirq);
-+}
-+
-+static struct irq_chip armada_370_xp_msi_irq_chip = {
-+ .name = "armada_370_xp_msi_irq",
-+ .irq_enable = unmask_msi_irq,
-+ .irq_disable = mask_msi_irq,
-+ .irq_mask = mask_msi_irq,
-+ .irq_unmask = unmask_msi_irq,
-+};
-+
-+static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
-+ irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
-+ handle_simple_irq);
-+ set_irq_flags(virq, IRQF_VALID);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
-+ .map = armada_370_xp_msi_map,
-+};
-+
-+static int armada_370_xp_msi_init(struct device_node *node,
-+ phys_addr_t main_int_phys_base)
-+{
-+ struct msi_chip *msi_chip;
-+ u32 reg;
-+ int ret;
-+
-+ msi_doorbell_addr = main_int_phys_base +
-+ ARMADA_370_XP_SW_TRIG_INT_OFFS;
-+
-+ msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
-+ if (!msi_chip)
-+ return -ENOMEM;
-+
-+ msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
-+ msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
-+ msi_chip->of_node = node;
-+
-+ armada_370_xp_msi_domain =
-+ irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
-+ &armada_370_xp_msi_irq_ops,
-+ NULL);
-+ if (!armada_370_xp_msi_domain) {
-+ kfree(msi_chip);
-+ return -ENOMEM;
-+ }
-+
-+ ret = of_pci_msi_chip_add(msi_chip);
-+ if (ret < 0) {
-+ irq_domain_remove(armada_370_xp_msi_domain);
-+ kfree(msi_chip);
-+ return ret;
-+ }
-+
-+ reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
-+ | PCI_MSI_DOORBELL_MASK;
-+
-+ writel(reg, per_cpu_int_base +
-+ ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
-+
-+ /* Unmask IPI interrupt */
-+ writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
-+
-+ return 0;
-+}
-+#else
-+static inline int armada_370_xp_msi_init(struct device_node *node,
-+ phys_addr_t main_int_phys_base)
-+{
-+ return 0;
-+}
-+#endif
-+
- #ifdef CONFIG_SMP
- static int armada_xp_set_affinity(struct irq_data *d,
- const struct cpumask *mask_val, bool force)
-@@ -214,12 +365,39 @@ armada_370_xp_handle_irq(struct pt_regs
- if (irqnr > 1022)
- break;
-
-- if (irqnr > 0) {
-+ if (irqnr > 1) {
- irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
- irqnr);
- handle_IRQ(irqnr, regs);
- continue;
- }
-+
-+#ifdef CONFIG_PCI_MSI
-+ /* MSI handling */
-+ if (irqnr == 1) {
-+ u32 msimask, msinr;
-+
-+ msimask = readl_relaxed(per_cpu_int_base +
-+ ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
-+ & PCI_MSI_DOORBELL_MASK;
-+
-+ writel(~PCI_MSI_DOORBELL_MASK, per_cpu_int_base +
-+ ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
-+
-+ for (msinr = PCI_MSI_DOORBELL_START;
-+ msinr < PCI_MSI_DOORBELL_END; msinr++) {
-+ int irq;
-+
-+ if (!(msimask & BIT(msinr)))
-+ continue;
-+
-+ irq = irq_find_mapping(armada_370_xp_msi_domain,
-+ msinr - 16);
-+ handle_IRQ(irq, regs);
-+ }
-+ }
-+#endif
-+
- #ifdef CONFIG_SMP
- /* IPI Handling */
- if (irqnr == 0) {
-@@ -292,6 +470,8 @@ static int __init armada_370_xp_mpic_of_
-
- #endif
-
-+ armada_370_xp_msi_init(node, main_int_res.start);
-+
- set_handle_irq(armada_370_xp_handle_irq);
-
- return 0;
+++ /dev/null
-From ea6a42a34462ea382209ff4f083b8b17260eb409 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 19 Jun 2013 18:27:20 +0200
-Subject: [PATCH 076/203] ARM: pci: add ->add_bus() and ->remove_bus() hooks to
- hw_pci
-
-Some PCI drivers may need to adjust the pci_bus structure after it has
-been allocated by the Linux PCI core. The PCI core allows
-architectures to implement the pcibios_add_bus() and
-pcibios_remove_bus() for this purpose. This commit therefore extends
-the hw_pci and pci_sys_data structures of the ARM PCI core to allow
-PCI drivers to register ->add_bus() and ->remove_bus() in hw_pci,
-which will get called when a bus is added or removed from the system.
-
-This will be used for example by the Marvell PCIe driver to connect a
-particular PCI bus with its corresponding MSI chip to handle Message
-Signaled Interrupts.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Reviewed-by: Thierry Reding <thierry.reding@gmail.com>
-Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
-Tested-by: Daniel Price <daniel.price@gmail.com>
-Tested-by: Thierry Reding <thierry.reding@gmail.com>
----
- arch/arm/include/asm/mach/pci.h | 4 ++++
- arch/arm/kernel/bios32.c | 16 ++++++++++++++++
- 2 files changed, 20 insertions(+)
-
---- a/arch/arm/include/asm/mach/pci.h
-+++ b/arch/arm/include/asm/mach/pci.h
-@@ -35,6 +35,8 @@ struct hw_pci {
- resource_size_t start,
- resource_size_t size,
- resource_size_t align);
-+ void (*add_bus)(struct pci_bus *bus);
-+ void (*remove_bus)(struct pci_bus *bus);
- };
-
- /*
-@@ -62,6 +64,8 @@ struct pci_sys_data {
- resource_size_t start,
- resource_size_t size,
- resource_size_t align);
-+ void (*add_bus)(struct pci_bus *bus);
-+ void (*remove_bus)(struct pci_bus *bus);
- void *private_data; /* platform controller private data */
- };
-
---- a/arch/arm/kernel/bios32.c
-+++ b/arch/arm/kernel/bios32.c
-@@ -363,6 +363,20 @@ void pcibios_fixup_bus(struct pci_bus *b
- }
- EXPORT_SYMBOL(pcibios_fixup_bus);
-
-+void pcibios_add_bus(struct pci_bus *bus)
-+{
-+ struct pci_sys_data *sys = bus->sysdata;
-+ if (sys->add_bus)
-+ sys->add_bus(bus);
-+}
-+
-+void pcibios_remove_bus(struct pci_bus *bus)
-+{
-+ struct pci_sys_data *sys = bus->sysdata;
-+ if (sys->remove_bus)
-+ sys->remove_bus(bus);
-+}
-+
- /*
- * Swizzle the device pin each time we cross a bridge. If a platform does
- * not provide a swizzle function, we perform the standard PCI swizzling.
-@@ -463,6 +477,8 @@ static void pcibios_init_hw(struct hw_pc
- sys->swizzle = hw->swizzle;
- sys->map_irq = hw->map_irq;
- sys->align_resource = hw->align_resource;
-+ sys->add_bus = hw->add_bus;
-+ sys->remove_bus = hw->remove_bus;
- INIT_LIST_HEAD(&sys->resources);
-
- if (hw->private_data)
+++ /dev/null
-From 2ae5acab1c267ef1c5e61e5086b93fba8eb9752e Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 6 Jun 2013 18:26:29 +0200
-Subject: [PATCH 077/203] ARM: mvebu: the MPIC now provides MSI controller
- features
-
-Adds the 'msi-controller' property to the main interrupt controller
-Device Tree node, to indicate that it can now behave as a MSI
-controller.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Reviewed-by: Thierry Reding <thierry.reding@gmail.com>
-Tested-by: Daniel Price <daniel.price@gmail.com>
-Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
----
- arch/arm/boot/dts/armada-370-xp.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -109,6 +109,7 @@
- #interrupt-cells = <1>;
- #size-cells = <1>;
- interrupt-controller;
-+ msi-controller;
- };
-
- coherency-fabric@20200 {
+++ /dev/null
-From be448338edda73460dc3e8c005b17edddf1c1b4f Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 6 Jun 2013 18:27:16 +0200
-Subject: [PATCH 078/203] PCI: mvebu: add support for MSI
-
-This commit adds support for Message Signaled Interrupts in the
-Marvell PCIe host controller. The work is very simple: it simply gets
-a reference to the msi_chip associated to the PCIe controller thanks
-to the msi-parent DT property, and stores this reference in the
-pci_bus structure. This is enough to let the Linux PCI core use the
-functions of msi_chip to setup and teardown MSIs.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Reviewed-by: Thierry Reding <thierry.reding@gmail.com>
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
----
- .../devicetree/bindings/pci/mvebu-pci.txt | 3 +++
- drivers/pci/host/pci-mvebu.c | 26 ++++++++++++++++++++++
- 2 files changed, 29 insertions(+)
-
---- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
-+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
-@@ -14,6 +14,8 @@ Mandatory properties:
- interfaces, and ranges describing the MBus windows needed to access
- the memory and I/O regions of each PCIe interface.
-
-+- msi-parent: Link to the hardware entity that serves as the Message
-+ Signaled Interrupt controller for this PCI controller.
- The ranges describing the MMIO registers have the following layout:
-
- 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
-@@ -85,6 +87,7 @@ pcie-controller {
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-+ msi-parent = <&mpic>;
-
- ranges =
- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -11,6 +11,7 @@
- #include <linux/clk.h>
- #include <linux/module.h>
- #include <linux/mbus.h>
-+#include <linux/msi.h>
- #include <linux/slab.h>
- #include <linux/platform_device.h>
- #include <linux/of_address.h>
-@@ -103,6 +104,7 @@ struct mvebu_pcie_port;
- struct mvebu_pcie {
- struct platform_device *pdev;
- struct mvebu_pcie_port *ports;
-+ struct msi_chip *msi;
- struct resource io;
- struct resource realio;
- struct resource mem;
-@@ -673,6 +675,12 @@ static struct pci_bus *mvebu_pcie_scan_b
- return bus;
- }
-
-+void mvebu_pcie_add_bus(struct pci_bus *bus)
-+{
-+ struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
-+ bus->msi = pcie->msi;
-+}
-+
- resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
- const struct resource *res,
- resource_size_t start,
-@@ -709,6 +717,7 @@ static void __init mvebu_pcie_enable(str
- hw.map_irq = mvebu_pcie_map_irq;
- hw.ops = &mvebu_pcie_ops;
- hw.align_resource = mvebu_pcie_align_resource;
-+ hw.add_bus = mvebu_pcie_add_bus;
-
- pci_common_init(&hw);
- }
-@@ -733,6 +742,21 @@ mvebu_pcie_map_registers(struct platform
- return devm_request_and_ioremap(&pdev->dev, ®s);
- }
-
-+static void __init mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
-+{
-+ struct device_node *msi_node;
-+
-+ msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
-+ "msi-parent", 0);
-+ if (!msi_node)
-+ return;
-+
-+ pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
-+
-+ if (pcie->msi)
-+ pcie->msi->dev = &pcie->pdev->dev;
-+}
-+
- #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
- #define DT_TYPE_IO 0x1
- #define DT_TYPE_MEM32 0x2
-@@ -911,6 +935,8 @@ static int __init mvebu_pcie_probe(struc
- i++;
- }
-
-+ mvebu_pcie_msi_enable(pcie);
-+
- mvebu_pcie_enable(pcie);
-
- return 0;
+++ /dev/null
-From 7171305e9caebac8cd12ef5a5ef3823f0fbe4a1c Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 6 Jun 2013 18:30:19 +0200
-Subject: [PATCH 079/203] ARM: mvebu: link PCIe controllers to the MSI
- controller
-
-This commit adjusts the Armada 370 and Armada XP PCIe controllers
-Device Tree informations to reference their MSI controller. In the
-case of this platform, the MSI controller is implemented by the MPIC.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Daniel Price <daniel.price@gmail.com>
-Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
----
- arch/arm/boot/dts/armada-370.dtsi | 1 +
- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 +
- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 +
- arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 +
- 4 files changed, 4 insertions(+)
-
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -44,6 +44,7 @@
- #address-cells = <3>;
- #size-cells = <2>;
-
-+ msi-parent = <&mpic>;
- bus-range = <0x00 0xff>;
-
- ranges =
---- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-@@ -57,6 +57,7 @@
- #address-cells = <3>;
- #size-cells = <2>;
-
-+ msi-parent = <&mpic>;
- bus-range = <0x00 0xff>;
-
- ranges =
---- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-@@ -58,6 +58,7 @@
- #address-cells = <3>;
- #size-cells = <2>;
-
-+ msi-parent = <&mpic>;
- bus-range = <0x00 0xff>;
-
- ranges =
---- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
-@@ -74,6 +74,7 @@
- #address-cells = <3>;
- #size-cells = <2>;
-
-+ msi-parent = <&mpic>;
- bus-range = <0x00 0xff>;
-
- ranges =
+++ /dev/null
-From 5378928ebac13756fc13d0b2de8dd45ace8026aa Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Mon, 15 Jul 2013 17:34:08 +0200
-Subject: [PATCH 080/203] of: provide a binding for the 'fixed-link' property
-
-Some Ethernet MACs have a "fixed link", and are not connected to a
-normal MDIO-managed PHY device. For those situations, a Device Tree
-binding allows to describe a "fixed link", as a "fixed-link" property
-of the Ethernet device Device Tree node.
-
-This patch adds:
-
- * A documentation for the Device Tree property "fixed-link".
-
- * A of_phy_register_fixed_link() OF helper, which provided an OF node
- that contains a "fixed-link" property, registers the corresponding
- fixed PHY.
-
- * Removes the warning on the of_phy_connect_fixed_link() that says
- new drivers should not use it, since Grant Likely indicated that
- this "fixed-link" property is indeed the way to go.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
----
- .../devicetree/bindings/net/fixed-link.txt | 26 ++++++++++++++++
- drivers/of/of_mdio.c | 36 +++++++++++++++++++---
- include/linux/of_mdio.h | 10 ++++++
- 3 files changed, 68 insertions(+), 4 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/net/fixed-link.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/net/fixed-link.txt
-@@ -0,0 +1,26 @@
-+Fixed link Device Tree binding
-+------------------------------
-+
-+Some Ethernet MACs have a "fixed link", and are not connected to a
-+normal MDIO-managed PHY device. For those situations, a Device Tree
-+binding allows to describe a "fixed link".
-+
-+Such a fixed link situation is described within an Ethernet device
-+Device Tree node using a 'fixed-link' property, composed of 5
-+elements:
-+
-+ 1. A fake PHY ID, which must be unique accross all fixed-link PHYs in
-+ the system.
-+ 2. The duplex (1 for full-duplex, 0 for half-duplex)
-+ 3. The speed (10, 100, 1000)
-+ 4. The pause setting (1 for enabled, 0 for disabled)
-+ 5. The asym pause setting (1 for enabled, 0 for disabled)
-+
-+Example:
-+
-+ethernet@0 {
-+ ...
-+ fixed-link = <1 1 1000 0 0>;
-+ ...
-+};
-+
---- a/drivers/of/of_mdio.c
-+++ b/drivers/of/of_mdio.c
-@@ -14,6 +14,7 @@
- #include <linux/netdevice.h>
- #include <linux/err.h>
- #include <linux/phy.h>
-+#include <linux/phy_fixed.h>
- #include <linux/of.h>
- #include <linux/of_irq.h>
- #include <linux/of_mdio.h>
-@@ -215,10 +216,6 @@ EXPORT_SYMBOL(of_phy_connect);
- * @dev: pointer to net_device claiming the phy
- * @hndlr: Link state callback for the network device
- * @iface: PHY data interface type
-- *
-- * This function is a temporary stop-gap and will be removed soon. It is
-- * only to support the fs_enet, ucc_geth and gianfar Ethernet drivers. Do
-- * not call this function from new drivers.
- */
- struct phy_device *of_phy_connect_fixed_link(struct net_device *dev,
- void (*hndlr)(struct net_device *),
-@@ -247,3 +244,34 @@ struct phy_device *of_phy_connect_fixed_
- return IS_ERR(phy) ? NULL : phy;
- }
- EXPORT_SYMBOL(of_phy_connect_fixed_link);
-+
-+#if defined(CONFIG_FIXED_PHY)
-+/**
-+ * of_phy_register_fixed_link - Parse fixed-link property and register a dummy phy
-+ * @np: pointer to the OF device node that contains the "fixed-link"
-+ * property for which a dummy phy should be registered.
-+ */
-+#define FIXED_LINK_PROPERTIES_COUNT 5
-+int of_phy_register_fixed_link(struct device_node *np)
-+{
-+ struct fixed_phy_status status = {};
-+ u32 fixed_link_props[FIXED_LINK_PROPERTIES_COUNT];
-+ int ret;
-+
-+ ret = of_property_read_u32_array(np, "fixed-link",
-+ fixed_link_props,
-+ FIXED_LINK_PROPERTIES_COUNT);
-+ if (ret < 0)
-+ return ret;
-+
-+ status.link = 1;
-+ status.duplex = fixed_link_props[1];
-+ status.speed = fixed_link_props[2];
-+ status.pause = fixed_link_props[3];
-+ status.asym_pause = fixed_link_props[4];
-+
-+ return fixed_phy_add(PHY_POLL, fixed_link_props[0],
-+ &status);
-+}
-+EXPORT_SYMBOL(of_phy_register_fixed_link);
-+#endif
---- a/include/linux/of_mdio.h
-+++ b/include/linux/of_mdio.h
-@@ -57,4 +57,14 @@ static inline struct mii_bus *of_mdio_fi
- }
- #endif /* CONFIG_OF */
-
-+#if defined(CONFIG_OF) && defined(CONFIG_FIXED_PHY)
-+extern int of_phy_register_fixed_link(struct device_node *np);
-+#else
-+static inline int of_phy_register_fixed_link(struct device_node *np)
-+{
-+ return -ENOSYS;
-+}
-+#endif
-+
-+
- #endif /* __LINUX_OF_MDIO_H */
+++ /dev/null
-From dce33dc5a6ba5f7fcbab4d7e92cc68c756a1f714 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Mon, 15 Jul 2013 17:34:09 +0200
-Subject: [PATCH 081/203] net: phy: call mdiobus_scan() after adding a fixed
- PHY
-
-The fixed_phy_add() function allows to register a fixed PHY. However,
-when this function gets called *after* fixed_mdio_bus_init() (which
-gets called at the module_init stage), then the fixed PHY is not
-registered into the phylib.
-
-In order to address this, we add a call to mdiobus_scan() in
-fixed_phy_add() to ensure that the PHY indeed gets registered into the
-phylib, even if the fixed_phy_add() is called after
-fixed_mdio_bus_init().
-
-This is needed because until now, the only code that was calling the
-fixed_add_phy() function was PowerPC-specific platform code, which
-could ensure that such fixed PHYs get registered before
-fixed_mdio_bus_init() is called.
-
-However, with the new of_phy_register_fixed_link() function, device
-drivers can parse their 'fixed-link' property and register a fixed PHY
-at ->probe() time, which may happen after fixed_mdio_bus_init() is
-called.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
----
- drivers/net/phy/fixed.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/net/phy/fixed.c
-+++ b/drivers/net/phy/fixed.c
-@@ -195,6 +195,8 @@ int fixed_phy_add(unsigned int irq, int
-
- list_add_tail(&fp->node, &fmb->phys);
-
-+ mdiobus_scan(fmb->mii_bus, phy_id);
-+
- return 0;
-
- err_regs:
+++ /dev/null
-From 350a4e8e9d517d2d7c48bc915da5b1e30163add3 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Mon, 15 Jul 2013 17:34:10 +0200
-Subject: [PATCH 082/203] net: mvneta: add support for fixed links
-
-Following the introduction of of_phy_register_fixed_link(), this patch
-introduces fixed link support in the mvneta driver, for Marvell Armada
-370/XP SOCs.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
----
- .../bindings/net/marvell-armada-370-neta.txt | 24 +++++++++++++++++++---
- drivers/net/ethernet/marvell/mvneta.c | 18 +++++++++++-----
- 2 files changed, 34 insertions(+), 8 deletions(-)
-
---- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
-+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
-@@ -4,13 +4,21 @@ Required properties:
- - compatible: should be "marvell,armada-370-neta".
- - reg: address and length of the register set for the device.
- - interrupts: interrupt for the device
--- phy: A phandle to a phy node defining the PHY address (as the reg
-- property, a single integer).
- - phy-mode: The interface between the SoC and the PHY (a string that
- of_get_phy_mode() can understand)
- - clocks: a pointer to the reference clock for this device.
-
--Example:
-+Optional properties:
-+
-+- phy: A phandle to a phy node defining the PHY address (as the reg
-+ property, a single integer). Note: if this property isn't present,
-+ then fixed link is assumed, and the 'fixed-link' property is
-+ mandatory.
-+- fixed-link: A 5 elements array that describe a fixed link, see
-+ fixed-link.txt for details. Note: if a 'phy' property is present,
-+ this 'fixed-link' property is ignored.
-+
-+Examples:
-
- ethernet@d0070000 {
- compatible = "marvell,armada-370-neta";
-@@ -21,3 +29,13 @@ ethernet@d0070000 {
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- };
-+
-+ethernet@d0070000 {
-+ compatible = "marvell,armada-370-neta";
-+ reg = <0xd0070000 0x2500>;
-+ interrupts = <8>;
-+ clocks = <&gate_clk 4>;
-+ status = "okay";
-+ fixed-link = <1 1 1000 0 0>;
-+ phy-mode = "rgmii-id";
-+};
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -2360,8 +2360,12 @@ static int mvneta_mdio_probe(struct mvne
- {
- struct phy_device *phy_dev;
-
-- phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
-- pp->phy_interface);
-+ if (pp->phy_node)
-+ phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
-+ pp->phy_interface);
-+ else
-+ phy_dev = of_phy_connect_fixed_link(pp->dev, mvneta_adjust_link,
-+ pp->phy_interface);
- if (!phy_dev) {
- netdev_err(pp->dev, "could not find the PHY\n");
- return -ENODEV;
-@@ -2719,9 +2723,13 @@ static int mvneta_probe(struct platform_
-
- phy_node = of_parse_phandle(dn, "phy", 0);
- if (!phy_node) {
-- dev_err(&pdev->dev, "no associated PHY\n");
-- err = -ENODEV;
-- goto err_free_irq;
-+ /* No 'phy' found, see if we have a 'fixed-link'
-+ * property */
-+ err = of_phy_register_fixed_link(dn);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "no 'phy' or 'fixed-link' properties\n");
-+ goto err_free_irq;
-+ }
- }
-
- phy_mode = of_get_phy_mode(dn);
+++ /dev/null
-From 409885c9ec1b0dba5c8f393af6d481c69bfa9b0a Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 13 Aug 2013 11:43:12 -0300
-Subject: [PATCH 083/203] clocksource: armada-370-xp: Use
- CLOCKSOURCE_OF_DECLARE
-
-This is almost cosmetic: we achieve a bit of consistency with
-other clocksource drivers by using the CLOCKSOURCE_OF_DECLARE
-macro for the boilerplate code.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
----
- arch/arm/mach-mvebu/armada-370-xp.c | 4 ++--
- drivers/clocksource/time-armada-370-xp.c | 6 +++---
- include/linux/time-armada-370-xp.h | 18 ------------------
- 3 files changed, 5 insertions(+), 23 deletions(-)
- delete mode 100644 include/linux/time-armada-370-xp.h
-
---- a/arch/arm/mach-mvebu/armada-370-xp.c
-+++ b/arch/arm/mach-mvebu/armada-370-xp.c
-@@ -17,7 +17,7 @@
- #include <linux/of_address.h>
- #include <linux/of_platform.h>
- #include <linux/io.h>
--#include <linux/time-armada-370-xp.h>
-+#include <linux/clocksource.h>
- #include <linux/clk/mvebu.h>
- #include <linux/dma-mapping.h>
- #include <linux/mbus.h>
-@@ -38,7 +38,7 @@ static void __init armada_370_xp_map_io(
- static void __init armada_370_xp_timer_and_clk_init(void)
- {
- mvebu_clocks_init();
-- armada_370_xp_timer_init();
-+ clocksource_of_init();
- coherency_init();
- BUG_ON(mvebu_mbus_dt_init());
- #ifdef CONFIG_CACHE_L2X0
---- a/drivers/clocksource/time-armada-370-xp.c
-+++ b/drivers/clocksource/time-armada-370-xp.c
-@@ -210,13 +210,11 @@ static struct local_timer_ops armada_370
- .stop = armada_370_xp_timer_stop,
- };
-
--void __init armada_370_xp_timer_init(void)
-+static void __init armada_370_xp_timer_init(struct device_node *np)
- {
- u32 u;
-- struct device_node *np;
- int res;
-
-- np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer");
- timer_base = of_iomap(np, 0);
- WARN_ON(!timer_base);
- local_base = of_iomap(np, 1);
-@@ -299,3 +297,5 @@ void __init armada_370_xp_timer_init(voi
- #endif
- }
- }
-+CLOCKSOURCE_OF_DECLARE(armada_370_xp, "marvell,armada-370-xp-timer",
-+ armada_370_xp_timer_init);
---- a/include/linux/time-armada-370-xp.h
-+++ /dev/null
-@@ -1,18 +0,0 @@
--/*
-- * Marvell Armada 370/XP SoC timer handling.
-- *
-- * Copyright (C) 2012 Marvell
-- *
-- * Lior Amsalem <alior@marvell.com>
-- * Gregory CLEMENT <gregory.clement@free-electrons.com>
-- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-- *
-- */
--#ifndef __TIME_ARMADA_370_XPPRCMU_H
--#define __TIME_ARMADA_370_XPPRCMU_H
--
--#include <linux/init.h>
--
--void __init armada_370_xp_timer_init(void);
--
--#endif
+++ /dev/null
-From 02b0213923da41034a766942508d882f9be51efd Mon Sep 17 00:00:00 2001
-From: Jean Pihet <jean.pihet@linaro.org>
-Date: Wed, 18 Sep 2013 20:55:09 +0200
-Subject: [PATCH 084/203] arm: clocksource: mvebu: Use the main timer as clock
- source from DT
-
-This commit:
- 573145f08c2b92c45498468afbbba909f6ce6135
- clocksource: armada-370-xp: Use CLOCKSOURCE_OF_DECLARE
-
-replaced a call to the driver's timer initialization by a call to
-clocksource_of_init(). However, it failed to select CONFIG_CLKSRC_OF.
-
-Fix this by selecting CONFIG_CLKSRC_OF for Armada370/XP machines.
-Without this change the kernel is stuck at: 'Calibrating delay loop...'.
-
-Signed-off-by: Jean Pihet <jean.pihet@linaro.org>
-Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/clocksource/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -24,6 +24,7 @@ config DW_APB_TIMER_OF
-
- config ARMADA_370_XP_TIMER
- bool
-+ select CLKSRC_OF
-
- config SUN4I_TIMER
- bool
+++ /dev/null
-From ddda6fa410b6e50ee67d4a628187e76b4a6c9b28 Mon Sep 17 00:00:00 2001
-From: Lior Amsalem <alior@marvell.com>
-Date: Mon, 25 Nov 2013 17:26:45 +0100
-Subject: [PATCH 086/203] irqchip: armada-370-xp: fix MSI race condition
-
-In the Armada 370/XP driver, when we receive an IRQ 1, we read the
-list of doorbells that caused the interrupt from register
-ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS. This gives the list of MSIs that
-were generated. However, instead of acknowledging only the MSIs that
-were generated, we acknowledge *all* the MSIs, by writing
-~MSI_DOORBELL_MASK in the ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS register.
-
-This creates a race condition: if a new MSI that isn't part of the
-ones read into the temporary "msimask" variable is fired before we
-acknowledge all MSIs, then we will simply loose it.
-
-It is important to mention that this ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS
-register has the following behavior: "A CPU write of 0 clears the bits
-in this field. A CPU write of 1 has no effect". This is what allows us
-to simply write ~msimask to acknoledge the handled MSIs.
-
-Notice that the same problem is present in the IPI implementation, but
-it is fixed as a separate patch, so that this IPI fix can be pushed to
-older stable versions as appropriate (all the way to 3.8), while the
-MSI code only appeared in 3.13.
-
-Signed-off-by: Lior Amsalem <alior@marvell.com>
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Cc: Thomas Gleixner <tglx@linutronix.de>
----
- drivers/irqchip/irq-armada-370-xp.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/irqchip/irq-armada-370-xp.c
-+++ b/drivers/irqchip/irq-armada-370-xp.c
-@@ -381,7 +381,7 @@ armada_370_xp_handle_irq(struct pt_regs
- ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
- & PCI_MSI_DOORBELL_MASK;
-
-- writel(~PCI_MSI_DOORBELL_MASK, per_cpu_int_base +
-+ writel(~msimask, per_cpu_int_base +
- ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
-
- for (msinr = PCI_MSI_DOORBELL_START;
+++ /dev/null
-From 98e6b600e81f71f8621e316f5d46cf261a9f1da4 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Mon, 25 Nov 2013 17:26:47 +0100
-Subject: [PATCH 088/203] ARM: mvebu: re-enable PCIe on Armada 370 DB
-
-Commit 14fd8ed0a7fd19913 ("ARM: mvebu: Relocate Armada 370/XP PCIe
-device tree nodes") relocated the PCIe controller DT nodes one level
-up in the Device Tree, to reflect a more correct representation of the
-hardware introduced by the mvebu-mbus Device Tree binding.
-
-However, while most of the boards were properly adjusted accordingly,
-the Armada 370 DB board was left unchanged, and therefore, PCIe is
-seen as not enabled on this board. This patch fixes that by moving the
-PCIe controller node one level-up in armada-370-db.dts.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Cc: stable@vger.kernel.org
----
- arch/arm/boot/dts/armada-370-db.dts | 28 ++++++++++++++--------------
- 1 file changed, 14 insertions(+), 14 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370-db.dts
-+++ b/arch/arm/boot/dts/armada-370-db.dts
-@@ -99,22 +99,22 @@
- spi-max-frequency = <50000000>;
- };
- };
-+ };
-
-- pcie-controller {
-+ pcie-controller {
-+ status = "okay";
-+ /*
-+ * The two PCIe units are accessible through
-+ * both standard PCIe slots and mini-PCIe
-+ * slots on the board.
-+ */
-+ pcie@1,0 {
-+ /* Port 0, Lane 0 */
-+ status = "okay";
-+ };
-+ pcie@2,0 {
-+ /* Port 1, Lane 0 */
- status = "okay";
-- /*
-- * The two PCIe units are accessible through
-- * both standard PCIe slots and mini-PCIe
-- * slots on the board.
-- */
-- pcie@1,0 {
-- /* Port 0, Lane 0 */
-- status = "okay";
-- };
-- pcie@2,0 {
-- /* Port 1, Lane 0 */
-- status = "okay";
-- };
- };
- };
- };
+++ /dev/null
-From 67f66e13d8a6da710d6df965021d92261083b584 Mon Sep 17 00:00:00 2001
-From: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Date: Wed, 25 Sep 2013 13:24:18 +0200
-Subject: [PATCH 089/203] ARM: mvebu: fix gated clock documentation
-
-The gated clock documentation referred only to the Orion SoC whereas
-it also applied for the Armada 370/XP SoC. This commit updates the
-introduction text and also the list of the compatible strings.
-
-Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- .../devicetree/bindings/clock/mvebu-gated-clock.txt | 14 ++++++++------
- 1 file changed, 8 insertions(+), 6 deletions(-)
-
---- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
-+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
-@@ -1,10 +1,10 @@
--* Gated Clock bindings for Marvell Orion SoCs
-+* Gated Clock bindings for Marvell EBU SoCs
-
--Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save
--some power. The clock consumer should specify the desired clock by having
--the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to
--the corresponding clock gating control bit in HW to ease manual clock lookup
--in datasheet.
-+Marvell Armada 370/XP, Dove and Kirkwood allow some peripheral clocks to be
-+gated to save some power. The clock consumer should specify the desired clock
-+by having the clock ID in its "clocks" phandle cell. The clock ID is directly
-+mapped to the corresponding clock gating control bit in HW to ease manual clock
-+lookup in datasheet.
-
- The following is a list of provided IDs for Armada 370:
- ID Clock Peripheral
-@@ -94,6 +94,8 @@ ID Clock Peripheral
-
- Required properties:
- - compatible : shall be one of the following:
-+ "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
-+ "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
- "marvell,dove-gating-clock" - for Dove SoC clock gating
- "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
- - reg : shall be the register address of the Clock Gating Control register
+++ /dev/null
-From 4aa571afd29f88898ef2fb954effcf53fec3264e Mon Sep 17 00:00:00 2001
-From: Huang Shijie <b32955@freescale.com>
-Date: Fri, 17 May 2013 11:17:25 +0800
-Subject: [PATCH 090/203] mtd: add datasheet's ECC information to nand_chip{}
-
-1.) Why add the ECC information to the nand_chip{} ?
- Each nand chip has its requirement for the ECC correctability, such as
- "4bit ECC for each 512Byte" or "40bit ECC for each 1024Byte".
- This ECC info is very important to the nand controller, such as gpmi.
-
- Take the Micron MT29F64G08CBABA for example, its geometry is
- 8KiB page size, 744 bytes oob size and it requires 40bit ECC per 1KiB.
- If we do not provide the ECC info to the gpmi nand driver, it has to
- calculate the ECC correctability itself. The gpmi driver will gets the 56bit
- ECC for per 1KiB which is beyond its BCH's 40bit ecc capibility.
- The gpmi will quits in this case. But in actually, the gpmi can supports
- this nand chip if it can get the right ECC info.
-
-2.) about the new fields.
- The @ecc_strength_ds stands for the ecc bits needed within the @ecc_step_ds.
- The two fields should be set from the nand chip's datasheets.
-
- For example:
- "4bit ECC for each 512Byte" could be:
- @ecc_strength_ds = 4, @ecc_step_ds = 512.
- "40bit ECC for each 1024Byte" could be:
- @ecc_strength_ds = 40, @ecc_step_ds = 1024.
-
-3.) Why do not re-use the @strength and @size in the nand_ecc_ctrl{}?
- The @strength and @size in nand_ecc_ctrl{} is used by the nand controller
- driver, while the @ecc_strength_ds and @ecc_step_ds are get from the datasheet.
-
-Signed-off-by: Huang Shijie <b32955@freescale.com>
-Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- include/linux/mtd/nand.h | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -434,6 +434,12 @@ struct nand_buffers {
- * bad block marker position; i.e., BBM == 11110111b is
- * not bad when badblockbits == 7
- * @cellinfo: [INTERN] MLC/multichip data from chip ident
-+ * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
-+ * Minimum amount of bit errors per @ecc_step_ds guaranteed
-+ * to be correctable. If unknown, set to zero.
-+ * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
-+ * also from the datasheet. It is the recommended ECC step
-+ * size, if known; if unknown, set to zero.
- * @numchips: [INTERN] number of physical chips
- * @chipsize: [INTERN] the size of one chip for multichip arrays
- * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
-@@ -510,6 +516,8 @@ struct nand_chip {
- unsigned int pagebuf_bitflips;
- int subpagesize;
- uint8_t cellinfo;
-+ uint16_t ecc_strength_ds;
-+ uint16_t ecc_step_ds;
- int badblockpos;
- int badblockbits;
-
+++ /dev/null
-From 50a7db84f71e7c4779596fb5f8efb579a5d29f97 Mon Sep 17 00:00:00 2001
-From: Huang Shijie <b32955@freescale.com>
-Date: Fri, 17 May 2013 11:17:27 +0800
-Subject: [PATCH 091/203] mtd: add data structures for Extended Parameter Page
-
-Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page
-to store the ECC info.
-
-The onfi spec tells us that if the nand chip's recommended ECC codeword
-size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_ then
-read the Extended ECC information that is part of the extended parameter
-page to retrieve the ECC requirements for this device.
-
-This patch adds
- [1] the neccessary fields for nand_onfi_params{},
- [2] and adds the onfi_ext_ecc_info{} for Extended ECC information,
- [3] adds onfi_ext_section{} for extended sections,
- [4] and adds onfi_ext_param_page{} for the Extended Parameter Page.
-
-Acked-by: Pekon Gupta <pekon@ti.com>
-Signed-off-by: Huang Shijie <b32955@freescale.com>
-Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
-[Brian: amended for checkpatch.pl]
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- include/linux/mtd/nand.h | 39 ++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 38 insertions(+), 1 deletion(-)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -224,7 +224,10 @@ struct nand_onfi_params {
- __le16 revision;
- __le16 features;
- __le16 opt_cmd;
-- u8 reserved[22];
-+ u8 reserved0[2];
-+ __le16 ext_param_page_length; /* since ONFI 2.1 */
-+ u8 num_of_param_pages; /* since ONFI 2.1 */
-+ u8 reserved1[17];
-
- /* manufacturer information block */
- char manufacturer[12];
-@@ -281,6 +284,40 @@ struct nand_onfi_params {
-
- #define ONFI_CRC_BASE 0x4F4E
-
-+/* Extended ECC information Block Definition (since ONFI 2.1) */
-+struct onfi_ext_ecc_info {
-+ u8 ecc_bits;
-+ u8 codeword_size;
-+ __le16 bb_per_lun;
-+ __le16 block_endurance;
-+ u8 reserved[2];
-+} __packed;
-+
-+#define ONFI_SECTION_TYPE_0 0 /* Unused section. */
-+#define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
-+#define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
-+struct onfi_ext_section {
-+ u8 type;
-+ u8 length;
-+} __packed;
-+
-+#define ONFI_EXT_SECTION_MAX 8
-+
-+/* Extended Parameter Page Definition (since ONFI 2.1) */
-+struct onfi_ext_param_page {
-+ __le16 crc;
-+ u8 sig[4]; /* 'E' 'P' 'P' 'S' */
-+ u8 reserved0[10];
-+ struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
-+
-+ /*
-+ * The actual size of the Extended Parameter Page is in
-+ * @ext_param_page_length of nand_onfi_params{}.
-+ * The following are the variable length sections.
-+ * So we do not add any fields below. Please see the ONFI spec.
-+ */
-+} __packed;
-+
- /**
- * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
- * @lock: protection lock
+++ /dev/null
-From aeeb6ea6eb18c46f5776dd068989686686cda359 Mon Sep 17 00:00:00 2001
-From: Huang Shijie <shijie8@gmail.com>
-Date: Fri, 17 May 2013 11:17:28 +0800
-Subject: [PATCH 092/203] mtd: add a helper to get the supported features for
- ONFI nand
-
-add a helper to get the supported features for ONFI nand.
-Also add the neccessary macros.
-
-Signed-off-by: Huang Shijie <b32955@freescale.com>
-Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- include/linux/mtd/nand.h | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -202,6 +202,10 @@ typedef enum {
- /* Keep gcc happy */
- struct nand_chip;
-
-+/* ONFI features */
-+#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
-+#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
-+
- /* ONFI timing mode, used in both asynchronous and synchronous mode */
- #define ONFI_TIMING_MODE_0 (1 << 0)
- #define ONFI_TIMING_MODE_1 (1 << 1)
-@@ -754,6 +758,12 @@ struct platform_nand_chip *get_platform_
- return chip->priv;
- }
-
-+/* return the supported features. */
-+static inline int onfi_feature(struct nand_chip *chip)
-+{
-+ return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
-+}
-+
- /* return the supported asynchronous timing mode. */
- static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
- {
+++ /dev/null
-From ceef2075f3aa430da137e3629b0280a46d420ccd Mon Sep 17 00:00:00 2001
-From: Huang Shijie <b32955@freescale.com>
-Date: Fri, 17 May 2013 11:17:26 +0800
-Subject: [PATCH 093/203] mtd: get the ECC info from the parameter page for
- ONFI nand
-
-From the ONFI spec, we can just get the ECC info from the @ecc_bits field of
-the parameter page.
-
-Signed-off-by: Huang Shijie <b32955@freescale.com>
-Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/nand_base.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
-@@ -2924,6 +2924,11 @@ static int nand_flash_detect_onfi(struct
- if (le16_to_cpu(p->features) & 1)
- *busw = NAND_BUSWIDTH_16;
-
-+ if (p->ecc_bits != 0xff) {
-+ chip->ecc_strength_ds = p->ecc_bits;
-+ chip->ecc_step_ds = 512;
-+ }
-+
- pr_info("ONFI flash detected\n");
- return 1;
- }
+++ /dev/null
-From f617846b1e20a2ba59cdd9435715339eaed1e251 Mon Sep 17 00:00:00 2001
-From: Huang Shijie <b32955@freescale.com>
-Date: Wed, 22 May 2013 10:28:27 +0800
-Subject: [PATCH 094/203] mtd: get the ECC info from the Extended Parameter
- Page
-
-Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page
-to store the ECC info.
-
-The onfi spec tells us that if the nand chip's recommended ECC codeword
-size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_ then
-read the Extended ECC information that is part of the extended parameter
-page to retrieve the ECC requirements for this device.
-
-This patch implement the reading of the Extended Parameter Page, and parses
-the sections for ECC type, and get the ECC info from the ECC section.
-
-Tested this patch with Micron MT29F64G08CBABAWP.
-
-Acked-by: Pekon Gupta <pekon@ti.com>
-Signed-off-by: Huang Shijie <b32955@freescale.com>
-Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/nand_base.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 87 insertions(+)
-
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
-@@ -2848,6 +2848,78 @@ static u16 onfi_crc16(u16 crc, u8 const
- return crc;
- }
-
-+/* Parse the Extended Parameter Page. */
-+static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
-+ struct nand_chip *chip, struct nand_onfi_params *p)
-+{
-+ struct onfi_ext_param_page *ep;
-+ struct onfi_ext_section *s;
-+ struct onfi_ext_ecc_info *ecc;
-+ uint8_t *cursor;
-+ int ret = -EINVAL;
-+ int len;
-+ int i;
-+
-+ len = le16_to_cpu(p->ext_param_page_length) * 16;
-+ ep = kmalloc(len, GFP_KERNEL);
-+ if (!ep) {
-+ ret = -ENOMEM;
-+ goto ext_out;
-+ }
-+
-+ /* Send our own NAND_CMD_PARAM. */
-+ chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
-+
-+ /* Use the Change Read Column command to skip the ONFI param pages. */
-+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
-+ sizeof(*p) * p->num_of_param_pages , -1);
-+
-+ /* Read out the Extended Parameter Page. */
-+ chip->read_buf(mtd, (uint8_t *)ep, len);
-+ if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
-+ != le16_to_cpu(ep->crc))) {
-+ pr_debug("fail in the CRC.\n");
-+ goto ext_out;
-+ }
-+
-+ /*
-+ * Check the signature.
-+ * Do not strictly follow the ONFI spec, maybe changed in future.
-+ */
-+ if (strncmp(ep->sig, "EPPS", 4)) {
-+ pr_debug("The signature is invalid.\n");
-+ goto ext_out;
-+ }
-+
-+ /* find the ECC section. */
-+ cursor = (uint8_t *)(ep + 1);
-+ for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
-+ s = ep->sections + i;
-+ if (s->type == ONFI_SECTION_TYPE_2)
-+ break;
-+ cursor += s->length * 16;
-+ }
-+ if (i == ONFI_EXT_SECTION_MAX) {
-+ pr_debug("We can not find the ECC section.\n");
-+ goto ext_out;
-+ }
-+
-+ /* get the info we want. */
-+ ecc = (struct onfi_ext_ecc_info *)cursor;
-+
-+ if (ecc->codeword_size) {
-+ chip->ecc_strength_ds = ecc->ecc_bits;
-+ chip->ecc_step_ds = 1 << ecc->codeword_size;
-+ }
-+
-+ pr_info("ONFI extended param page detected.\n");
-+ return 0;
-+
-+ext_out:
-+ kfree(ep);
-+ return ret;
-+}
-+
- /*
- * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
- */
-@@ -2927,6 +2999,21 @@ static int nand_flash_detect_onfi(struct
- if (p->ecc_bits != 0xff) {
- chip->ecc_strength_ds = p->ecc_bits;
- chip->ecc_step_ds = 512;
-+ } else if (chip->onfi_version >= 21 &&
-+ (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
-+
-+ /*
-+ * The nand_flash_detect_ext_param_page() uses the
-+ * Change Read Column command which maybe not supported
-+ * by the chip->cmdfunc. So try to update the chip->cmdfunc
-+ * now. We do not replace user supplied command function.
-+ */
-+ if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
-+ chip->cmdfunc = nand_command_lp;
-+
-+ /* The Extended Parameter Page is supported since ONFI 2.1. */
-+ if (nand_flash_detect_ext_param_page(mtd, chip, p))
-+ pr_info("Failed to detect the extended param page.\n");
- }
-
- pr_info("ONFI flash detected\n");
+++ /dev/null
-From 5d15281ca712cb873835e301937f3a8342e88d4b Mon Sep 17 00:00:00 2001
-From: Brian Norris <computersforpeace@gmail.com>
-Date: Mon, 16 Sep 2013 17:59:20 -0700
-Subject: [PATCH 095/203] mtd: nand: fix memory leak in ONFI extended parameter
- page
-
-This fixes a memory leak in the ONFI support code for detecting the
-required ECC levels from this commit:
-
- commit 6dcbe0cdd83fb5f77be4f44c9e06c535281c375a
- Author: Huang Shijie <b32955@freescale.com>
- Date: Wed May 22 10:28:27 2013 +0800
-
- mtd: get the ECC info from the Extended Parameter Page
-
-In the success case, we never freed the 'ep' buffer.
-
-Also, this fixes an oversight in the same commit where we (harmlessly)
-freed the NULL pointer.
-
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Acked-by: Huang Shijie <b32955@freescale.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/nand_base.c | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
-@@ -2862,10 +2862,8 @@ static int nand_flash_detect_ext_param_p
-
- len = le16_to_cpu(p->ext_param_page_length) * 16;
- ep = kmalloc(len, GFP_KERNEL);
-- if (!ep) {
-- ret = -ENOMEM;
-- goto ext_out;
-- }
-+ if (!ep)
-+ return -ENOMEM;
-
- /* Send our own NAND_CMD_PARAM. */
- chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
-@@ -2913,7 +2911,7 @@ static int nand_flash_detect_ext_param_p
- }
-
- pr_info("ONFI extended param page detected.\n");
-- return 0;
-+ ret = 0;
-
- ext_out:
- kfree(ep);
+++ /dev/null
-From ac8294dfb4085f3193bec27673062e5ad63d770a Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 26 Sep 2013 16:35:27 -0300
-Subject: [PATCH 096/203] clk: mvebu: Add Core Divider clock
-
-This commit introduces a new group of clocks present in Armada 370/XP
-SoCs (called "Core Divider" clocks) and add a provider for them.
-The only clock supported for now is the NAND clock (ndclk), but the
-infrastructure to add the rest is already set.
-
-Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Mike Turquette <mturquette@linaro.org>
----
- arch/arm/mach-mvebu/Kconfig | 1 +
- drivers/clk/mvebu/Kconfig | 3 +
- drivers/clk/mvebu/Makefile | 1 +
- drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++
- 4 files changed, 228 insertions(+)
- create mode 100644 drivers/clk/mvebu/clk-corediv.c
-
---- a/arch/arm/mach-mvebu/Kconfig
-+++ b/arch/arm/mach-mvebu/Kconfig
-@@ -13,6 +13,7 @@ config ARCH_MVEBU
- select MVEBU_CLK_CORE
- select MVEBU_CLK_CPU
- select MVEBU_CLK_GATING
-+ select MVEBU_CLK_COREDIV
- select MVEBU_MBUS
- select ZONE_DMA if ARM_LPAE
- select ARCH_REQUIRE_GPIOLIB
---- a/drivers/clk/mvebu/Kconfig
-+++ b/drivers/clk/mvebu/Kconfig
-@@ -6,3 +6,6 @@ config MVEBU_CLK_CPU
-
- config MVEBU_CLK_GATING
- bool
-+
-+config MVEBU_CLK_COREDIV
-+ bool
---- a/drivers/clk/mvebu/Makefile
-+++ b/drivers/clk/mvebu/Makefile
-@@ -1,3 +1,4 @@
- obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
- obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
- obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
-+obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o
---- /dev/null
-+++ b/drivers/clk/mvebu/clk-corediv.c
-@@ -0,0 +1,223 @@
-+/*
-+ * MVEBU Core divider clock
-+ *
-+ * Copyright (C) 2013 Marvell
-+ *
-+ * Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/clk-provider.h>
-+#include <linux/of_address.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <asm/io.h>
-+
-+#define CORE_CLK_DIV_RATIO_MASK 0xff
-+#define CORE_CLK_DIV_RATIO_RELOAD BIT(8)
-+#define CORE_CLK_DIV_ENABLE_OFFSET 24
-+#define CORE_CLK_DIV_RATIO_OFFSET 0x8
-+
-+struct clk_corediv_desc {
-+ unsigned int mask;
-+ unsigned int offset;
-+ unsigned int fieldbit;
-+};
-+
-+struct clk_corediv {
-+ struct clk_hw hw;
-+ void __iomem *reg;
-+ struct clk_corediv_desc desc;
-+ spinlock_t lock;
-+};
-+
-+static struct clk_onecell_data clk_data;
-+
-+static const struct clk_corediv_desc mvebu_corediv_desc[] __initconst = {
-+ { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
-+};
-+
-+#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
-+
-+static int clk_corediv_is_enabled(struct clk_hw *hwclk)
-+{
-+ struct clk_corediv *corediv = to_corediv_clk(hwclk);
-+ struct clk_corediv_desc *desc = &corediv->desc;
-+ u32 enable_mask = BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET;
-+
-+ return !!(readl(corediv->reg) & enable_mask);
-+}
-+
-+static int clk_corediv_enable(struct clk_hw *hwclk)
-+{
-+ struct clk_corediv *corediv = to_corediv_clk(hwclk);
-+ struct clk_corediv_desc *desc = &corediv->desc;
-+ unsigned long flags = 0;
-+ u32 reg;
-+
-+ spin_lock_irqsave(&corediv->lock, flags);
-+
-+ reg = readl(corediv->reg);
-+ reg |= (BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET);
-+ writel(reg, corediv->reg);
-+
-+ spin_unlock_irqrestore(&corediv->lock, flags);
-+
-+ return 0;
-+}
-+
-+static void clk_corediv_disable(struct clk_hw *hwclk)
-+{
-+ struct clk_corediv *corediv = to_corediv_clk(hwclk);
-+ struct clk_corediv_desc *desc = &corediv->desc;
-+ unsigned long flags = 0;
-+ u32 reg;
-+
-+ spin_lock_irqsave(&corediv->lock, flags);
-+
-+ reg = readl(corediv->reg);
-+ reg &= ~(BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET);
-+ writel(reg, corediv->reg);
-+
-+ spin_unlock_irqrestore(&corediv->lock, flags);
-+}
-+
-+static unsigned long clk_corediv_recalc_rate(struct clk_hw *hwclk,
-+ unsigned long parent_rate)
-+{
-+ struct clk_corediv *corediv = to_corediv_clk(hwclk);
-+ struct clk_corediv_desc *desc = &corediv->desc;
-+ u32 reg, div;
-+
-+ reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET);
-+ div = (reg >> desc->offset) & desc->mask;
-+ return parent_rate / div;
-+}
-+
-+static long clk_corediv_round_rate(struct clk_hw *hwclk, unsigned long rate,
-+ unsigned long *parent_rate)
-+{
-+ /* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */
-+ u32 div;
-+
-+ div = *parent_rate / rate;
-+ if (div < 4)
-+ div = 4;
-+ else if (div > 6)
-+ div = 8;
-+
-+ return *parent_rate / div;
-+}
-+
-+static int clk_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate,
-+ unsigned long parent_rate)
-+{
-+ struct clk_corediv *corediv = to_corediv_clk(hwclk);
-+ struct clk_corediv_desc *desc = &corediv->desc;
-+ unsigned long flags = 0;
-+ u32 reg, div;
-+
-+ div = parent_rate / rate;
-+
-+ spin_lock_irqsave(&corediv->lock, flags);
-+
-+ /* Write new divider to the divider ratio register */
-+ reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET);
-+ reg &= ~(desc->mask << desc->offset);
-+ reg |= (div & desc->mask) << desc->offset;
-+ writel(reg, corediv->reg + CORE_CLK_DIV_RATIO_OFFSET);
-+
-+ /* Set reload-force for this clock */
-+ reg = readl(corediv->reg) | BIT(desc->fieldbit);
-+ writel(reg, corediv->reg);
-+
-+ /* Now trigger the clock update */
-+ reg = readl(corediv->reg) | CORE_CLK_DIV_RATIO_RELOAD;
-+ writel(reg, corediv->reg);
-+
-+ /*
-+ * Wait for clocks to settle down, and then clear all the
-+ * ratios request and the reload request.
-+ */
-+ udelay(1000);
-+ reg &= ~(CORE_CLK_DIV_RATIO_MASK | CORE_CLK_DIV_RATIO_RELOAD);
-+ writel(reg, corediv->reg);
-+ udelay(1000);
-+
-+ spin_unlock_irqrestore(&corediv->lock, flags);
-+
-+ return 0;
-+}
-+
-+static const struct clk_ops corediv_ops = {
-+ .enable = clk_corediv_enable,
-+ .disable = clk_corediv_disable,
-+ .is_enabled = clk_corediv_is_enabled,
-+ .recalc_rate = clk_corediv_recalc_rate,
-+ .round_rate = clk_corediv_round_rate,
-+ .set_rate = clk_corediv_set_rate,
-+};
-+
-+static void __init mvebu_corediv_clk_init(struct device_node *node)
-+{
-+ struct clk_init_data init;
-+ struct clk_corediv *corediv;
-+ struct clk **clks;
-+ void __iomem *base;
-+ const char *parent_name;
-+ const char *clk_name;
-+ int i;
-+
-+ base = of_iomap(node, 0);
-+ if (WARN_ON(!base))
-+ return;
-+
-+ parent_name = of_clk_get_parent_name(node, 0);
-+
-+ clk_data.clk_num = ARRAY_SIZE(mvebu_corediv_desc);
-+
-+ /* clks holds the clock array */
-+ clks = kcalloc(clk_data.clk_num, sizeof(struct clk *),
-+ GFP_KERNEL);
-+ if (WARN_ON(!clks))
-+ goto err_unmap;
-+ /* corediv holds the clock specific array */
-+ corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv),
-+ GFP_KERNEL);
-+ if (WARN_ON(!corediv))
-+ goto err_free_clks;
-+
-+ spin_lock_init(&corediv->lock);
-+
-+ for (i = 0; i < clk_data.clk_num; i++) {
-+ of_property_read_string_index(node, "clock-output-names",
-+ i, &clk_name);
-+ init.num_parents = 1;
-+ init.parent_names = &parent_name;
-+ init.name = clk_name;
-+ init.ops = &corediv_ops;
-+ init.flags = 0;
-+
-+ corediv[i].desc = mvebu_corediv_desc[i];
-+ corediv[i].reg = base;
-+ corediv[i].hw.init = &init;
-+
-+ clks[i] = clk_register(NULL, &corediv[i].hw);
-+ WARN_ON(IS_ERR(clks[i]));
-+ }
-+
-+ clk_data.clks = clks;
-+ of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
-+ return;
-+
-+err_free_clks:
-+ kfree(clks);
-+err_unmap:
-+ iounmap(base);
-+}
-+CLK_OF_DECLARE(mvebu_corediv_clk, "marvell,armada-370-corediv-clock",
-+ mvebu_corediv_clk_init);
+++ /dev/null
-From 455ad812cb2ec97339f780e2a79169620f1e7485 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Fri, 18 Oct 2013 20:02:30 -0300
-Subject: [PATCH 097/203] ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XP
-
-Armada 370/XP SoCs have a 2 GHz fixed PLL that is used to feed
-other clocks. This commit adds a DT representation of this clock
-through a fixed-clock compatible node.
-
-Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370-xp.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -251,4 +251,13 @@
-
- };
- };
-+
-+ clocks {
-+ /* 2 GHz fixed main PLL */
-+ mainpll: mainpll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <2000000000>;
-+ };
-+ };
- };
+++ /dev/null
-From 408b807592d9cdbc1a69b119f4a862b2ab1e4d87 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Fri, 18 Oct 2013 20:02:31 -0300
-Subject: [PATCH 098/203] ARM: mvebu: Add the core-divider clock to Armada
- 370/XP
-
-The Armada 370/XP SoC has a clock provider called "Core Divider",
-that is derived from a fixed 2 GHz PLL clock.
-
-Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370-xp.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -134,6 +134,14 @@
- status = "disabled";
- };
-
-+ coredivclk: corediv-clock@18740 {
-+ compatible = "marvell,armada-370-corediv-clock";
-+ reg = <0x18740 0xc>;
-+ #clock-cells = <1>;
-+ clocks = <&mainpll>;
-+ clock-output-names = "nand";
-+ };
-+
- timer@20300 {
- compatible = "marvell,armada-370-xp-timer";
- reg = <0x20300 0x30>, <0x21040 0x30>;
+++ /dev/null
-From 64356fe97302ad842d9871a5a4411d8b41127f59 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:33 -0300
-Subject: [PATCH 099/203] ARM: mvebu: Add support for NAND controller in Armada
- 370/XP
-
-The Armada 370 and Armada XP SoC have a NAND controller (aka NFCv2).
-This commit adds support for it in Armada 370 and Armada XP SoC
-common devicetree.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370-xp.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -257,6 +257,15 @@
- status = "disabled";
- };
-
-+ nand@d0000 {
-+ compatible = "marvell,armada370-nand";
-+ reg = <0xd0000 0x54>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ interrupts = <113>;
-+ clocks = <&coredivclk 0>;
-+ status = "disabled";
-+ };
- };
- };
-
+++ /dev/null
-From 9226a0bb330bb83df9a465ba418efd3277cd00d3 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:34 -0300
-Subject: [PATCH 100/203] ARM: mvebu: Enable NAND controller in Armada XP GP
- board
-
-The Armada XP GP board has a NAND flash, so enable it in the devicetree.
-
-In order to skip the driver's custom device detection and use only ONFI
-detection, the "marvell,keep-config" parameter is used.
-This is needed because we haven't support for setting the timings
-parameters yet and must rely in bootloader's.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-xp-gp.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm/boot/dts/armada-xp-gp.dts
-+++ b/arch/arm/boot/dts/armada-xp-gp.dts
-@@ -175,6 +175,14 @@
- spi-max-frequency = <108000000>;
- };
- };
-+
-+ nand@d0000 {
-+ status = "okay";
-+ num-cs = <1>;
-+ marvell,nand-keep-config;
-+ marvell,nand-enable-arbiter;
-+ nand-on-flash-bbt;
-+ };
- };
- };
- };
+++ /dev/null
-From 271ef48cf11b86ab666582051fed3bdb13681e64 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 17 Apr 2013 13:38:09 -0300
-Subject: [PATCH 101/203] mtd: nand: pxa3xx: Use devm_kzalloc
-
-Replace regular kzalloc with managed devm_kzalloc
-which simplifies the error path.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 14 ++++----------
- 1 file changed, 4 insertions(+), 10 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1035,12 +1035,10 @@ static int alloc_nand_resource(struct pl
- int ret, irq, cs;
-
- pdata = pdev->dev.platform_data;
-- info = kzalloc(sizeof(*info) + (sizeof(*mtd) +
-- sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
-- if (!info) {
-- dev_err(&pdev->dev, "failed to allocate memory\n");
-+ info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
-+ sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
-+ if (!info)
- return -ENOMEM;
-- }
-
- info->pdev = pdev;
- for (cs = 0; cs < pdata->num_cs; cs++) {
-@@ -1072,8 +1070,7 @@ static int alloc_nand_resource(struct pl
- info->clk = clk_get(&pdev->dev, NULL);
- if (IS_ERR(info->clk)) {
- dev_err(&pdev->dev, "failed to get nand clock\n");
-- ret = PTR_ERR(info->clk);
-- goto fail_free_mtd;
-+ return PTR_ERR(info->clk);
- }
- clk_enable(info->clk);
-
-@@ -1165,8 +1162,6 @@ fail_free_res:
- fail_put_clk:
- clk_disable(info->clk);
- clk_put(info->clk);
--fail_free_mtd:
-- kfree(info);
- return ret;
- }
-
-@@ -1202,7 +1197,6 @@ static int pxa3xx_nand_remove(struct pla
-
- for (cs = 0; cs < pdata->num_cs; cs++)
- nand_release(info->host[cs]->mtd);
-- kfree(info);
- return 0;
- }
-
+++ /dev/null
-From 5c461327aca8975276d2480ddf02b6c7f0a29548 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 17 Apr 2013 13:38:10 -0300
-Subject: [PATCH 102/203] mtd: nand: pxa3xx: Use devm_ioremap_resource
-
-Using the new devm_ioremap_resource() we can greatly
-simplify resource handling.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 31 ++++---------------------------
- 1 file changed, 4 insertions(+), 27 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1108,30 +1108,16 @@ static int alloc_nand_resource(struct pl
- }
-
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- if (r == NULL) {
-- dev_err(&pdev->dev, "no IO memory resource defined\n");
-- ret = -ENODEV;
-+ info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
-+ if (IS_ERR(info->mmio_base)) {
-+ ret = PTR_ERR(info->mmio_base);
- goto fail_put_clk;
- }
--
-- r = request_mem_region(r->start, resource_size(r), pdev->name);
-- if (r == NULL) {
-- dev_err(&pdev->dev, "failed to request memory resource\n");
-- ret = -EBUSY;
-- goto fail_put_clk;
-- }
--
-- info->mmio_base = ioremap(r->start, resource_size(r));
-- if (info->mmio_base == NULL) {
-- dev_err(&pdev->dev, "ioremap() failed\n");
-- ret = -ENODEV;
-- goto fail_free_res;
-- }
- info->mmio_phys = r->start;
-
- ret = pxa3xx_nand_init_buff(info);
- if (ret)
-- goto fail_free_io;
-+ goto fail_put_clk;
-
- /* initialize all interrupts to be disabled */
- disable_int(info, NDSR_MASK);
-@@ -1155,10 +1141,6 @@ fail_free_buf:
- info->data_buff, info->data_buff_phys);
- } else
- kfree(info->data_buff);
--fail_free_io:
-- iounmap(info->mmio_base);
--fail_free_res:
-- release_mem_region(r->start, resource_size(r));
- fail_put_clk:
- clk_disable(info->clk);
- clk_put(info->clk);
-@@ -1169,7 +1151,6 @@ static int pxa3xx_nand_remove(struct pla
- {
- struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
- struct pxa3xx_nand_platform_data *pdata;
-- struct resource *r;
- int irq, cs;
-
- if (!info)
-@@ -1188,10 +1169,6 @@ static int pxa3xx_nand_remove(struct pla
- } else
- kfree(info->data_buff);
-
-- iounmap(info->mmio_base);
-- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- release_mem_region(r->start, resource_size(r));
--
- clk_disable(info->clk);
- clk_put(info->clk);
-
+++ /dev/null
-From 4ff9eea8b6841bb8be7becba9713a0ce7c82da9d Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 17 Apr 2013 13:38:11 -0300
-Subject: [PATCH 103/203] mtd: nand: pxa3xx: Use devm_clk_get
-
-Replacing clk_get by managed devm_clk_get, the error path
-can be greatly simplified.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 16 +++++++---------
- 1 file changed, 7 insertions(+), 9 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1067,7 +1067,7 @@ static int alloc_nand_resource(struct pl
-
- spin_lock_init(&chip->controller->lock);
- init_waitqueue_head(&chip->controller->wq);
-- info->clk = clk_get(&pdev->dev, NULL);
-+ info->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(info->clk)) {
- dev_err(&pdev->dev, "failed to get nand clock\n");
- return PTR_ERR(info->clk);
-@@ -1087,7 +1087,7 @@ static int alloc_nand_resource(struct pl
- if (r == NULL) {
- dev_err(&pdev->dev, "no resource defined for data DMA\n");
- ret = -ENXIO;
-- goto fail_put_clk;
-+ goto fail_disable_clk;
- }
- info->drcmr_dat = r->start;
-
-@@ -1095,7 +1095,7 @@ static int alloc_nand_resource(struct pl
- if (r == NULL) {
- dev_err(&pdev->dev, "no resource defined for command DMA\n");
- ret = -ENXIO;
-- goto fail_put_clk;
-+ goto fail_disable_clk;
- }
- info->drcmr_cmd = r->start;
- }
-@@ -1104,20 +1104,20 @@ static int alloc_nand_resource(struct pl
- if (irq < 0) {
- dev_err(&pdev->dev, "no IRQ resource defined\n");
- ret = -ENXIO;
-- goto fail_put_clk;
-+ goto fail_disable_clk;
- }
-
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
- if (IS_ERR(info->mmio_base)) {
- ret = PTR_ERR(info->mmio_base);
-- goto fail_put_clk;
-+ goto fail_disable_clk;
- }
- info->mmio_phys = r->start;
-
- ret = pxa3xx_nand_init_buff(info);
- if (ret)
-- goto fail_put_clk;
-+ goto fail_disable_clk;
-
- /* initialize all interrupts to be disabled */
- disable_int(info, NDSR_MASK);
-@@ -1141,9 +1141,8 @@ fail_free_buf:
- info->data_buff, info->data_buff_phys);
- } else
- kfree(info->data_buff);
--fail_put_clk:
-+fail_disable_clk:
- clk_disable(info->clk);
-- clk_put(info->clk);
- return ret;
- }
-
-@@ -1170,7 +1169,6 @@ static int pxa3xx_nand_remove(struct pla
- kfree(info->data_buff);
-
- clk_disable(info->clk);
-- clk_put(info->clk);
-
- for (cs = 0; cs < pdata->num_cs; cs++)
- nand_release(info->host[cs]->mtd);
+++ /dev/null
-From e9274ba8dd0c93f12c0fd5896e11f754aa700baf Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 17 Apr 2013 13:38:12 -0300
-Subject: [PATCH 104/203] mtd: nand: pxa3xx: Use clk_prepare_enable and
- clk_disable_unprepare
-
-This patch converts the module to use clk_prepare_enable and
-clk_disable_unprepare variants as required by common clock framework.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1072,7 +1072,7 @@ static int alloc_nand_resource(struct pl
- dev_err(&pdev->dev, "failed to get nand clock\n");
- return PTR_ERR(info->clk);
- }
-- clk_enable(info->clk);
-+ clk_prepare_enable(info->clk);
-
- /*
- * This is a dirty hack to make this driver work from devicetree
-@@ -1142,7 +1142,7 @@ fail_free_buf:
- } else
- kfree(info->data_buff);
- fail_disable_clk:
-- clk_disable(info->clk);
-+ clk_disable_unprepare(info->clk);
- return ret;
- }
-
-@@ -1168,7 +1168,7 @@ static int pxa3xx_nand_remove(struct pla
- } else
- kfree(info->data_buff);
-
-- clk_disable(info->clk);
-+ clk_disable_unprepare(info->clk);
-
- for (cs = 0; cs < pdata->num_cs; cs++)
- nand_release(info->host[cs]->mtd);
+++ /dev/null
-From 7e8fbc673938278ec7165b99b76227d7cc2ab012 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 17 Apr 2013 13:38:13 -0300
-Subject: [PATCH 105/203] mtd: nand: pxa3xx: Check for clk_prepare_enable()
- return value
-
-clk_prepare_enable() can fail due to unknown reason.
-Add a check for this and return the error code if it fails.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1072,7 +1072,9 @@ static int alloc_nand_resource(struct pl
- dev_err(&pdev->dev, "failed to get nand clock\n");
- return PTR_ERR(info->clk);
- }
-- clk_prepare_enable(info->clk);
-+ ret = clk_prepare_enable(info->clk);
-+ if (ret < 0)
-+ return ret;
-
- /*
- * This is a dirty hack to make this driver work from devicetree
+++ /dev/null
-From 49ff5bd7d4d51a8eb05796f130e9a1a96d18f522 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 17 Apr 2013 13:38:14 -0300
-Subject: [PATCH 106/203] mtd: nand: pxa3xx: Move buffer release code to its
- own function
-
-Create a function to release the buffer and the dma channel, thus undoing
-what pxa3xx_nand_init_buff() did. This commit makes the code more readable
-and will allow to handle non-DMA capable platforms easier.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 26 ++++++++++++++------------
- 1 file changed, 14 insertions(+), 12 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -912,6 +912,18 @@ static int pxa3xx_nand_init_buff(struct
- return 0;
- }
-
-+static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
-+{
-+ struct platform_device *pdev = info->pdev;
-+ if (use_dma) {
-+ pxa_free_dma(info->data_dma_ch);
-+ dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
-+ info->data_buff, info->data_buff_phys);
-+ } else {
-+ kfree(info->data_buff);
-+ }
-+}
-+
- static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
- {
- struct mtd_info *mtd;
-@@ -1137,12 +1149,7 @@ static int alloc_nand_resource(struct pl
-
- fail_free_buf:
- free_irq(irq, info);
-- if (use_dma) {
-- pxa_free_dma(info->data_dma_ch);
-- dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
-- info->data_buff, info->data_buff_phys);
-- } else
-- kfree(info->data_buff);
-+ pxa3xx_nand_free_buff(info);
- fail_disable_clk:
- clk_disable_unprepare(info->clk);
- return ret;
-@@ -1163,12 +1170,7 @@ static int pxa3xx_nand_remove(struct pla
- irq = platform_get_irq(pdev, 0);
- if (irq >= 0)
- free_irq(irq, info);
-- if (use_dma) {
-- pxa_free_dma(info->data_dma_ch);
-- dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE,
-- info->data_buff, info->data_buff_phys);
-- } else
-- kfree(info->data_buff);
-+ pxa3xx_nand_free_buff(info);
-
- clk_disable_unprepare(info->clk);
-
+++ /dev/null
-From c16f0b44984bc623621d26df22823b50f13f65d8 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 14 May 2013 08:15:21 -0300
-Subject: [PATCH 107/203] mtd: nand: pxa3xx: Set info->use_dma properly
-
-Currently, the variable info->use_dma is never set and always
-zero-valued which means the driver never does DMA transfers.
-We fix this by simply setting info->use_dma to the module parameter,
-also named 'use_dma'. Note that the module parameter has the same name,
-but different semantics.
-
-This fixes a regression introduced by the below commit
-which removed the info->use_dma variable set.
-
- commit 4eb2da8994042d68e84e31138788429a102da2ea
- Author: Lei Wen <leiwen@marvell.com>
- Date: Mon Feb 28 10:32:13 2011 +0800
-
- mtd: pxa3xx_nand: unify prepare command
-
-Before the above commit, the driver had use_dma=1 on all NAND commands
-except on CMD_STATUS. This behavior is long lost and we are not
-recovering in this patch, either.
-
-This was spotted and verified by human inspection.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
-Acked-by: Igor Grinberg <grinberg@compulab.co.il>
-Reviewed-by: Haojian Zhuang <haojian.zhuang@gmail.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -506,6 +506,7 @@ static int prepare_command_pool(struct p
- info->buf_count = 0;
- info->oob_size = 0;
- info->use_ecc = 0;
-+ info->use_dma = (use_dma) ? 1 : 0;
- info->is_ready = 0;
- info->retcode = ERR_NONE;
- if (info->cs != 0)
+++ /dev/null
-From baef6bdc8a3e9cb30ab254fd23eb655d592a19df Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 14 May 2013 08:15:22 -0300
-Subject: [PATCH 108/203] mtd: nand: pxa3xx: Use of_machine_is_compatible()
-
-This patch replaces cpu_is_pxa3xx() with of_machine_is_compatible()
-which allows to build this driver for other platforms than ARCH_PXA.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
-Acked-by: Igor Grinberg <grinberg@compulab.co.il>
-Reviewed-by: Haojian Zhuang <haojian.zhuang@gmail.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1094,7 +1094,7 @@ static int alloc_nand_resource(struct pl
- * bindings. It can be removed once we have a prober DMA controller
- * framework for DT.
- */
-- if (pdev->dev.of_node && cpu_is_pxa3xx()) {
-+ if (pdev->dev.of_node && of_machine_is_compatible("marvell,pxa3xx")) {
- info->drcmr_dat = 97;
- info->drcmr_cmd = 99;
- } else {
+++ /dev/null
-From 3bda9dc1472596d094f020ab7231466d54b6fe00 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 14 May 2013 08:15:23 -0300
-Subject: [PATCH 109/203] mtd: nand: pxa3xx: Fix MODULE_DEVICE_TABLE
- declaration
-
-This module's device table is incorrectly declared using
-i2c_pxa_dt_ids, instead of pxa3xx_nand_dt_ids.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
-Acked-by: Igor Grinberg <grinberg@compulab.co.il>
-Reviewed-by: Haojian Zhuang <haojian.zhuang@gmail.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1185,7 +1185,7 @@ static struct of_device_id pxa3xx_nand_d
- { .compatible = "marvell,pxa3xx-nand" },
- {}
- };
--MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
-+MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
-
- static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
- {
+++ /dev/null
-From 82dad325809637899313315c3103985df94c90a5 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 14 May 2013 08:15:24 -0300
-Subject: [PATCH 110/203] mtd: nand: pxa3xx: Add address support for READID
- command
-
-This allows to support READID ONFI command which sends 0x20
-as address together with the 0x90 READID command.
-
-This is required to detect ONFI compliant devices.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
-Acked-by: Igor Grinberg <grinberg@compulab.co.il>
-Reviewed-by: Haojian Zhuang <haojian.zhuang@gmail.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -596,6 +596,7 @@ static int prepare_command_pool(struct p
- info->ndcb0 |= NDCB0_CMD_TYPE(3)
- | NDCB0_ADDR_CYC(1)
- | cmd;
-+ info->ndcb1 = (column & 0xFF);
-
- info->data_size = 8;
- break;
+++ /dev/null
-From 9d6e063c1fb2cb10e6e0c3883ca3d1944dadcfc4 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 14 May 2013 08:15:25 -0300
-Subject: [PATCH 111/203] mtd: nand: pxa3xx: Add support for Read parameter
- page command
-
-This command is required to identify ONFI-compliant devices.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
-Acked-by: Igor Grinberg <grinberg@compulab.co.il>
-Reviewed-by: Haojian Zhuang <haojian.zhuang@gmail.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -590,6 +590,16 @@ static int prepare_command_pool(struct p
- | addr_cycle;
- break;
-
-+ case NAND_CMD_PARAM:
-+ cmd = NAND_CMD_PARAM;
-+ info->buf_count = 256;
-+ info->ndcb0 |= NDCB0_CMD_TYPE(0)
-+ | NDCB0_ADDR_CYC(1)
-+ | cmd;
-+ info->ndcb1 = (column & 0xFF);
-+ info->data_size = 256;
-+ break;
-+
- case NAND_CMD_READID:
- cmd = host->cmdset->read_id;
- info->buf_count = host->read_id_bytes;
+++ /dev/null
-From 03ab29791d222be44a7e2f5716f8a1cdbcf76ceb Mon Sep 17 00:00:00 2001
-From: Jingoo Han <jg1.han@samsung.com>
-Date: Tue, 7 May 2013 15:44:14 +0900
-Subject: [PATCH 112/203] mtd: nand: pxa3xx_nand: remove unnecessary
- platform_set_drvdata()
-
-The driver core clears the driver data to NULL after device_release
-or on probe failure, since commit 0998d0631001288a5974afc0b2a5f568bcdecb4d
-(device-core: Ensure drvdata = NULL when no driver is bound).
-Thus, it is not needed to manually clear the device driver data to NULL.
-
-Signed-off-by: Jingoo Han <jg1.han@samsung.com>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1177,7 +1177,6 @@ static int pxa3xx_nand_remove(struct pla
- return 0;
-
- pdata = pdev->dev.platform_data;
-- platform_set_drvdata(pdev, NULL);
-
- irq = platform_get_irq(pdev, 0);
- if (irq >= 0)
+++ /dev/null
-From f37031e030eb05ba579c82b9e0424d2608c1ad67 Mon Sep 17 00:00:00 2001
-From: Jingoo Han <jg1.han@samsung.com>
-Date: Tue, 30 Jul 2013 17:18:33 +0900
-Subject: [PATCH 113/203] mtd: nand: use dev_get_platdata()
-
-Use the wrapper function for retrieving the platform data instead of
-accessing dev->platform_data directly.
-
-Signed-off-by: Jingoo Han <jg1.han@samsung.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -815,7 +815,7 @@ static int pxa3xx_nand_config_flash(stru
- const struct pxa3xx_nand_flash *f)
- {
- struct platform_device *pdev = info->pdev;
-- struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
-+ struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
- struct pxa3xx_nand_host *host = info->host[info->cs];
- uint32_t ndcr = 0x0; /* enable all interrupts */
-
-@@ -958,7 +958,7 @@ static int pxa3xx_nand_scan(struct mtd_i
- struct pxa3xx_nand_host *host = mtd->priv;
- struct pxa3xx_nand_info *info = host->info_data;
- struct platform_device *pdev = info->pdev;
-- struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
-+ struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
- struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
- const struct pxa3xx_nand_flash *f = NULL;
- struct nand_chip *chip = mtd->priv;
-@@ -1058,7 +1058,7 @@ static int alloc_nand_resource(struct pl
- struct resource *r;
- int ret, irq, cs;
-
-- pdata = pdev->dev.platform_data;
-+ pdata = dev_get_platdata(&pdev->dev);
- info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
- sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
- if (!info)
-@@ -1176,7 +1176,7 @@ static int pxa3xx_nand_remove(struct pla
- if (!info)
- return 0;
-
-- pdata = pdev->dev.platform_data;
-+ pdata = dev_get_platdata(&pdev->dev);
-
- irq = platform_get_irq(pdev, 0);
- if (irq >= 0)
-@@ -1239,7 +1239,7 @@ static int pxa3xx_nand_probe(struct plat
- if (ret)
- return ret;
-
-- pdata = pdev->dev.platform_data;
-+ pdata = dev_get_platdata(&pdev->dev);
- if (!pdata) {
- dev_err(&pdev->dev, "no platform data defined\n");
- return -ENODEV;
-@@ -1286,7 +1286,7 @@ static int pxa3xx_nand_suspend(struct pl
- struct mtd_info *mtd;
- int cs;
-
-- pdata = pdev->dev.platform_data;
-+ pdata = dev_get_platdata(&pdev->dev);
- if (info->state) {
- dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
- return -EAGAIN;
-@@ -1307,7 +1307,7 @@ static int pxa3xx_nand_resume(struct pla
- struct mtd_info *mtd;
- int cs;
-
-- pdata = pdev->dev.platform_data;
-+ pdata = dev_get_platdata(&pdev->dev);
- /* We don't want to handle interrupt without calling mtd routine */
- disable_int(info, NDCR_INT_MASK);
-
+++ /dev/null
-From 259e46e4327a9937761fd3f7bc07e208b1fa50e6 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Sat, 10 Aug 2013 16:34:52 -0300
-Subject: [PATCH 114/203] mtd: nand: pxa3xx: Introduce 'marvell,armada370-nand'
- compatible string
-
-This driver supports NFCv1 (as found in PXA SoC) and NFCv2 (as found in
-Armada 370/XP SoC). As both controller has a few differences, a way of
-distinguishing between the two is needed.
-
-This commit introduces a new compatible string 'marvell,armada370-nand'
-and assigns a compatible data of type enum pxa3xx_nand_variant to allow
-such distinction.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Cc: devicetree@vger.kernel.org
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 31 ++++++++++++++++++++++++++++++-
- 1 file changed, 30 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -123,6 +123,11 @@ enum {
- STATE_READY,
- };
-
-+enum pxa3xx_nand_variant {
-+ PXA3XX_NAND_VARIANT_PXA,
-+ PXA3XX_NAND_VARIANT_ARMADA370,
-+};
-+
- struct pxa3xx_nand_host {
- struct nand_chip chip;
- struct pxa3xx_nand_cmdset *cmdset;
-@@ -171,6 +176,12 @@ struct pxa3xx_nand_info {
- struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
- unsigned int state;
-
-+ /*
-+ * This driver supports NFCv1 (as found in PXA SoC)
-+ * and NFCv2 (as found in Armada 370/XP SoC).
-+ */
-+ enum pxa3xx_nand_variant variant;
-+
- int cs;
- int use_ecc; /* use HW ECC ? */
- int use_dma; /* use DMA ? */
-@@ -1192,11 +1203,28 @@ static int pxa3xx_nand_remove(struct pla
-
- #ifdef CONFIG_OF
- static struct of_device_id pxa3xx_nand_dt_ids[] = {
-- { .compatible = "marvell,pxa3xx-nand" },
-+ {
-+ .compatible = "marvell,pxa3xx-nand",
-+ .data = (void *)PXA3XX_NAND_VARIANT_PXA,
-+ },
-+ {
-+ .compatible = "marvell,armada370-nand",
-+ .data = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
-+ },
- {}
- };
- MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
-
-+static enum pxa3xx_nand_variant
-+pxa3xx_nand_get_variant(struct platform_device *pdev)
-+{
-+ const struct of_device_id *of_id =
-+ of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
-+ if (!of_id)
-+ return PXA3XX_NAND_VARIANT_PXA;
-+ return (enum pxa3xx_nand_variant)of_id->data;
-+}
-+
- static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
- {
- struct pxa3xx_nand_platform_data *pdata;
-@@ -1252,6 +1280,7 @@ static int pxa3xx_nand_probe(struct plat
- }
-
- info = platform_get_drvdata(pdev);
-+ info->variant = pxa3xx_nand_get_variant(pdev);
- probe_success = 0;
- for (cs = 0; cs < pdata->num_cs; cs++) {
- info->cs = cs;
+++ /dev/null
-From d6af8f27223a244d74ab44842bdec707c97cfe55 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:48 -0300
-Subject: [PATCH 115/203] mtd: nand: pxa3xx: Handle ECC and DMA enable/disable
- properly
-
-When ECC is not selected, the ECC enable bit must be cleared
-in the NAND control register. Same applies to DMA.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -314,8 +314,17 @@ static void pxa3xx_nand_start(struct pxa
- uint32_t ndcr;
-
- ndcr = host->reg_ndcr;
-- ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
-- ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
-+
-+ if (info->use_ecc)
-+ ndcr |= NDCR_ECC_EN;
-+ else
-+ ndcr &= ~NDCR_ECC_EN;
-+
-+ if (info->use_dma)
-+ ndcr |= NDCR_DMA_EN;
-+ else
-+ ndcr &= ~NDCR_DMA_EN;
-+
- ndcr |= NDCR_ND_RUN;
-
- /* clear status bits and run */
+++ /dev/null
-From be5f1d59341e48dbe0730253417c52bf79c6c3a7 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:49 -0300
-Subject: [PATCH 116/203] mtd: nand: pxa3xx: Allow to set/clear the 'spare
- enable' field
-
-Some commands (such as the ONFI parameter page read) need to
-clear the 'spare enable' bit. This commit allows to set/clear
-depending on the prepared command, instead of having it always
-set.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -185,6 +185,7 @@ struct pxa3xx_nand_info {
- int cs;
- int use_ecc; /* use HW ECC ? */
- int use_dma; /* use DMA ? */
-+ int use_spare; /* use spare ? */
- int is_ready;
-
- unsigned int page_size; /* page size of attached chip */
-@@ -325,6 +326,11 @@ static void pxa3xx_nand_start(struct pxa
- else
- ndcr &= ~NDCR_DMA_EN;
-
-+ if (info->use_spare)
-+ ndcr |= NDCR_SPARE_EN;
-+ else
-+ ndcr &= ~NDCR_SPARE_EN;
-+
- ndcr |= NDCR_ND_RUN;
-
- /* clear status bits and run */
-@@ -526,6 +532,7 @@ static int prepare_command_pool(struct p
- info->buf_count = 0;
- info->oob_size = 0;
- info->use_ecc = 0;
-+ info->use_spare = 1;
- info->use_dma = (use_dma) ? 1 : 0;
- info->is_ready = 0;
- info->retcode = ERR_NONE;
+++ /dev/null
-From 6bbda039fe5e9d1b3c04f4f0dd8479a2c102d28e Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:50 -0300
-Subject: [PATCH 117/203] mtd: nand: pxa3xx: Support command buffer #3
-
-Some newer controllers support a fourth command buffer. This additional
-command buffer allows to set an arbitrary length count, using the
-NDCB3.NDLENCNT field, to perform non-standard length operations
-such as the ONFI parameter page read.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -197,6 +197,7 @@ struct pxa3xx_nand_info {
- uint32_t ndcb0;
- uint32_t ndcb1;
- uint32_t ndcb2;
-+ uint32_t ndcb3;
- };
-
- static bool use_dma = 1;
-@@ -493,9 +494,22 @@ static irqreturn_t pxa3xx_nand_irq(int i
- nand_writel(info, NDSR, NDSR_WRCMDREQ);
- status &= ~NDSR_WRCMDREQ;
- info->state = STATE_CMD_HANDLE;
-+
-+ /*
-+ * Command buffer registers NDCB{0-2} (and optionally NDCB3)
-+ * must be loaded by writing directly either 12 or 16
-+ * bytes directly to NDCB0, four bytes at a time.
-+ *
-+ * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
-+ * but each NDCBx register can be read.
-+ */
- nand_writel(info, NDCB0, info->ndcb0);
- nand_writel(info, NDCB0, info->ndcb1);
- nand_writel(info, NDCB0, info->ndcb2);
-+
-+ /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
-+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
-+ nand_writel(info, NDCB0, info->ndcb3);
- }
-
- /* clear NDSR to let the controller exit the IRQ */
-@@ -554,6 +568,7 @@ static int prepare_command_pool(struct p
- default:
- info->ndcb1 = 0;
- info->ndcb2 = 0;
-+ info->ndcb3 = 0;
- break;
- }
-
+++ /dev/null
-From adbba4cf6ea15c2acb53e3fd9fc03c6b37f1f1fc Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:51 -0300
-Subject: [PATCH 118/203] mtd: nand: pxa3xx: Use 'length override' in ONFI
- paramater page read
-
-The ONFI command 'parameter page read' needs a non-standard length.
-Therefore, we enable the 'length override' field in NDCB0 and set
-a non-zero 'length count' in NDCB3.
-
-Additionally, the 'spare enable' bit must be disabled for any command
-that sets a non-zero 'length count' in NDCB3.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -80,6 +80,7 @@
- #define NDSR_RDDREQ (0x1 << 1)
- #define NDSR_WRCMDREQ (0x1)
-
-+#define NDCB0_LEN_OVRD (0x1 << 28)
- #define NDCB0_ST_ROW_EN (0x1 << 26)
- #define NDCB0_AUTO_RS (0x1 << 25)
- #define NDCB0_CSEL (0x1 << 24)
-@@ -562,6 +563,9 @@ static int prepare_command_pool(struct p
- case NAND_CMD_READOOB:
- pxa3xx_set_datasize(info);
- break;
-+ case NAND_CMD_PARAM:
-+ info->use_spare = 0;
-+ break;
- case NAND_CMD_SEQIN:
- exec_cmd = 0;
- break;
-@@ -637,8 +641,10 @@ static int prepare_command_pool(struct p
- info->buf_count = 256;
- info->ndcb0 |= NDCB0_CMD_TYPE(0)
- | NDCB0_ADDR_CYC(1)
-+ | NDCB0_LEN_OVRD
- | cmd;
- info->ndcb1 = (column & 0xFF);
-+ info->ndcb3 = 256;
- info->data_size = 256;
- break;
-
+++ /dev/null
-From 9f27a3899318ef0c4c147ed2d84cfbfb339d9bb6 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:52 -0300
-Subject: [PATCH 119/203] mtd: nand: pxa3xx: Add a local loop variable
-
-This is just a cosmetic change, to make the code more readable.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1320,8 +1320,9 @@ static int pxa3xx_nand_probe(struct plat
- info->variant = pxa3xx_nand_get_variant(pdev);
- probe_success = 0;
- for (cs = 0; cs < pdata->num_cs; cs++) {
-+ struct mtd_info *mtd = info->host[cs]->mtd;
- info->cs = cs;
-- ret = pxa3xx_nand_scan(info->host[cs]->mtd);
-+ ret = pxa3xx_nand_scan(mtd);
- if (ret) {
- dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
- cs);
-@@ -1329,7 +1330,7 @@ static int pxa3xx_nand_probe(struct plat
- }
-
- ppdata.of_node = pdev->dev.of_node;
-- ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
-+ ret = mtd_device_parse_register(mtd, NULL,
- &ppdata, pdata->parts[cs],
- pdata->nr_parts[cs]);
- if (!ret)
+++ /dev/null
-From 96d8ffc47c7ee9689b8b48ac9588e0b00fa9bd44 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:53 -0300
-Subject: [PATCH 120/203] mtd: nand: pxa3xx: Remove hardcoded mtd name
-
-There's no advantage in using a hardcoded name for the mtd device.
-Instead use the provided by the platform_device.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -244,8 +244,6 @@ static struct pxa3xx_nand_flash builtin_
- /* Define a default flash type setting serve as flash detecting only */
- #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
-
--const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
--
- #define NDTR0_tCH(c) (min((c), 7) << 19)
- #define NDTR0_tCS(c) (min((c), 7) << 16)
- #define NDTR0_tWH(c) (min((c), 7) << 11)
-@@ -1091,8 +1089,6 @@ KEEP_CONFIG:
- host->row_addr_cycles = 3;
- else
- host->row_addr_cycles = 2;
--
-- mtd->name = mtd_names[0];
- return nand_scan_tail(mtd);
- }
-
-@@ -1321,6 +1317,8 @@ static int pxa3xx_nand_probe(struct plat
- probe_success = 0;
- for (cs = 0; cs < pdata->num_cs; cs++) {
- struct mtd_info *mtd = info->host[cs]->mtd;
-+
-+ mtd->name = pdev->name;
- info->cs = cs;
- ret = pxa3xx_nand_scan(mtd);
- if (ret) {
+++ /dev/null
-From 45d36da3f284cd424b0ac2060cfccc17f9979552 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:54 -0300
-Subject: [PATCH 121/203] mtd: nand: pxa3xx: Remove unneeded internal cmdset
-
-Use the defined macros for NAND command instead of using a constant
-internal structure. This commit is only a cleanup, there's no
-functionality modification.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 63 ++++++++-------------------
- include/linux/platform_data/mtd-nand-pxa3xx.h | 13 ------
- 2 files changed, 17 insertions(+), 59 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -131,7 +131,6 @@ enum pxa3xx_nand_variant {
-
- struct pxa3xx_nand_host {
- struct nand_chip chip;
-- struct pxa3xx_nand_cmdset *cmdset;
- struct mtd_info *mtd;
- void *info_data;
-
-@@ -205,23 +204,6 @@ static bool use_dma = 1;
- module_param(use_dma, bool, 0444);
- MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
-
--/*
-- * Default NAND flash controller configuration setup by the
-- * bootloader. This configuration is used only when pdata->keep_config is set
-- */
--static struct pxa3xx_nand_cmdset default_cmdset = {
-- .read1 = 0x3000,
-- .read2 = 0x0050,
-- .program = 0x1080,
-- .read_status = 0x0070,
-- .read_id = 0x0090,
-- .erase = 0xD060,
-- .reset = 0x00FF,
-- .lock = 0x002A,
-- .unlock = 0x2423,
-- .lock_status = 0x007A,
--};
--
- static struct pxa3xx_nand_timing timing[] = {
- { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
- { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
-@@ -530,7 +512,6 @@ static inline int is_buf_blank(uint8_t *
- static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
- uint16_t column, int page_addr)
- {
-- uint16_t cmd;
- int addr_cycle, exec_cmd;
- struct pxa3xx_nand_host *host;
- struct mtd_info *mtd;
-@@ -580,21 +561,17 @@ static int prepare_command_pool(struct p
- switch (command) {
- case NAND_CMD_READOOB:
- case NAND_CMD_READ0:
-- cmd = host->cmdset->read1;
-+ info->buf_start = column;
-+ info->ndcb0 |= NDCB0_CMD_TYPE(0)
-+ | addr_cycle
-+ | NAND_CMD_READ0;
-+
- if (command == NAND_CMD_READOOB)
-- info->buf_start = mtd->writesize + column;
-- else
-- info->buf_start = column;
-+ info->buf_start += mtd->writesize;
-
-- if (unlikely(host->page_size < PAGE_CHUNK_SIZE))
-- info->ndcb0 |= NDCB0_CMD_TYPE(0)
-- | addr_cycle
-- | (cmd & NDCB0_CMD1_MASK);
-- else
-- info->ndcb0 |= NDCB0_CMD_TYPE(0)
-- | NDCB0_DBC
-- | addr_cycle
-- | cmd;
-+ /* Second command setting for large pages */
-+ if (host->page_size >= PAGE_CHUNK_SIZE)
-+ info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
-
- case NAND_CMD_SEQIN:
- /* small page addr setting */
-@@ -625,62 +602,58 @@ static int prepare_command_pool(struct p
- break;
- }
-
-- cmd = host->cmdset->program;
- info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
- | NDCB0_AUTO_RS
- | NDCB0_ST_ROW_EN
- | NDCB0_DBC
-- | cmd
-+ | (NAND_CMD_PAGEPROG << 8)
-+ | NAND_CMD_SEQIN
- | addr_cycle;
- break;
-
- case NAND_CMD_PARAM:
-- cmd = NAND_CMD_PARAM;
- info->buf_count = 256;
- info->ndcb0 |= NDCB0_CMD_TYPE(0)
- | NDCB0_ADDR_CYC(1)
- | NDCB0_LEN_OVRD
-- | cmd;
-+ | command;
- info->ndcb1 = (column & 0xFF);
- info->ndcb3 = 256;
- info->data_size = 256;
- break;
-
- case NAND_CMD_READID:
-- cmd = host->cmdset->read_id;
- info->buf_count = host->read_id_bytes;
- info->ndcb0 |= NDCB0_CMD_TYPE(3)
- | NDCB0_ADDR_CYC(1)
-- | cmd;
-+ | command;
- info->ndcb1 = (column & 0xFF);
-
- info->data_size = 8;
- break;
- case NAND_CMD_STATUS:
-- cmd = host->cmdset->read_status;
- info->buf_count = 1;
- info->ndcb0 |= NDCB0_CMD_TYPE(4)
- | NDCB0_ADDR_CYC(1)
-- | cmd;
-+ | command;
-
- info->data_size = 8;
- break;
-
- case NAND_CMD_ERASE1:
-- cmd = host->cmdset->erase;
- info->ndcb0 |= NDCB0_CMD_TYPE(2)
- | NDCB0_AUTO_RS
- | NDCB0_ADDR_CYC(3)
- | NDCB0_DBC
-- | cmd;
-+ | (NAND_CMD_ERASE2 << 8)
-+ | NAND_CMD_ERASE1;
- info->ndcb1 = page_addr;
- info->ndcb2 = 0;
-
- break;
- case NAND_CMD_RESET:
-- cmd = host->cmdset->reset;
- info->ndcb0 |= NDCB0_CMD_TYPE(5)
-- | cmd;
-+ | command;
-
- break;
-
-@@ -876,7 +849,6 @@ static int pxa3xx_nand_config_flash(stru
- }
-
- /* calculate flash information */
-- host->cmdset = &default_cmdset;
- host->page_size = f->page_size;
- host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
-
-@@ -922,7 +894,6 @@ static int pxa3xx_nand_detect_config(str
- }
-
- host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
-- host->cmdset = &default_cmdset;
-
- host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
- host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
---- a/include/linux/platform_data/mtd-nand-pxa3xx.h
-+++ b/include/linux/platform_data/mtd-nand-pxa3xx.h
-@@ -16,19 +16,6 @@ struct pxa3xx_nand_timing {
- unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
- };
-
--struct pxa3xx_nand_cmdset {
-- uint16_t read1;
-- uint16_t read2;
-- uint16_t program;
-- uint16_t read_status;
-- uint16_t read_id;
-- uint16_t erase;
-- uint16_t reset;
-- uint16_t lock;
-- uint16_t unlock;
-- uint16_t lock_status;
--};
--
- struct pxa3xx_nand_flash {
- char *name;
- uint32_t chip_id;
+++ /dev/null
-From 5c5367d7f9ad835b3b8a2dddfbe90e4c6e669084 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:55 -0300
-Subject: [PATCH 122/203] mtd: nand: pxa3xx: Move cached registers to info
- structure
-
-This registers are not per-chip (aka host) but controller-wide,
-so it's better to store them in the global 'info' structure.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 36 +++++++++++++++++-------------------
- 1 file changed, 17 insertions(+), 19 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -144,10 +144,6 @@ struct pxa3xx_nand_host {
- unsigned int row_addr_cycles;
- size_t read_id_bytes;
-
-- /* cached register value */
-- uint32_t reg_ndcr;
-- uint32_t ndtr0cs0;
-- uint32_t ndtr1cs0;
- };
-
- struct pxa3xx_nand_info {
-@@ -193,6 +189,11 @@ struct pxa3xx_nand_info {
- unsigned int oob_size;
- int retcode;
-
-+ /* cached register value */
-+ uint32_t reg_ndcr;
-+ uint32_t ndtr0cs0;
-+ uint32_t ndtr1cs0;
-+
- /* generated NDCBx register values */
- uint32_t ndcb0;
- uint32_t ndcb1;
-@@ -258,8 +259,8 @@ static void pxa3xx_nand_set_timing(struc
- NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
- NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
-
-- host->ndtr0cs0 = ndtr0;
-- host->ndtr1cs0 = ndtr1;
-+ info->ndtr0cs0 = ndtr0;
-+ info->ndtr1cs0 = ndtr1;
- nand_writel(info, NDTR0CS0, ndtr0);
- nand_writel(info, NDTR1CS0, ndtr1);
- }
-@@ -267,7 +268,7 @@ static void pxa3xx_nand_set_timing(struc
- static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
- {
- struct pxa3xx_nand_host *host = info->host[info->cs];
-- int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
-+ int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
-
- info->data_size = host->page_size;
- if (!oob_enable) {
-@@ -293,10 +294,9 @@ static void pxa3xx_set_datasize(struct p
- */
- static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
- {
-- struct pxa3xx_nand_host *host = info->host[info->cs];
- uint32_t ndcr;
-
-- ndcr = host->reg_ndcr;
-+ ndcr = info->reg_ndcr;
-
- if (info->use_ecc)
- ndcr |= NDCR_ECC_EN;
-@@ -683,7 +683,7 @@ static void pxa3xx_nand_cmdfunc(struct m
- * "byte" address into a "word" address appropriate
- * for indexing a word-oriented device
- */
-- if (host->reg_ndcr & NDCR_DWIDTH_M)
-+ if (info->reg_ndcr & NDCR_DWIDTH_M)
- column /= 2;
-
- /*
-@@ -693,8 +693,8 @@ static void pxa3xx_nand_cmdfunc(struct m
- */
- if (info->cs != host->cs) {
- info->cs = host->cs;
-- nand_writel(info, NDTR0CS0, host->ndtr0cs0);
-- nand_writel(info, NDTR1CS0, host->ndtr1cs0);
-+ nand_writel(info, NDTR0CS0, info->ndtr0cs0);
-+ nand_writel(info, NDTR1CS0, info->ndtr1cs0);
- }
-
- info->state = STATE_PREPARED;
-@@ -870,7 +870,7 @@ static int pxa3xx_nand_config_flash(stru
- ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
- ndcr |= NDCR_SPARE_EN; /* enable spare by default */
-
-- host->reg_ndcr = ndcr;
-+ info->reg_ndcr = ndcr;
-
- pxa3xx_nand_set_timing(host, f->timing);
- return 0;
-@@ -893,11 +893,9 @@ static int pxa3xx_nand_detect_config(str
- host->read_id_bytes = 2;
- }
-
-- host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
--
-- host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
-- host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
--
-+ info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
-+ info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
-+ info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
- return 0;
- }
-
-@@ -1044,7 +1042,7 @@ KEEP_CONFIG:
- chip->ecc.size = host->page_size;
- chip->ecc.strength = 1;
-
-- if (host->reg_ndcr & NDCR_DWIDTH_M)
-+ if (info->reg_ndcr & NDCR_DWIDTH_M)
- chip->options |= NAND_BUSWIDTH_16;
-
- if (nand_scan_ident(mtd, 1, def))
+++ /dev/null
-From 085ced2b9e159dbeae029e338958b8c8ae9073b9 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:56 -0300
-Subject: [PATCH 123/203] mtd: nand: pxa3xx: Make dma code dependent on dma
- capable platforms
-
-This patch adds a macro ARCH_HAS_DMA to compile-out arch specific
-dma code, namely pxa_request_dma() and pxa_free_dma(). These symbols
-are available only in pxa, which makes impossible to build the driver in
-other platforms than ARCH_PXA.
-
-In order to handle non-dma capable platforms, we implement a fallbacks that
-allocate buffers as if 'use_dma=false', putting the dma related code
-under the ARCH_HAS_DMA conditional.
-
-Please note that the correct way to handle this is to migrate the
-dma code to use of the mmp_pdma dmaengine driver. However, currently
-this is not possible because the two dmaengine drivers can't work together.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 34 ++++++++++++++++++++++++++++++++++
- 1 file changed, 34 insertions(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -25,7 +25,14 @@
- #include <linux/of.h>
- #include <linux/of_device.h>
-
-+#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
-+#define ARCH_HAS_DMA
-+#endif
-+
-+#ifdef ARCH_HAS_DMA
- #include <mach/dma.h>
-+#endif
-+
- #include <linux/platform_data/mtd-nand-pxa3xx.h>
-
- #define CHIP_DELAY_TIMEOUT (2 * HZ/10)
-@@ -381,6 +388,7 @@ static void handle_data_pio(struct pxa3x
- }
- }
-
-+#ifdef ARCH_HAS_DMA
- static void start_data_dma(struct pxa3xx_nand_info *info)
- {
- struct pxa_dma_desc *desc = info->data_desc;
-@@ -427,6 +435,10 @@ static void pxa3xx_nand_data_dma_irq(int
- enable_int(info, NDCR_INT_MASK);
- nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
- }
-+#else
-+static void start_data_dma(struct pxa3xx_nand_info *info)
-+{}
-+#endif
-
- static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
- {
-@@ -905,6 +917,7 @@ static int pxa3xx_nand_detect_config(str
- */
- #define MAX_BUFF_SIZE PAGE_SIZE
-
-+#ifdef ARCH_HAS_DMA
- static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
- {
- struct platform_device *pdev = info->pdev;
-@@ -950,6 +963,20 @@ static void pxa3xx_nand_free_buff(struct
- kfree(info->data_buff);
- }
- }
-+#else
-+static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
-+{
-+ info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
-+ if (info->data_buff == NULL)
-+ return -ENOMEM;
-+ return 0;
-+}
-+
-+static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
-+{
-+ kfree(info->data_buff);
-+}
-+#endif
-
- static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
- {
-@@ -1265,6 +1292,13 @@ static int pxa3xx_nand_probe(struct plat
- struct pxa3xx_nand_info *info;
- int ret, cs, probe_success;
-
-+#ifndef ARCH_HAS_DMA
-+ if (use_dma) {
-+ use_dma = 0;
-+ dev_warn(&pdev->dev,
-+ "This platform can't do DMA on this device\n");
-+ }
-+#endif
- ret = pxa3xx_nand_probe_dt(pdev);
- if (ret)
- return ret;
+++ /dev/null
-From d6d4e28e52f3cd70f60d03405181994a2763532b Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:57 -0300
-Subject: [PATCH 124/203] mtd: nand: pxa3xx: Add __maybe_unused keyword to
- enable_int()
-
-Now that we have added ARCH_HAS_DMA conditional the function
-enable_int() may be unused. Declare it as __maybe_unused,
-in order to remove the following warning, when the function is not used:
-
-drivers/mtd/nand//pxa3xx_nand.c:343:24: warning: 'enable_int' defined
-but not used [-Wunused-function]
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -348,7 +348,8 @@ static void pxa3xx_nand_stop(struct pxa3
- nand_writel(info, NDSR, NDSR_MASK);
- }
-
--static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
-+static void __maybe_unused
-+enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
- {
- uint32_t ndcr;
-
+++ /dev/null
-From c26369f5b9929e1187ccf716d6d1678196ec0b4f Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:58 -0300
-Subject: [PATCH 125/203] mtd: nand: pxa3xx: Allow devices with no dma
- resources
-
-When use_dma=0 there's no point in requesting resources for dma,
-since they won't be used anyway. Therefore we remove that requirement,
-therefore allowing devices without dma to pass the driver probe.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 51 +++++++++++++++++++++++-------------------
- 1 file changed, 28 insertions(+), 23 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1141,30 +1141,35 @@ static int alloc_nand_resource(struct pl
- if (ret < 0)
- return ret;
-
-- /*
-- * This is a dirty hack to make this driver work from devicetree
-- * bindings. It can be removed once we have a prober DMA controller
-- * framework for DT.
-- */
-- if (pdev->dev.of_node && of_machine_is_compatible("marvell,pxa3xx")) {
-- info->drcmr_dat = 97;
-- info->drcmr_cmd = 99;
-- } else {
-- r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-- if (r == NULL) {
-- dev_err(&pdev->dev, "no resource defined for data DMA\n");
-- ret = -ENXIO;
-- goto fail_disable_clk;
-- }
-- info->drcmr_dat = r->start;
-+ if (use_dma) {
-+ /*
-+ * This is a dirty hack to make this driver work from
-+ * devicetree bindings. It can be removed once we have
-+ * a prober DMA controller framework for DT.
-+ */
-+ if (pdev->dev.of_node &&
-+ of_machine_is_compatible("marvell,pxa3xx")) {
-+ info->drcmr_dat = 97;
-+ info->drcmr_cmd = 99;
-+ } else {
-+ r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-+ if (r == NULL) {
-+ dev_err(&pdev->dev,
-+ "no resource defined for data DMA\n");
-+ ret = -ENXIO;
-+ goto fail_disable_clk;
-+ }
-+ info->drcmr_dat = r->start;
-
-- r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
-- if (r == NULL) {
-- dev_err(&pdev->dev, "no resource defined for command DMA\n");
-- ret = -ENXIO;
-- goto fail_disable_clk;
-+ r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
-+ if (r == NULL) {
-+ dev_err(&pdev->dev,
-+ "no resource defined for cmd DMA\n");
-+ ret = -ENXIO;
-+ goto fail_disable_clk;
-+ }
-+ info->drcmr_cmd = r->start;
- }
-- info->drcmr_cmd = r->start;
- }
-
- irq = platform_get_irq(pdev, 0);
+++ /dev/null
-From 1fea4cca22fcb1045a0c1ad42df793e3ea29b5bf Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:46 -0300
-Subject: [PATCH 126/203] mtd: nand: pxa3xx: Remove unneeded ifdef CONFIG_OF
-
-There's no need to enclose this code within idef CONFIG_OF,
-because the OF framework provides no-op stubs if CONFIG_OF=n.
-
-Cc: devicetree@vger.kernel.org
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: Olof Johansson <olof@lixom.net>
----
- drivers/mtd/nand/pxa3xx_nand.c | 7 -------
- 1 file changed, 7 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1236,7 +1236,6 @@ static int pxa3xx_nand_remove(struct pla
- return 0;
- }
-
--#ifdef CONFIG_OF
- static struct of_device_id pxa3xx_nand_dt_ids[] = {
- {
- .compatible = "marvell,pxa3xx-nand",
-@@ -1284,12 +1283,6 @@ static int pxa3xx_nand_probe_dt(struct p
-
- return 0;
- }
--#else
--static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
--{
-- return 0;
--}
--#endif
-
- static int pxa3xx_nand_probe(struct platform_device *pdev)
- {
+++ /dev/null
-From fe013a7a5667763bde164dd5c9341ee5361a9c23 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Sat, 19 Oct 2013 18:19:25 -0300
-Subject: [PATCH 127/203] mtd: nand: pxa3xx: Fix registered MTD name
-
-In a recent commit:
-
- commit f455578dd961087a5cf94730d9f6489bb1d355f0
- Author: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
- Date: Mon Aug 12 14:14:53 2013 -0300
-
- mtd: nand: pxa3xx: Remove hardcoded mtd name
-
- There's no advantage in using a hardcoded name for the mtd device.
- Instead use the provided by the platform_device.
-
-The MTD name was changed to use the one provided by the platform_device.
-However, this can be problematic as some users want to set partitions
-using the kernel parameter 'mtdparts', where the name is needed.
-
-Therefore, to avoid regressions in users relying in 'mtdparts' we revert
-the change and use the previous one 'pxa3xx_nand-0'.
-
-While at it, let's put a big comment and prevent this change from happening
-ever again.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1320,7 +1320,12 @@ static int pxa3xx_nand_probe(struct plat
- for (cs = 0; cs < pdata->num_cs; cs++) {
- struct mtd_info *mtd = info->host[cs]->mtd;
-
-- mtd->name = pdev->name;
-+ /*
-+ * The mtd name matches the one used in 'mtdparts' kernel
-+ * parameter. This name cannot be changed or otherwise
-+ * user's mtd partitions configuration would get broken.
-+ */
-+ mtd->name = "pxa3xx_nand-0";
- info->cs = cs;
- ret = pxa3xx_nand_scan(mtd);
- if (ret) {
+++ /dev/null
-From 38a6d3f3330da6586695746a0a85a96143171211 Mon Sep 17 00:00:00 2001
-From: Sachin Kamat <sachin.kamat@linaro.org>
-Date: Mon, 30 Sep 2013 15:10:24 +0530
-Subject: [PATCH 128/203] mtd: nand: pxa3xx_nand: Remove redundant of_match_ptr
-
-The data structure of_match_ptr() protects is always compiled in.
-Hence of_match_ptr() is not needed.
-
-Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1412,7 +1412,7 @@ static int pxa3xx_nand_resume(struct pla
- static struct platform_driver pxa3xx_nand_driver = {
- .driver = {
- .name = "pxa3xx-nand",
-- .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
-+ .of_match_table = pxa3xx_nand_dt_ids,
- },
- .probe = pxa3xx_nand_probe,
- .remove = pxa3xx_nand_remove,
+++ /dev/null
-From 18166290599760e8ff1b6c0389834beafd09a517 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Fri, 4 Oct 2013 15:30:37 -0300
-Subject: [PATCH 129/203] mtd: nand: pxa3xx: Move DMA I/O enabling
-
-Instead of setting info->dma each time a command is prepared,
-we can move it after the DMA buffers are allocated.
-
-This is more clear and it's the proper place to enable this, given
-DMA cannot be turned on and off during runtime.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -540,7 +540,6 @@ static int prepare_command_pool(struct p
- info->oob_size = 0;
- info->use_ecc = 0;
- info->use_spare = 1;
-- info->use_dma = (use_dma) ? 1 : 0;
- info->is_ready = 0;
- info->retcode = ERR_NONE;
- if (info->cs != 0)
-@@ -950,6 +949,11 @@ static int pxa3xx_nand_init_buff(struct
- return info->data_dma_ch;
- }
-
-+ /*
-+ * Now that DMA buffers are allocated we turn on
-+ * DMA proper for I/O operations.
-+ */
-+ info->use_dma = 1;
- return 0;
- }
-
+++ /dev/null
-From 71d6267980d7590e38059a784785ca158e361f87 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Fri, 4 Oct 2013 15:30:38 -0300
-Subject: [PATCH 130/203] mtd: nand: pxa3xx: Allocate data buffer on detected
- flash size
-
-This commit replaces the currently hardcoded buffer size, by a
-dynamic detection scheme. First a small 256 bytes buffer is allocated
-so the device can be detected (using READID and friends commands).
-
-After detection, this buffer is released and a new buffer is allocated
-to acommodate the page size plus out-of-band size.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 45 ++++++++++++++++++++++++++++--------------
- 1 file changed, 30 insertions(+), 15 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -39,6 +39,13 @@
- #define NAND_STOP_DELAY (2 * HZ/50)
- #define PAGE_CHUNK_SIZE (2048)
-
-+/*
-+ * Define a buffer size for the initial command that detects the flash device:
-+ * STATUS, READID and PARAM. The largest of these is the PARAM command,
-+ * needing 256 bytes.
-+ */
-+#define INIT_BUFFER_SIZE 256
-+
- /* registers and bit definitions */
- #define NDCR (0x00) /* Control register */
- #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
-@@ -164,6 +171,7 @@ struct pxa3xx_nand_info {
-
- unsigned int buf_start;
- unsigned int buf_count;
-+ unsigned int buf_size;
-
- /* DMA information */
- int drcmr_dat;
-@@ -911,26 +919,20 @@ static int pxa3xx_nand_detect_config(str
- return 0;
- }
-
--/* the maximum possible buffer size for large page with OOB data
-- * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
-- * data buffer and the DMA descriptor
-- */
--#define MAX_BUFF_SIZE PAGE_SIZE
--
- #ifdef ARCH_HAS_DMA
- static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
- {
- struct platform_device *pdev = info->pdev;
-- int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
-+ int data_desc_offset = info->buf_size - sizeof(struct pxa_dma_desc);
-
- if (use_dma == 0) {
-- info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
-+ info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
- if (info->data_buff == NULL)
- return -ENOMEM;
- return 0;
- }
-
-- info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
-+ info->data_buff = dma_alloc_coherent(&pdev->dev, info->buf_size,
- &info->data_buff_phys, GFP_KERNEL);
- if (info->data_buff == NULL) {
- dev_err(&pdev->dev, "failed to allocate dma buffer\n");
-@@ -944,7 +946,7 @@ static int pxa3xx_nand_init_buff(struct
- pxa3xx_nand_data_dma_irq, info);
- if (info->data_dma_ch < 0) {
- dev_err(&pdev->dev, "failed to request data dma\n");
-- dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
-+ dma_free_coherent(&pdev->dev, info->buf_size,
- info->data_buff, info->data_buff_phys);
- return info->data_dma_ch;
- }
-@@ -962,7 +964,7 @@ static void pxa3xx_nand_free_buff(struct
- struct platform_device *pdev = info->pdev;
- if (use_dma) {
- pxa_free_dma(info->data_dma_ch);
-- dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
-+ dma_free_coherent(&pdev->dev, info->buf_size,
- info->data_buff, info->data_buff_phys);
- } else {
- kfree(info->data_buff);
-@@ -971,7 +973,7 @@ static void pxa3xx_nand_free_buff(struct
- #else
- static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
- {
-- info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
-+ info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
- if (info->data_buff == NULL)
- return -ENOMEM;
- return 0;
-@@ -1085,7 +1087,16 @@ KEEP_CONFIG:
- else
- host->col_addr_cycles = 1;
-
-+ /* release the initial buffer */
-+ kfree(info->data_buff);
-+
-+ /* allocate the real data + oob buffer */
-+ info->buf_size = mtd->writesize + mtd->oobsize;
-+ ret = pxa3xx_nand_init_buff(info);
-+ if (ret)
-+ return ret;
- info->oob_buff = info->data_buff + mtd->writesize;
-+
- if ((mtd->size >> chip->page_shift) > 65536)
- host->row_addr_cycles = 3;
- else
-@@ -1191,9 +1202,13 @@ static int alloc_nand_resource(struct pl
- }
- info->mmio_phys = r->start;
-
-- ret = pxa3xx_nand_init_buff(info);
-- if (ret)
-+ /* Allocate a buffer to allow flash detection */
-+ info->buf_size = INIT_BUFFER_SIZE;
-+ info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
-+ if (info->data_buff == NULL) {
-+ ret = -ENOMEM;
- goto fail_disable_clk;
-+ }
-
- /* initialize all interrupts to be disabled */
- disable_int(info, NDSR_MASK);
-@@ -1211,7 +1226,7 @@ static int alloc_nand_resource(struct pl
-
- fail_free_buf:
- free_irq(irq, info);
-- pxa3xx_nand_free_buff(info);
-+ kfree(info->data_buff);
- fail_disable_clk:
- clk_disable_unprepare(info->clk);
- return ret;
+++ /dev/null
-From e3779fc4a84e1c51c061e3e13b1abf1c9a56a2cd Mon Sep 17 00:00:00 2001
-From: Michael Opdenacker <michael.opdenacker@free-electrons.com>
-Date: Sun, 13 Oct 2013 08:21:32 +0200
-Subject: [PATCH 131/203] mtd: nand: remove deprecated IRQF_DISABLED
-
-This patch proposes to remove the use of the IRQF_DISABLED flag
-
-It's a NOOP since 2.6.35 and it will be removed one day.
-
-Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1213,8 +1213,7 @@ static int alloc_nand_resource(struct pl
- /* initialize all interrupts to be disabled */
- disable_int(info, NDSR_MASK);
-
-- ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
-- pdev->name, info);
-+ ret = request_irq(irq, pxa3xx_nand_irq, 0, pdev->name, info);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to request IRQ\n");
- goto fail_free_buf;
+++ /dev/null
-From 54c1163b143e4ed911b8dddc0829c87f93b3debd Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:10 -0300
-Subject: [PATCH 132/203] mtd: nand: pxa3xx: Add documentation about the
- controller
-
-Given there's no public specification to this date, and in order
-to capture some important details and singularities about the
-controller let's document them once and for good.
-
-Cc: linux-doc@vger.kernel.org
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -7,6 +7,8 @@
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-+ *
-+ * See Documentation/mtd/nand/pxa3xx-nand.txt for more details.
- */
-
- #include <linux/kernel.h>
+++ /dev/null
-From ec1977c2873dc7f0e6cec3edb8c30d92882f65d1 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:12 -0300
-Subject: [PATCH 133/203] mtd: nand: pxa3xx: Prevent sub-page writes
-
-The current driver doesn't support sub-page writing, so report
-that to the NAND core.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1145,6 +1145,7 @@ static int alloc_nand_resource(struct pl
- chip->read_byte = pxa3xx_nand_read_byte;
- chip->read_buf = pxa3xx_nand_read_buf;
- chip->write_buf = pxa3xx_nand_write_buf;
-+ chip->options |= NAND_NO_SUBPAGE_WRITE;
- }
-
- spin_lock_init(&chip->controller->lock);
+++ /dev/null
-From 97598678602aaea473303523ce37a45d258206ca Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:13 -0300
-Subject: [PATCH 134/203] mtd: nand: pxa3xx: read_page() returns max_bitflips
-
-As per the ecc.read_page() prototype, we must return the maximum number
-of bitflips that were corrected on any one region covering an ecc step.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -751,6 +751,7 @@ static int pxa3xx_nand_read_page_hwecc(s
- {
- struct pxa3xx_nand_host *host = mtd->priv;
- struct pxa3xx_nand_info *info = host->info_data;
-+ int max_bitflips = 0;
-
- chip->read_buf(mtd, buf, mtd->writesize);
- chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
-@@ -758,6 +759,7 @@ static int pxa3xx_nand_read_page_hwecc(s
- if (info->retcode == ERR_SBERR) {
- switch (info->use_ecc) {
- case 1:
-+ max_bitflips = 1;
- mtd->ecc_stats.corrected++;
- break;
- case 0:
-@@ -776,7 +778,7 @@ static int pxa3xx_nand_read_page_hwecc(s
- mtd->ecc_stats.failed++;
- }
-
-- return 0;
-+ return max_bitflips;
- }
-
- static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
+++ /dev/null
-From dc333ddda677d416a6726509e144c6dfb93e7e89 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:14 -0300
-Subject: [PATCH 135/203] mtd: nand: pxa3xx: Early variant detection
-
-In order to customize early settings depending on the detected SoC variant,
-move the detection to be before the nand_chip struct filling.
-
-In a follow-up patch, this change is needed to detect the variant *before*
-the call to alloc_nand_resource(), which allows to set a different cmdfunc()
-for each variant.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 48 +++++++++++++++++++++---------------------
- 1 file changed, 24 insertions(+), 24 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -258,6 +258,29 @@ static struct pxa3xx_nand_flash builtin_
- /* convert nano-seconds to nand flash controller clock cycles */
- #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
-
-+static struct of_device_id pxa3xx_nand_dt_ids[] = {
-+ {
-+ .compatible = "marvell,pxa3xx-nand",
-+ .data = (void *)PXA3XX_NAND_VARIANT_PXA,
-+ },
-+ {
-+ .compatible = "marvell,armada370-nand",
-+ .data = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
-+ },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
-+
-+static enum pxa3xx_nand_variant
-+pxa3xx_nand_get_variant(struct platform_device *pdev)
-+{
-+ const struct of_device_id *of_id =
-+ of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
-+ if (!of_id)
-+ return PXA3XX_NAND_VARIANT_PXA;
-+ return (enum pxa3xx_nand_variant)of_id->data;
-+}
-+
- static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
- const struct pxa3xx_nand_timing *t)
- {
-@@ -1125,6 +1148,7 @@ static int alloc_nand_resource(struct pl
- return -ENOMEM;
-
- info->pdev = pdev;
-+ info->variant = pxa3xx_nand_get_variant(pdev);
- for (cs = 0; cs < pdata->num_cs; cs++) {
- mtd = (struct mtd_info *)((unsigned int)&info[1] +
- (sizeof(*mtd) + sizeof(*host)) * cs);
-@@ -1259,29 +1283,6 @@ static int pxa3xx_nand_remove(struct pla
- return 0;
- }
-
--static struct of_device_id pxa3xx_nand_dt_ids[] = {
-- {
-- .compatible = "marvell,pxa3xx-nand",
-- .data = (void *)PXA3XX_NAND_VARIANT_PXA,
-- },
-- {
-- .compatible = "marvell,armada370-nand",
-- .data = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
-- },
-- {}
--};
--MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
--
--static enum pxa3xx_nand_variant
--pxa3xx_nand_get_variant(struct platform_device *pdev)
--{
-- const struct of_device_id *of_id =
-- of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
-- if (!of_id)
-- return PXA3XX_NAND_VARIANT_PXA;
-- return (enum pxa3xx_nand_variant)of_id->data;
--}
--
- static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
- {
- struct pxa3xx_nand_platform_data *pdata;
-@@ -1338,7 +1339,6 @@ static int pxa3xx_nand_probe(struct plat
- }
-
- info = platform_get_drvdata(pdev);
-- info->variant = pxa3xx_nand_get_variant(pdev);
- probe_success = 0;
- for (cs = 0; cs < pdata->num_cs; cs++) {
- struct mtd_info *mtd = info->host[cs]->mtd;
+++ /dev/null
-From 67ab922e1e292494732a10f367d3de47338639ac Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:15 -0300
-Subject: [PATCH 136/203] mtd: nand: pxa3xx: Use chip->cmdfunc instead of the
- internal
-
-Whenever possible, it's always better to use the generic chip->cmdfunc
-instead of the internal pxa3xx_nand_cmdfunc().
-In this particular case, this will allow to have multiple cmdfunc()
-implementations for different SoC variants.
-
-Reviewed-by: Huang Shijie <shijie8@gmail.com>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1015,14 +1015,18 @@ static void pxa3xx_nand_free_buff(struct
- static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
- {
- struct mtd_info *mtd;
-+ struct nand_chip *chip;
- int ret;
-+
- mtd = info->host[info->cs]->mtd;
-+ chip = mtd->priv;
-+
- /* use the common timing to make a try */
- ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
- if (ret)
- return ret;
-
-- pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
-+ chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
- if (info->is_ready)
- return 0;
-
+++ /dev/null
-From 496f307424d3958ef43ad06ae6a0be98ede2a92c Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:16 -0300
-Subject: [PATCH 137/203] mtd: nand: pxa3xx: Split FIFO size from to-be-read
- FIFO count
-
-Introduce a fifo_size field to represent the size of the controller's
-FIFO buffer, and use it to distinguish that size from the amount
-of data bytes to be read from the FIFO.
-
-This is important to support devices with pages larger than the
-controller's internal FIFO, that need to read the pages in FIFO-sized
-chunks.
-
-In particular, the current code is at least confusing, for it mixes
-all the different sizes involved: FIFO size, page size and data size.
-
-This commit starts the cleaning by removing the info->page_size field
-that is not currently used. The host->page_size field should also
-be removed and use always mtd->writesize instead. Follow up commits
-will clean this up.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 12 +++++++-----
- 1 file changed, 7 insertions(+), 5 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -201,8 +201,8 @@ struct pxa3xx_nand_info {
- int use_spare; /* use spare ? */
- int is_ready;
-
-- unsigned int page_size; /* page size of attached chip */
-- unsigned int data_size; /* data size in FIFO */
-+ unsigned int fifo_size; /* max. data size in the FIFO */
-+ unsigned int data_size; /* data to be read from FIFO */
- unsigned int oob_size;
- int retcode;
-
-@@ -307,16 +307,15 @@ static void pxa3xx_nand_set_timing(struc
-
- static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
- {
-- struct pxa3xx_nand_host *host = info->host[info->cs];
- int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
-
-- info->data_size = host->page_size;
-+ info->data_size = info->fifo_size;
- if (!oob_enable) {
- info->oob_size = 0;
- return;
- }
-
-- switch (host->page_size) {
-+ switch (info->fifo_size) {
- case 2048:
- info->oob_size = (info->use_ecc) ? 40 : 64;
- break;
-@@ -933,9 +932,12 @@ static int pxa3xx_nand_detect_config(str
- uint32_t ndcr = nand_readl(info, NDCR);
-
- if (ndcr & NDCR_PAGE_SZ) {
-+ /* Controller's FIFO size */
-+ info->fifo_size = 2048;
- host->page_size = 2048;
- host->read_id_bytes = 4;
- } else {
-+ info->fifo_size = 512;
- host->page_size = 512;
- host->read_id_bytes = 2;
- }
+++ /dev/null
-From ad40a597cbfeb2374c799ba6dad3a69f131511c8 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:17 -0300
-Subject: [PATCH 138/203] mtd: nand: pxa3xx: Replace host->page_size by
- mtd->writesize
-
-There's no need to privately store the device page size as it's
-available in mtd structure field mtd->writesize.
-Also, this removes the hardcoded page size value, leaving the
-auto-detected value only.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 10 +++-------
- 1 file changed, 3 insertions(+), 7 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -151,7 +151,6 @@ struct pxa3xx_nand_host {
- void *info_data;
-
- /* page size of attached chip */
-- unsigned int page_size;
- int use_ecc;
- int cs;
-
-@@ -614,12 +613,12 @@ static int prepare_command_pool(struct p
- info->buf_start += mtd->writesize;
-
- /* Second command setting for large pages */
-- if (host->page_size >= PAGE_CHUNK_SIZE)
-+ if (mtd->writesize >= PAGE_CHUNK_SIZE)
- info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
-
- case NAND_CMD_SEQIN:
- /* small page addr setting */
-- if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
-+ if (unlikely(mtd->writesize < PAGE_CHUNK_SIZE)) {
- info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
- | (column & 0xFF);
-
-@@ -895,7 +894,6 @@ static int pxa3xx_nand_config_flash(stru
- }
-
- /* calculate flash information */
-- host->page_size = f->page_size;
- host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
-
- /* calculate addressing information */
-@@ -934,11 +932,9 @@ static int pxa3xx_nand_detect_config(str
- if (ndcr & NDCR_PAGE_SZ) {
- /* Controller's FIFO size */
- info->fifo_size = 2048;
-- host->page_size = 2048;
- host->read_id_bytes = 4;
- } else {
- info->fifo_size = 512;
-- host->page_size = 512;
- host->read_id_bytes = 2;
- }
-
-@@ -1106,7 +1102,7 @@ static int pxa3xx_nand_scan(struct mtd_i
- def = pxa3xx_flash_ids;
- KEEP_CONFIG:
- chip->ecc.mode = NAND_ECC_HW;
-- chip->ecc.size = host->page_size;
-+ chip->ecc.size = info->fifo_size;
- chip->ecc.strength = 1;
-
- if (info->reg_ndcr & NDCR_DWIDTH_M)
+++ /dev/null
-From 8bce53e42f78e009fbfbd4a98ea98f66e6cd5b4c Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:18 -0300
-Subject: [PATCH 139/203] mtd: nand: pxa3xx: Add a nice comment to
- pxa3xx_set_datasize()
-
-Add a comment clarifying the use of pxa3xx_set_datasize() which is only
-applicable on data read/write commands (i.e. commands with a data cycle,
-such as READID, READ0, STATUS, etc.)
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -304,6 +304,11 @@ static void pxa3xx_nand_set_timing(struc
- nand_writel(info, NDTR1CS0, ndtr1);
- }
-
-+/*
-+ * Set the data and OOB size, depending on the selected
-+ * spare and ECC configuration.
-+ * Only applicable to READ0, READOOB and PAGEPROG commands.
-+ */
- static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
- {
- int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
+++ /dev/null
-From b5289e9cb18e6c254e13826e6bcfbfe95b819d77 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:26 -0300
-Subject: [PATCH 140/203] mtd: nand: pxa3xx: Use a completion to signal device
- ready
-
-The expected behavior of the waitfunc() NAND chip call is to wait
-for the device to be READY (this is a standard chip line).
-However, the current implementation does almost nothing, which opens
-the possibility of issuing a command to a non-ready device.
-
-Fix this by adding a new completion to wait for the ready event to arrive.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 38 ++++++++++++++++++++++++--------------
- 1 file changed, 24 insertions(+), 14 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -37,6 +37,7 @@
-
- #include <linux/platform_data/mtd-nand-pxa3xx.h>
-
-+#define NAND_DEV_READY_TIMEOUT 50
- #define CHIP_DELAY_TIMEOUT (2 * HZ/10)
- #define NAND_STOP_DELAY (2 * HZ/50)
- #define PAGE_CHUNK_SIZE (2048)
-@@ -168,7 +169,7 @@ struct pxa3xx_nand_info {
- struct clk *clk;
- void __iomem *mmio_base;
- unsigned long mmio_phys;
-- struct completion cmd_complete;
-+ struct completion cmd_complete, dev_ready;
-
- unsigned int buf_start;
- unsigned int buf_count;
-@@ -198,7 +199,7 @@ struct pxa3xx_nand_info {
- int use_ecc; /* use HW ECC ? */
- int use_dma; /* use DMA ? */
- int use_spare; /* use spare ? */
-- int is_ready;
-+ int need_wait;
-
- unsigned int fifo_size; /* max. data size in the FIFO */
- unsigned int data_size; /* data to be read from FIFO */
-@@ -480,7 +481,7 @@ static void start_data_dma(struct pxa3xx
- static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
- {
- struct pxa3xx_nand_info *info = devid;
-- unsigned int status, is_completed = 0;
-+ unsigned int status, is_completed = 0, is_ready = 0;
- unsigned int ready, cmd_done;
-
- if (info->cs == 0) {
-@@ -516,8 +517,8 @@ static irqreturn_t pxa3xx_nand_irq(int i
- is_completed = 1;
- }
- if (status & ready) {
-- info->is_ready = 1;
- info->state = STATE_READY;
-+ is_ready = 1;
- }
-
- if (status & NDSR_WRCMDREQ) {
-@@ -546,6 +547,8 @@ static irqreturn_t pxa3xx_nand_irq(int i
- nand_writel(info, NDSR, status);
- if (is_completed)
- complete(&info->cmd_complete);
-+ if (is_ready)
-+ complete(&info->dev_ready);
- NORMAL_IRQ_EXIT:
- return IRQ_HANDLED;
- }
-@@ -576,7 +579,6 @@ static int prepare_command_pool(struct p
- info->oob_size = 0;
- info->use_ecc = 0;
- info->use_spare = 1;
-- info->is_ready = 0;
- info->retcode = ERR_NONE;
- if (info->cs != 0)
- info->ndcb0 = NDCB0_CSEL;
-@@ -749,6 +751,8 @@ static void pxa3xx_nand_cmdfunc(struct m
- exec_cmd = prepare_command_pool(info, command, column, page_addr);
- if (exec_cmd) {
- init_completion(&info->cmd_complete);
-+ init_completion(&info->dev_ready);
-+ info->need_wait = 1;
- pxa3xx_nand_start(info);
-
- ret = wait_for_completion_timeout(&info->cmd_complete,
-@@ -863,21 +867,27 @@ static int pxa3xx_nand_waitfunc(struct m
- {
- struct pxa3xx_nand_host *host = mtd->priv;
- struct pxa3xx_nand_info *info = host->info_data;
-+ int ret;
-+
-+ if (info->need_wait) {
-+ ret = wait_for_completion_timeout(&info->dev_ready,
-+ CHIP_DELAY_TIMEOUT);
-+ info->need_wait = 0;
-+ if (!ret) {
-+ dev_err(&info->pdev->dev, "Ready time out!!!\n");
-+ return NAND_STATUS_FAIL;
-+ }
-+ }
-
- /* pxa3xx_nand_send_command has waited for command complete */
- if (this->state == FL_WRITING || this->state == FL_ERASING) {
- if (info->retcode == ERR_NONE)
- return 0;
-- else {
-- /*
-- * any error make it return 0x01 which will tell
-- * the caller the erase and write fail
-- */
-- return 0x01;
-- }
-+ else
-+ return NAND_STATUS_FAIL;
- }
-
-- return 0;
-+ return NAND_STATUS_READY;
- }
-
- static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
-@@ -1030,7 +1040,7 @@ static int pxa3xx_nand_sensing(struct px
- return ret;
-
- chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
-- if (info->is_ready)
-+ if (!info->need_wait)
- return 0;
-
- return -ENODEV;
+++ /dev/null
-From 2a1254f505ca4d376eae81768e4d5d890b578d13 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:27 -0300
-Subject: [PATCH 141/203] mtd: nand: pxa3xx: Use waitfunc() to wait for the
- device to be ready
-
-In pxa3xx_nand_sensing() instead of simply using info->is_ready
-after issuing a command, the correct way of checking is to wait
-for the device to be ready through the chip's waitfunc().
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1040,10 +1040,11 @@ static int pxa3xx_nand_sensing(struct px
- return ret;
-
- chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
-- if (!info->need_wait)
-- return 0;
-+ ret = chip->waitfunc(mtd, chip);
-+ if (ret & NAND_STATUS_FAIL)
-+ return -ENODEV;
-
-- return -ENODEV;
-+ return 0;
- }
-
- static int pxa3xx_nand_scan(struct mtd_info *mtd)
+++ /dev/null
-From bd428b9b18c2dffb8c9d737e99adfd145822e502 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:28 -0300
-Subject: [PATCH 142/203] mtd: nand: pxa3xx: Add bad block handling
-
-Add support for flash-based bad block table using Marvell's
-custom in-flash bad block table layout. The support is enabled
-a 'flash_bbt' platform data or device tree parameter.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- .../devicetree/bindings/mtd/pxa3xx-nand.txt | 2 ++
- drivers/mtd/nand/pxa3xx_nand.c | 37 ++++++++++++++++++++++
- include/linux/platform_data/mtd-nand-pxa3xx.h | 3 ++
- 3 files changed, 42 insertions(+)
-
---- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
-+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
-@@ -13,6 +13,8 @@ Optional properties:
- - marvell,nand-keep-config: Set to keep the NAND controller config as set
- by the bootloader
- - num-cs: Number of chipselect lines to usw
-+ - nand-on-flash-bbt: boolean to enable on flash bbt option if
-+ not present false
-
- Example:
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -26,6 +26,7 @@
- #include <linux/slab.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
-+#include <linux/of_mtd.h>
-
- #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
- #define ARCH_HAS_DMA
-@@ -241,6 +242,29 @@ static struct pxa3xx_nand_flash builtin_
- { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
- };
-
-+static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
-+static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
-+
-+static struct nand_bbt_descr bbt_main_descr = {
-+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
-+ | NAND_BBT_2BIT | NAND_BBT_VERSION,
-+ .offs = 8,
-+ .len = 6,
-+ .veroffs = 14,
-+ .maxblocks = 8, /* Last 8 blocks in each chip */
-+ .pattern = bbt_pattern
-+};
-+
-+static struct nand_bbt_descr bbt_mirror_descr = {
-+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
-+ | NAND_BBT_2BIT | NAND_BBT_VERSION,
-+ .offs = 8,
-+ .len = 6,
-+ .veroffs = 14,
-+ .maxblocks = 8, /* Last 8 blocks in each chip */
-+ .pattern = bbt_mirror_pattern
-+};
-+
- /* Define a default flash type setting serve as flash detecting only */
- #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
-
-@@ -1126,6 +1150,18 @@ KEEP_CONFIG:
-
- if (nand_scan_ident(mtd, 1, def))
- return -ENODEV;
-+
-+ if (pdata->flash_bbt) {
-+ /*
-+ * We'll use a bad block table stored in-flash and don't
-+ * allow writing the bad block marker to the flash.
-+ */
-+ chip->bbt_options |= NAND_BBT_USE_FLASH |
-+ NAND_BBT_NO_OOB_BBM;
-+ chip->bbt_td = &bbt_main_descr;
-+ chip->bbt_md = &bbt_mirror_descr;
-+ }
-+
- /* calculate addressing information */
- if (mtd->writesize >= 2048)
- host->col_addr_cycles = 2;
-@@ -1320,6 +1356,7 @@ static int pxa3xx_nand_probe_dt(struct p
- if (of_get_property(np, "marvell,nand-keep-config", NULL))
- pdata->keep_config = 1;
- of_property_read_u32(np, "num-cs", &pdata->num_cs);
-+ pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
-
- pdev->dev.platform_data = pdata;
-
---- a/include/linux/platform_data/mtd-nand-pxa3xx.h
-+++ b/include/linux/platform_data/mtd-nand-pxa3xx.h
-@@ -55,6 +55,9 @@ struct pxa3xx_nand_platform_data {
- /* indicate how many chip selects will be used */
- int num_cs;
-
-+ /* use an flash-based bad block table */
-+ bool flash_bbt;
-+
- const struct mtd_partition *parts[NUM_CHIP_SELECT];
- unsigned int nr_parts[NUM_CHIP_SELECT];
-
+++ /dev/null
-From 3677d22ed7e3a631f35e2addc4e2181f6215e4b0 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:29 -0300
-Subject: [PATCH 143/203] mtd: nand: pxa3xx: Add driver-specific ECC BCH
- support
-
-This commit adds the BCH ECC support available in NFCv2 controller.
-Depending on the detected required strength the respective ECC layout
-is selected.
-
-This commit adds an empty ECC layout, since support to access large
-pages is first required. Once that support is added, a proper ECC
-layout will be added as well.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 86 +++++++++++++++++++++++++++++++++---------
- 1 file changed, 69 insertions(+), 17 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -58,6 +58,7 @@
- #define NDPCR (0x18) /* Page Count Register */
- #define NDBDR0 (0x1C) /* Bad Block Register 0 */
- #define NDBDR1 (0x20) /* Bad Block Register 1 */
-+#define NDECCCTRL (0x28) /* ECC control */
- #define NDDB (0x40) /* Data Buffer */
- #define NDCB0 (0x48) /* Command Buffer0 */
- #define NDCB1 (0x4C) /* Command Buffer1 */
-@@ -198,6 +199,7 @@ struct pxa3xx_nand_info {
-
- int cs;
- int use_ecc; /* use HW ECC ? */
-+ int ecc_bch; /* using BCH ECC? */
- int use_dma; /* use DMA ? */
- int use_spare; /* use spare ? */
- int need_wait;
-@@ -205,6 +207,8 @@ struct pxa3xx_nand_info {
- unsigned int fifo_size; /* max. data size in the FIFO */
- unsigned int data_size; /* data to be read from FIFO */
- unsigned int oob_size;
-+ unsigned int spare_size;
-+ unsigned int ecc_size;
- int retcode;
-
- /* cached register value */
-@@ -339,19 +343,12 @@ static void pxa3xx_set_datasize(struct p
- int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
-
- info->data_size = info->fifo_size;
-- if (!oob_enable) {
-- info->oob_size = 0;
-+ if (!oob_enable)
- return;
-- }
-
-- switch (info->fifo_size) {
-- case 2048:
-- info->oob_size = (info->use_ecc) ? 40 : 64;
-- break;
-- case 512:
-- info->oob_size = (info->use_ecc) ? 8 : 16;
-- break;
-- }
-+ info->oob_size = info->spare_size;
-+ if (!info->use_ecc)
-+ info->oob_size += info->ecc_size;
- }
-
- /**
-@@ -366,10 +363,15 @@ static void pxa3xx_nand_start(struct pxa
-
- ndcr = info->reg_ndcr;
-
-- if (info->use_ecc)
-+ if (info->use_ecc) {
- ndcr |= NDCR_ECC_EN;
-- else
-+ if (info->ecc_bch)
-+ nand_writel(info, NDECCCTRL, 0x1);
-+ } else {
- ndcr &= ~NDCR_ECC_EN;
-+ if (info->ecc_bch)
-+ nand_writel(info, NDECCCTRL, 0x0);
-+ }
-
- if (info->use_dma)
- ndcr |= NDCR_DMA_EN;
-@@ -1071,6 +1073,41 @@ static int pxa3xx_nand_sensing(struct px
- return 0;
- }
-
-+static int pxa_ecc_init(struct pxa3xx_nand_info *info,
-+ struct nand_ecc_ctrl *ecc,
-+ int strength, int page_size)
-+{
-+ /*
-+ * We don't use strength here as the PXA variant
-+ * is used with non-ONFI compliant devices.
-+ */
-+ if (page_size == 2048) {
-+ info->spare_size = 40;
-+ info->ecc_size = 24;
-+ ecc->mode = NAND_ECC_HW;
-+ ecc->size = 512;
-+ ecc->strength = 1;
-+ return 1;
-+
-+ } else if (page_size == 512) {
-+ info->spare_size = 8;
-+ info->ecc_size = 8;
-+ ecc->mode = NAND_ECC_HW;
-+ ecc->size = 512;
-+ ecc->strength = 1;
-+ return 1;
-+ }
-+ return 0;
-+}
-+
-+static int armada370_ecc_init(struct pxa3xx_nand_info *info,
-+ struct nand_ecc_ctrl *ecc,
-+ int strength, int page_size)
-+{
-+ /* Unimplemented yet */
-+ return 0;
-+}
-+
- static int pxa3xx_nand_scan(struct mtd_info *mtd)
- {
- struct pxa3xx_nand_host *host = mtd->priv;
-@@ -1141,13 +1178,13 @@ static int pxa3xx_nand_scan(struct mtd_i
- pxa3xx_flash_ids[1].name = NULL;
- def = pxa3xx_flash_ids;
- KEEP_CONFIG:
-- chip->ecc.mode = NAND_ECC_HW;
-- chip->ecc.size = info->fifo_size;
-- chip->ecc.strength = 1;
--
- if (info->reg_ndcr & NDCR_DWIDTH_M)
- chip->options |= NAND_BUSWIDTH_16;
-
-+ /* Device detection must be done with ECC disabled */
-+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
-+ nand_writel(info, NDECCCTRL, 0x0);
-+
- if (nand_scan_ident(mtd, 1, def))
- return -ENODEV;
-
-@@ -1162,6 +1199,21 @@ KEEP_CONFIG:
- chip->bbt_md = &bbt_mirror_descr;
- }
-
-+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
-+ ret = armada370_ecc_init(info, &chip->ecc,
-+ chip->ecc_strength_ds,
-+ mtd->writesize);
-+ else
-+ ret = pxa_ecc_init(info, &chip->ecc,
-+ chip->ecc_strength_ds,
-+ mtd->writesize);
-+ if (!ret) {
-+ dev_err(&info->pdev->dev,
-+ "ECC strength %d at page size %d is not supported\n",
-+ chip->ecc_strength_ds, mtd->writesize);
-+ return -ENODEV;
-+ }
-+
- /* calculate addressing information */
- if (mtd->writesize >= 2048)
- host->col_addr_cycles = 2;
+++ /dev/null
-From cb574fecefd9552e5c6c5105adab7b37b0feb712 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:30 -0300
-Subject: [PATCH 144/203] mtd: nand: pxa3xx: Clear cmd buffer #3 (NDCB3) on
- command start
-
-Command buffer #3 is not properly cleared and it keeps the last
-set value. Fix this by clearing when a command is setup.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -606,6 +606,7 @@ static int prepare_command_pool(struct p
- info->use_ecc = 0;
- info->use_spare = 1;
- info->retcode = ERR_NONE;
-+ info->ndcb3 = 0;
- if (info->cs != 0)
- info->ndcb0 = NDCB0_CSEL;
- else
-@@ -627,7 +628,6 @@ static int prepare_command_pool(struct p
- default:
- info->ndcb1 = 0;
- info->ndcb2 = 0;
-- info->ndcb3 = 0;
- break;
- }
-
+++ /dev/null
-From 09a84f8e89c3715160423701b0606ef99e2a05bf Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:31 -0300
-Subject: [PATCH 145/203] mtd: nand: pxa3xx: Add helper function to set page
- address
-
-Let's simplify the code by first introducing a helper function
-to set the page address, as done by the READ0, READOOB and SEQIN
-commands.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 36 +++++++++++++++++++++---------------
- 1 file changed, 21 insertions(+), 15 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -587,6 +587,26 @@ static inline int is_buf_blank(uint8_t *
- return 1;
- }
-
-+static void set_command_address(struct pxa3xx_nand_info *info,
-+ unsigned int page_size, uint16_t column, int page_addr)
-+{
-+ /* small page addr setting */
-+ if (page_size < PAGE_CHUNK_SIZE) {
-+ info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
-+ | (column & 0xFF);
-+
-+ info->ndcb2 = 0;
-+ } else {
-+ info->ndcb1 = ((page_addr & 0xFFFF) << 16)
-+ | (column & 0xFFFF);
-+
-+ if (page_addr & 0xFF0000)
-+ info->ndcb2 = (page_addr & 0xFF0000) >> 16;
-+ else
-+ info->ndcb2 = 0;
-+ }
-+}
-+
- static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
- uint16_t column, int page_addr)
- {
-@@ -650,22 +670,8 @@ static int prepare_command_pool(struct p
- info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
-
- case NAND_CMD_SEQIN:
-- /* small page addr setting */
-- if (unlikely(mtd->writesize < PAGE_CHUNK_SIZE)) {
-- info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
-- | (column & 0xFF);
--
-- info->ndcb2 = 0;
-- } else {
-- info->ndcb1 = ((page_addr & 0xFFFF) << 16)
-- | (column & 0xFFFF);
--
-- if (page_addr & 0xFF0000)
-- info->ndcb2 = (page_addr & 0xFF0000) >> 16;
-- else
-- info->ndcb2 = 0;
-- }
-
-+ set_command_address(info, mtd->writesize, column, page_addr);
- info->buf_count = mtd->writesize + mtd->oobsize;
- memset(info->data_buff, 0xFF, info->buf_count);
-
+++ /dev/null
-From 11532c10a29e4faef29b5f3b354391d1e2f90213 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:32 -0300
-Subject: [PATCH 146/203] mtd: nand: pxa3xx: Remove READ0 switch/case
- falltrough
-
-READ0 and READOOB command preparation has a falltrough to SEQIN
-case, where the command address is specified.
-This is certainly confusing and makes the code less readable with
-no added value. Let's remove it.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -669,6 +669,11 @@ static int prepare_command_pool(struct p
- if (mtd->writesize >= PAGE_CHUNK_SIZE)
- info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
-
-+ set_command_address(info, mtd->writesize, column, page_addr);
-+ info->buf_count = mtd->writesize + mtd->oobsize;
-+ memset(info->data_buff, 0xFF, info->buf_count);
-+ break;
-+
- case NAND_CMD_SEQIN:
-
- set_command_address(info, mtd->writesize, column, page_addr);
+++ /dev/null
-From 78c8c8dc7e27c4502504cb4daa07bc9762f54de9 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:33 -0300
-Subject: [PATCH 147/203] mtd: nand: pxa3xx: Split prepare_command_pool() in
- two stages
-
-This commit splits the prepare_command_pool() function into two
-stages: prepare_start_command() / prepare_set_command().
-
-This is a preparation patch without any functionality changes,
-and is meant to allow support for multiple page reading/writing
-operations.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 44 ++++++++++++++++++++++++------------------
- 1 file changed, 25 insertions(+), 19 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -607,18 +607,8 @@ static void set_command_address(struct p
- }
- }
-
--static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
-- uint16_t column, int page_addr)
-+static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
- {
-- int addr_cycle, exec_cmd;
-- struct pxa3xx_nand_host *host;
-- struct mtd_info *mtd;
--
-- host = info->host[info->cs];
-- mtd = host->mtd;
-- addr_cycle = 0;
-- exec_cmd = 1;
--
- /* reset data and oob column point to handle data */
- info->buf_start = 0;
- info->buf_count = 0;
-@@ -627,10 +617,6 @@ static int prepare_command_pool(struct p
- info->use_spare = 1;
- info->retcode = ERR_NONE;
- info->ndcb3 = 0;
-- if (info->cs != 0)
-- info->ndcb0 = NDCB0_CSEL;
-- else
-- info->ndcb0 = 0;
-
- switch (command) {
- case NAND_CMD_READ0:
-@@ -642,14 +628,32 @@ static int prepare_command_pool(struct p
- case NAND_CMD_PARAM:
- info->use_spare = 0;
- break;
-- case NAND_CMD_SEQIN:
-- exec_cmd = 0;
-- break;
- default:
- info->ndcb1 = 0;
- info->ndcb2 = 0;
- break;
- }
-+}
-+
-+static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
-+ uint16_t column, int page_addr)
-+{
-+ int addr_cycle, exec_cmd;
-+ struct pxa3xx_nand_host *host;
-+ struct mtd_info *mtd;
-+
-+ host = info->host[info->cs];
-+ mtd = host->mtd;
-+ addr_cycle = 0;
-+ exec_cmd = 1;
-+
-+ if (info->cs != 0)
-+ info->ndcb0 = NDCB0_CSEL;
-+ else
-+ info->ndcb0 = 0;
-+
-+ if (command == NAND_CMD_SEQIN)
-+ exec_cmd = 0;
-
- addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
- + host->col_addr_cycles);
-@@ -784,8 +788,10 @@ static void pxa3xx_nand_cmdfunc(struct m
- nand_writel(info, NDTR1CS0, info->ndtr1cs0);
- }
-
-+ prepare_start_command(info, command);
-+
- info->state = STATE_PREPARED;
-- exec_cmd = prepare_command_pool(info, command, column, page_addr);
-+ exec_cmd = prepare_set_command(info, command, column, page_addr);
- if (exec_cmd) {
- init_completion(&info->cmd_complete);
- init_completion(&info->dev_ready);
+++ /dev/null
-From 1c0aed9b4cfb7bb891aab07a429436d017ac4d7c Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:34 -0300
-Subject: [PATCH 148/203] mtd: nand: pxa3xx: Move the data buffer clean to
- prepare_start_command()
-
-To allow future support of multiple page reading/writing, move the data
-buffer clean out of prepare_set_command().
-
-This is done to prevent the data buffer from being cleaned on every command
-preparation, when a multiple command sequence is implemented to read/write
-pages larger than the FIFO size (2 KiB).
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 21 ++++++++++++++++-----
- 1 file changed, 16 insertions(+), 5 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -609,6 +609,9 @@ static void set_command_address(struct p
-
- static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
- {
-+ struct pxa3xx_nand_host *host = info->host[info->cs];
-+ struct mtd_info *mtd = host->mtd;
-+
- /* reset data and oob column point to handle data */
- info->buf_start = 0;
- info->buf_count = 0;
-@@ -633,6 +636,19 @@ static void prepare_start_command(struct
- info->ndcb2 = 0;
- break;
- }
-+
-+ /*
-+ * If we are about to issue a read command, or about to set
-+ * the write address, then clean the data buffer.
-+ */
-+ if (command == NAND_CMD_READ0 ||
-+ command == NAND_CMD_READOOB ||
-+ command == NAND_CMD_SEQIN) {
-+
-+ info->buf_count = mtd->writesize + mtd->oobsize;
-+ memset(info->data_buff, 0xFF, info->buf_count);
-+ }
-+
- }
-
- static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
-@@ -674,16 +690,11 @@ static int prepare_set_command(struct px
- info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
-
- set_command_address(info, mtd->writesize, column, page_addr);
-- info->buf_count = mtd->writesize + mtd->oobsize;
-- memset(info->data_buff, 0xFF, info->buf_count);
- break;
-
- case NAND_CMD_SEQIN:
-
- set_command_address(info, mtd->writesize, column, page_addr);
-- info->buf_count = mtd->writesize + mtd->oobsize;
-- memset(info->data_buff, 0xFF, info->buf_count);
--
- break;
-
- case NAND_CMD_PAGEPROG:
+++ /dev/null
-From d5c9b013c71a570737353270f94b9a52639fcea1 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:35 -0300
-Subject: [PATCH 149/203] mtd: nand: pxa3xx: Fix SEQIN column address set
-
-This commit adds support page programming with a non-zero "column"
-address setting. This is important to support OOB writing, through
-command sequences such as:
-
- cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, ofs);
- write_buf(mtd, oob_buf, 6);
- cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -694,7 +694,8 @@ static int prepare_set_command(struct px
-
- case NAND_CMD_SEQIN:
-
-- set_command_address(info, mtd->writesize, column, page_addr);
-+ info->buf_start = column;
-+ set_command_address(info, mtd->writesize, 0, page_addr);
- break;
-
- case NAND_CMD_PAGEPROG:
+++ /dev/null
-From 6e3022aeb5d221af838ad43a2163374aecacf929 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:36 -0300
-Subject: [PATCH 150/203] mtd: nand: pxa3xx: Add a read/write buffers markers
-
-In preparation to support multiple (aka chunked, aka splitted)
-page I/O, this commit adds 'data_buff_pos' and 'oob_buff_pos' fields
-to keep track of where the next read (or write) should be done.
-
-This will allow multiple calls to handle_data_pio() to continue
-the read (or write) operation.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 40 +++++++++++++++++++++++++++++-----------
- 1 file changed, 29 insertions(+), 11 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -176,6 +176,8 @@ struct pxa3xx_nand_info {
- unsigned int buf_start;
- unsigned int buf_count;
- unsigned int buf_size;
-+ unsigned int data_buff_pos;
-+ unsigned int oob_buff_pos;
-
- /* DMA information */
- int drcmr_dat;
-@@ -338,11 +340,12 @@ static void pxa3xx_nand_set_timing(struc
- * spare and ECC configuration.
- * Only applicable to READ0, READOOB and PAGEPROG commands.
- */
--static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
-+static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info,
-+ struct mtd_info *mtd)
- {
- int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
-
-- info->data_size = info->fifo_size;
-+ info->data_size = mtd->writesize;
- if (!oob_enable)
- return;
-
-@@ -430,26 +433,39 @@ static void disable_int(struct pxa3xx_na
-
- static void handle_data_pio(struct pxa3xx_nand_info *info)
- {
-+ unsigned int do_bytes = min(info->data_size, info->fifo_size);
-+
- switch (info->state) {
- case STATE_PIO_WRITING:
-- __raw_writesl(info->mmio_base + NDDB, info->data_buff,
-- DIV_ROUND_UP(info->data_size, 4));
-+ __raw_writesl(info->mmio_base + NDDB,
-+ info->data_buff + info->data_buff_pos,
-+ DIV_ROUND_UP(do_bytes, 4));
-+
- if (info->oob_size > 0)
-- __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
-- DIV_ROUND_UP(info->oob_size, 4));
-+ __raw_writesl(info->mmio_base + NDDB,
-+ info->oob_buff + info->oob_buff_pos,
-+ DIV_ROUND_UP(info->oob_size, 4));
- break;
- case STATE_PIO_READING:
-- __raw_readsl(info->mmio_base + NDDB, info->data_buff,
-- DIV_ROUND_UP(info->data_size, 4));
-+ __raw_readsl(info->mmio_base + NDDB,
-+ info->data_buff + info->data_buff_pos,
-+ DIV_ROUND_UP(do_bytes, 4));
-+
- if (info->oob_size > 0)
-- __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
-- DIV_ROUND_UP(info->oob_size, 4));
-+ __raw_readsl(info->mmio_base + NDDB,
-+ info->oob_buff + info->oob_buff_pos,
-+ DIV_ROUND_UP(info->oob_size, 4));
- break;
- default:
- dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
- info->state);
- BUG();
- }
-+
-+ /* Update buffer pointers for multi-page read/write */
-+ info->data_buff_pos += do_bytes;
-+ info->oob_buff_pos += info->oob_size;
-+ info->data_size -= do_bytes;
- }
-
- #ifdef ARCH_HAS_DMA
-@@ -616,6 +632,8 @@ static void prepare_start_command(struct
- info->buf_start = 0;
- info->buf_count = 0;
- info->oob_size = 0;
-+ info->data_buff_pos = 0;
-+ info->oob_buff_pos = 0;
- info->use_ecc = 0;
- info->use_spare = 1;
- info->retcode = ERR_NONE;
-@@ -626,7 +644,7 @@ static void prepare_start_command(struct
- case NAND_CMD_PAGEPROG:
- info->use_ecc = 1;
- case NAND_CMD_READOOB:
-- pxa3xx_set_datasize(info);
-+ pxa3xx_set_datasize(info, mtd);
- break;
- case NAND_CMD_PARAM:
- info->use_spare = 0;
+++ /dev/null
-From cfd1799f9ec5c9820f371e1fcf2f3c458bd24ebb Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:37 -0300
-Subject: [PATCH 151/203] mtd: nand: pxa3xx: Introduce multiple page I/O
- support
-
-As preparation work to fully support large pages, this commit adds
-the initial infrastructure to support splitted (aka chunked) I/O
-operation. This commit adds support for read, and follow-up patches
-will add write support.
-
-When a read (aka READ0) command is issued, the driver loops issuing
-the same command until all the requested data is transfered, changing
-the 'extended' command field as needed.
-
-For instance, if the driver is required to read a 4 KiB page, using a
-chunk size of 2 KiB, the transaction is splitted in:
-1. Monolithic read, first 2 KiB page chunk is read
-2. Last naked read, second and last 2KiB page chunk is read
-
-If ECC is enabled it is calculated on each chunk transfered and added
-at a controller-fixed location after the data chunk that must be
-spare area.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 182 ++++++++++++++++++++++++++++++++++++++---
- 1 file changed, 172 insertions(+), 10 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -103,6 +103,8 @@
- #define NDCB0_ST_ROW_EN (0x1 << 26)
- #define NDCB0_AUTO_RS (0x1 << 25)
- #define NDCB0_CSEL (0x1 << 24)
-+#define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
-+#define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
- #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
- #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
- #define NDCB0_NC (0x1 << 20)
-@@ -113,6 +115,14 @@
- #define NDCB0_CMD1_MASK (0xff)
- #define NDCB0_ADDR_CYC_SHIFT (16)
-
-+#define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
-+#define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
-+#define EXT_CMD_TYPE_READ 4 /* Read */
-+#define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
-+#define EXT_CMD_TYPE_FINAL 3 /* Final command */
-+#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
-+#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
-+
- /* macros for registers read/write */
- #define nand_writel(info, off, val) \
- __raw_writel((val), (info)->mmio_base + (off))
-@@ -206,8 +216,8 @@ struct pxa3xx_nand_info {
- int use_spare; /* use spare ? */
- int need_wait;
-
-- unsigned int fifo_size; /* max. data size in the FIFO */
- unsigned int data_size; /* data to be read from FIFO */
-+ unsigned int chunk_size; /* split commands chunk size */
- unsigned int oob_size;
- unsigned int spare_size;
- unsigned int ecc_size;
-@@ -271,6 +281,31 @@ static struct nand_bbt_descr bbt_mirror_
- .pattern = bbt_mirror_pattern
- };
-
-+static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
-+ .eccbytes = 64,
-+ .eccpos = {
-+ 32, 33, 34, 35, 36, 37, 38, 39,
-+ 40, 41, 42, 43, 44, 45, 46, 47,
-+ 48, 49, 50, 51, 52, 53, 54, 55,
-+ 56, 57, 58, 59, 60, 61, 62, 63,
-+ 96, 97, 98, 99, 100, 101, 102, 103,
-+ 104, 105, 106, 107, 108, 109, 110, 111,
-+ 112, 113, 114, 115, 116, 117, 118, 119,
-+ 120, 121, 122, 123, 124, 125, 126, 127},
-+ /* Bootrom looks in bytes 0 & 5 for bad blocks */
-+ .oobfree = { {6, 26}, { 64, 32} }
-+};
-+
-+static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
-+ .eccbytes = 128,
-+ .eccpos = {
-+ 32, 33, 34, 35, 36, 37, 38, 39,
-+ 40, 41, 42, 43, 44, 45, 46, 47,
-+ 48, 49, 50, 51, 52, 53, 54, 55,
-+ 56, 57, 58, 59, 60, 61, 62, 63},
-+ .oobfree = { }
-+};
-+
- /* Define a default flash type setting serve as flash detecting only */
- #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
-
-@@ -433,7 +468,7 @@ static void disable_int(struct pxa3xx_na
-
- static void handle_data_pio(struct pxa3xx_nand_info *info)
- {
-- unsigned int do_bytes = min(info->data_size, info->fifo_size);
-+ unsigned int do_bytes = min(info->data_size, info->chunk_size);
-
- switch (info->state) {
- case STATE_PIO_WRITING:
-@@ -670,7 +705,7 @@ static void prepare_start_command(struct
- }
-
- static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
-- uint16_t column, int page_addr)
-+ int ext_cmd_type, uint16_t column, int page_addr)
- {
- int addr_cycle, exec_cmd;
- struct pxa3xx_nand_host *host;
-@@ -703,9 +738,20 @@ static int prepare_set_command(struct px
- if (command == NAND_CMD_READOOB)
- info->buf_start += mtd->writesize;
-
-- /* Second command setting for large pages */
-- if (mtd->writesize >= PAGE_CHUNK_SIZE)
-+ /*
-+ * Multiple page read needs an 'extended command type' field,
-+ * which is either naked-read or last-read according to the
-+ * state.
-+ */
-+ if (mtd->writesize == PAGE_CHUNK_SIZE) {
- info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
-+ } else if (mtd->writesize > PAGE_CHUNK_SIZE) {
-+ info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
-+ | NDCB0_LEN_OVRD
-+ | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
-+ info->ndcb3 = info->chunk_size +
-+ info->oob_size;
-+ }
-
- set_command_address(info, mtd->writesize, column, page_addr);
- break;
-@@ -821,7 +867,8 @@ static void pxa3xx_nand_cmdfunc(struct m
- prepare_start_command(info, command);
-
- info->state = STATE_PREPARED;
-- exec_cmd = prepare_set_command(info, command, column, page_addr);
-+ exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
-+
- if (exec_cmd) {
- init_completion(&info->cmd_complete);
- init_completion(&info->dev_ready);
-@@ -839,6 +886,93 @@ static void pxa3xx_nand_cmdfunc(struct m
- info->state = STATE_IDLE;
- }
-
-+static void armada370_nand_cmdfunc(struct mtd_info *mtd,
-+ const unsigned command,
-+ int column, int page_addr)
-+{
-+ struct pxa3xx_nand_host *host = mtd->priv;
-+ struct pxa3xx_nand_info *info = host->info_data;
-+ int ret, exec_cmd, ext_cmd_type;
-+
-+ /*
-+ * if this is a x16 device then convert the input
-+ * "byte" address into a "word" address appropriate
-+ * for indexing a word-oriented device
-+ */
-+ if (info->reg_ndcr & NDCR_DWIDTH_M)
-+ column /= 2;
-+
-+ /*
-+ * There may be different NAND chip hooked to
-+ * different chip select, so check whether
-+ * chip select has been changed, if yes, reset the timing
-+ */
-+ if (info->cs != host->cs) {
-+ info->cs = host->cs;
-+ nand_writel(info, NDTR0CS0, info->ndtr0cs0);
-+ nand_writel(info, NDTR1CS0, info->ndtr1cs0);
-+ }
-+
-+ /* Select the extended command for the first command */
-+ switch (command) {
-+ case NAND_CMD_READ0:
-+ case NAND_CMD_READOOB:
-+ ext_cmd_type = EXT_CMD_TYPE_MONO;
-+ break;
-+ default:
-+ ext_cmd_type = 0;
-+ }
-+
-+ prepare_start_command(info, command);
-+
-+ /*
-+ * Prepare the "is ready" completion before starting a command
-+ * transaction sequence. If the command is not executed the
-+ * completion will be completed, see below.
-+ *
-+ * We can do that inside the loop because the command variable
-+ * is invariant and thus so is the exec_cmd.
-+ */
-+ info->need_wait = 1;
-+ init_completion(&info->dev_ready);
-+ do {
-+ info->state = STATE_PREPARED;
-+ exec_cmd = prepare_set_command(info, command, ext_cmd_type,
-+ column, page_addr);
-+ if (!exec_cmd) {
-+ info->need_wait = 0;
-+ complete(&info->dev_ready);
-+ break;
-+ }
-+
-+ init_completion(&info->cmd_complete);
-+ pxa3xx_nand_start(info);
-+
-+ ret = wait_for_completion_timeout(&info->cmd_complete,
-+ CHIP_DELAY_TIMEOUT);
-+ if (!ret) {
-+ dev_err(&info->pdev->dev, "Wait time out!!!\n");
-+ /* Stop State Machine for next command cycle */
-+ pxa3xx_nand_stop(info);
-+ break;
-+ }
-+
-+ /* Check if the sequence is complete */
-+ if (info->data_size == 0)
-+ break;
-+
-+ if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
-+ /* Last read: issue a 'last naked read' */
-+ if (info->data_size == info->chunk_size)
-+ ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
-+ else
-+ ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
-+ }
-+ } while (1);
-+
-+ info->state = STATE_IDLE;
-+}
-+
- static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required)
- {
-@@ -1019,13 +1153,14 @@ static int pxa3xx_nand_detect_config(str
-
- if (ndcr & NDCR_PAGE_SZ) {
- /* Controller's FIFO size */
-- info->fifo_size = 2048;
-+ info->chunk_size = 2048;
- host->read_id_bytes = 4;
- } else {
-- info->fifo_size = 512;
-+ info->chunk_size = 512;
- host->read_id_bytes = 2;
- }
-
-+ /* Set an initial chunk size */
- info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
- info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
- info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
-@@ -1129,6 +1264,7 @@ static int pxa_ecc_init(struct pxa3xx_na
- * is used with non-ONFI compliant devices.
- */
- if (page_size == 2048) {
-+ info->chunk_size = 2048;
- info->spare_size = 40;
- info->ecc_size = 24;
- ecc->mode = NAND_ECC_HW;
-@@ -1137,6 +1273,7 @@ static int pxa_ecc_init(struct pxa3xx_na
- return 1;
-
- } else if (page_size == 512) {
-+ info->chunk_size = 512;
- info->spare_size = 8;
- info->ecc_size = 8;
- ecc->mode = NAND_ECC_HW;
-@@ -1151,7 +1288,28 @@ static int armada370_ecc_init(struct pxa
- struct nand_ecc_ctrl *ecc,
- int strength, int page_size)
- {
-- /* Unimplemented yet */
-+ if (strength == 4 && page_size == 4096) {
-+ info->ecc_bch = 1;
-+ info->chunk_size = 2048;
-+ info->spare_size = 32;
-+ info->ecc_size = 32;
-+ ecc->mode = NAND_ECC_HW;
-+ ecc->size = info->chunk_size;
-+ ecc->layout = &ecc_layout_4KB_bch4bit;
-+ ecc->strength = 16;
-+ return 1;
-+
-+ } else if (strength == 8 && page_size == 4096) {
-+ info->ecc_bch = 1;
-+ info->chunk_size = 1024;
-+ info->spare_size = 0;
-+ info->ecc_size = 32;
-+ ecc->mode = NAND_ECC_HW;
-+ ecc->size = info->chunk_size;
-+ ecc->layout = &ecc_layout_4KB_bch8bit;
-+ ecc->strength = 16;
-+ return 1;
-+ }
- return 0;
- }
-
-@@ -1319,12 +1477,16 @@ static int alloc_nand_resource(struct pl
- chip->controller = &info->controller;
- chip->waitfunc = pxa3xx_nand_waitfunc;
- chip->select_chip = pxa3xx_nand_select_chip;
-- chip->cmdfunc = pxa3xx_nand_cmdfunc;
- chip->read_word = pxa3xx_nand_read_word;
- chip->read_byte = pxa3xx_nand_read_byte;
- chip->read_buf = pxa3xx_nand_read_buf;
- chip->write_buf = pxa3xx_nand_write_buf;
- chip->options |= NAND_NO_SUBPAGE_WRITE;
-+
-+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
-+ chip->cmdfunc = armada370_nand_cmdfunc;
-+ else
-+ chip->cmdfunc = pxa3xx_nand_cmdfunc;
- }
-
- spin_lock_init(&chip->controller->lock);
+++ /dev/null
-From db95c66cebb6297595a5a32b369d1033b08775ce Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:38 -0300
-Subject: [PATCH 152/203] mtd: nand: pxa3xx: Add multiple chunk write support
-
-This commit adds write support for large pages (4 KiB, 8 KiB).
-Such support is implemented by issuing a multiple command sequence,
-transfering a set of 2 KiB chunks per transaction.
-
-The splitted command sequence requires to send the SEQIN command
-independently of the PAGEPROG command and therefore it's set as
-an execution command.
-
-Since PAGEPROG enables ECC, each 2 KiB chunk of data is written
-together with ECC code at a controller-fixed location within
-the flash page.
-
-Currently, only devices with a 4 KiB page size has been tested.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 81 +++++++++++++++++++++++++++++++++++++-----
- 1 file changed, 73 insertions(+), 8 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -760,6 +760,20 @@ static int prepare_set_command(struct px
-
- info->buf_start = column;
- set_command_address(info, mtd->writesize, 0, page_addr);
-+
-+ /*
-+ * Multiple page programming needs to execute the initial
-+ * SEQIN command that sets the page address.
-+ */
-+ if (mtd->writesize > PAGE_CHUNK_SIZE) {
-+ info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
-+ | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
-+ | addr_cycle
-+ | command;
-+ /* No data transfer in this case */
-+ info->data_size = 0;
-+ exec_cmd = 1;
-+ }
- break;
-
- case NAND_CMD_PAGEPROG:
-@@ -769,13 +783,40 @@ static int prepare_set_command(struct px
- break;
- }
-
-- info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
-- | NDCB0_AUTO_RS
-- | NDCB0_ST_ROW_EN
-- | NDCB0_DBC
-- | (NAND_CMD_PAGEPROG << 8)
-- | NAND_CMD_SEQIN
-- | addr_cycle;
-+ /* Second command setting for large pages */
-+ if (mtd->writesize > PAGE_CHUNK_SIZE) {
-+ /*
-+ * Multiple page write uses the 'extended command'
-+ * field. This can be used to issue a command dispatch
-+ * or a naked-write depending on the current stage.
-+ */
-+ info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
-+ | NDCB0_LEN_OVRD
-+ | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
-+ info->ndcb3 = info->chunk_size +
-+ info->oob_size;
-+
-+ /*
-+ * This is the command dispatch that completes a chunked
-+ * page program operation.
-+ */
-+ if (info->data_size == 0) {
-+ info->ndcb0 = NDCB0_CMD_TYPE(0x1)
-+ | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
-+ | command;
-+ info->ndcb1 = 0;
-+ info->ndcb2 = 0;
-+ info->ndcb3 = 0;
-+ }
-+ } else {
-+ info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
-+ | NDCB0_AUTO_RS
-+ | NDCB0_ST_ROW_EN
-+ | NDCB0_DBC
-+ | (NAND_CMD_PAGEPROG << 8)
-+ | NAND_CMD_SEQIN
-+ | addr_cycle;
-+ }
- break;
-
- case NAND_CMD_PARAM:
-@@ -919,8 +960,15 @@ static void armada370_nand_cmdfunc(struc
- case NAND_CMD_READOOB:
- ext_cmd_type = EXT_CMD_TYPE_MONO;
- break;
-+ case NAND_CMD_SEQIN:
-+ ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
-+ break;
-+ case NAND_CMD_PAGEPROG:
-+ ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
-+ break;
- default:
- ext_cmd_type = 0;
-+ break;
- }
-
- prepare_start_command(info, command);
-@@ -958,7 +1006,16 @@ static void armada370_nand_cmdfunc(struc
- }
-
- /* Check if the sequence is complete */
-- if (info->data_size == 0)
-+ if (info->data_size == 0 && command != NAND_CMD_PAGEPROG)
-+ break;
-+
-+ /*
-+ * After a splitted program command sequence has issued
-+ * the command dispatch, the command sequence is complete.
-+ */
-+ if (info->data_size == 0 &&
-+ command == NAND_CMD_PAGEPROG &&
-+ ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
- break;
-
- if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
-@@ -967,6 +1024,14 @@ static void armada370_nand_cmdfunc(struc
- ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
- else
- ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
-+
-+ /*
-+ * If a splitted program command has no more data to transfer,
-+ * the command dispatch must be issued to complete.
-+ */
-+ } else if (command == NAND_CMD_PAGEPROG &&
-+ info->data_size == 0) {
-+ ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
- }
- } while (1);
-
+++ /dev/null
-From 26d82e0081aa6f0c7db5e4bb5b154b7c528cb8d6 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 14 Nov 2013 18:25:39 -0300
-Subject: [PATCH 153/203] mtd: nand: pxa3xx: Add ECC BCH correctable errors
- detection
-
-This commit extends the ECC correctable error detection to include
-ECC BCH errors. The number of BCH correctable errors can be any up to 16,
-and the actual value is exposed in the NDSR register.
-
-Therefore, we change some symbol names to refer to correctable or
-uncorrectable (instead of single-bit or double-bit as it was in the
-Hamming case) and while at it, cleanup the detection code slightly.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 57 ++++++++++++++++++++++++++----------------
- 1 file changed, 35 insertions(+), 22 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -85,6 +85,9 @@
- #define NDCR_INT_MASK (0xFFF)
-
- #define NDSR_MASK (0xfff)
-+#define NDSR_ERR_CNT_OFF (16)
-+#define NDSR_ERR_CNT_MASK (0x1f)
-+#define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
- #define NDSR_RDY (0x1 << 12)
- #define NDSR_FLASH_RDY (0x1 << 11)
- #define NDSR_CS0_PAGED (0x1 << 10)
-@@ -93,8 +96,8 @@
- #define NDSR_CS1_CMDD (0x1 << 7)
- #define NDSR_CS0_BBD (0x1 << 6)
- #define NDSR_CS1_BBD (0x1 << 5)
--#define NDSR_DBERR (0x1 << 4)
--#define NDSR_SBERR (0x1 << 3)
-+#define NDSR_UNCORERR (0x1 << 4)
-+#define NDSR_CORERR (0x1 << 3)
- #define NDSR_WRDREQ (0x1 << 2)
- #define NDSR_RDDREQ (0x1 << 1)
- #define NDSR_WRCMDREQ (0x1)
-@@ -135,9 +138,9 @@ enum {
- ERR_NONE = 0,
- ERR_DMABUSERR = -1,
- ERR_SENDCMD = -2,
-- ERR_DBERR = -3,
-+ ERR_UNCORERR = -3,
- ERR_BBERR = -4,
-- ERR_SBERR = -5,
-+ ERR_CORERR = -5,
- };
-
- enum {
-@@ -221,6 +224,8 @@ struct pxa3xx_nand_info {
- unsigned int oob_size;
- unsigned int spare_size;
- unsigned int ecc_size;
-+ unsigned int ecc_err_cnt;
-+ unsigned int max_bitflips;
- int retcode;
-
- /* cached register value */
-@@ -571,10 +576,25 @@ static irqreturn_t pxa3xx_nand_irq(int i
-
- status = nand_readl(info, NDSR);
-
-- if (status & NDSR_DBERR)
-- info->retcode = ERR_DBERR;
-- if (status & NDSR_SBERR)
-- info->retcode = ERR_SBERR;
-+ if (status & NDSR_UNCORERR)
-+ info->retcode = ERR_UNCORERR;
-+ if (status & NDSR_CORERR) {
-+ info->retcode = ERR_CORERR;
-+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
-+ info->ecc_bch)
-+ info->ecc_err_cnt = NDSR_ERR_CNT(status);
-+ else
-+ info->ecc_err_cnt = 1;
-+
-+ /*
-+ * Each chunk composing a page is corrected independently,
-+ * and we need to store maximum number of corrected bitflips
-+ * to return it to the MTD layer in ecc.read_page().
-+ */
-+ info->max_bitflips = max_t(unsigned int,
-+ info->max_bitflips,
-+ info->ecc_err_cnt);
-+ }
- if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
- /* whether use dma to transfer data */
- if (info->use_dma) {
-@@ -672,6 +692,7 @@ static void prepare_start_command(struct
- info->use_ecc = 0;
- info->use_spare = 1;
- info->retcode = ERR_NONE;
-+ info->ecc_err_cnt = 0;
- info->ndcb3 = 0;
-
- switch (command) {
-@@ -1053,26 +1074,18 @@ static int pxa3xx_nand_read_page_hwecc(s
- {
- struct pxa3xx_nand_host *host = mtd->priv;
- struct pxa3xx_nand_info *info = host->info_data;
-- int max_bitflips = 0;
-
- chip->read_buf(mtd, buf, mtd->writesize);
- chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
-
-- if (info->retcode == ERR_SBERR) {
-- switch (info->use_ecc) {
-- case 1:
-- max_bitflips = 1;
-- mtd->ecc_stats.corrected++;
-- break;
-- case 0:
-- default:
-- break;
-- }
-- } else if (info->retcode == ERR_DBERR) {
-+ if (info->retcode == ERR_CORERR && info->use_ecc) {
-+ mtd->ecc_stats.corrected += info->ecc_err_cnt;
-+
-+ } else if (info->retcode == ERR_UNCORERR) {
- /*
- * for blank page (all 0xff), HW will calculate its ECC as
- * 0, which is different from the ECC information within
-- * OOB, ignore such double bit errors
-+ * OOB, ignore such uncorrectable errors
- */
- if (is_buf_blank(buf, mtd->writesize))
- info->retcode = ERR_NONE;
-@@ -1080,7 +1093,7 @@ static int pxa3xx_nand_read_page_hwecc(s
- mtd->ecc_stats.failed++;
- }
-
-- return max_bitflips;
-+ return info->max_bitflips;
- }
-
- static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
+++ /dev/null
-From c312e183e96bed3b727888673d4b6b54b8e6283e Mon Sep 17 00:00:00 2001
-From: Brian Norris <computersforpeace@gmail.com>
-Date: Thu, 14 Nov 2013 14:41:32 -0800
-Subject: [PATCH 154/203] mtd: nand: pxa3xx: make ECC configuration checks more
- explicit
-
-The Armada BCH configuration in this driver uses one of the two
-following ECC schemes:
-
- 16-bit correction per 2048 bytes
- 16-bit correction per 1024 bytes
-
-These are sufficient for mapping to the 4-bit per 512-bytes and 8-bit
-per 512-bytes (respectively) minimum correctability requirements of many
-common NAND.
-
-The current code only checks for the required strength (4-bit or 8-bit)
-without checking the ECC step size that is associated with that strength
-(and simply assumes it is 512). While that is often a safe assumption to
-make, let's make it explicit, since we have that information.
-
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 15 ++++++++++++---
- 1 file changed, 12 insertions(+), 3 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1364,9 +1364,13 @@ static int pxa_ecc_init(struct pxa3xx_na
-
- static int armada370_ecc_init(struct pxa3xx_nand_info *info,
- struct nand_ecc_ctrl *ecc,
-- int strength, int page_size)
-+ int strength, int ecc_stepsize, int page_size)
- {
-- if (strength == 4 && page_size == 4096) {
-+ /*
-+ * Required ECC: 4-bit correction per 512 bytes
-+ * Select: 16-bit correction per 2048 bytes
-+ */
-+ if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
- info->ecc_bch = 1;
- info->chunk_size = 2048;
- info->spare_size = 32;
-@@ -1377,7 +1381,11 @@ static int armada370_ecc_init(struct pxa
- ecc->strength = 16;
- return 1;
-
-- } else if (strength == 8 && page_size == 4096) {
-+ /*
-+ * Required ECC: 8-bit correction per 512 bytes
-+ * Select: 16-bit correction per 1024 bytes
-+ */
-+ } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
- info->ecc_bch = 1;
- info->chunk_size = 1024;
- info->spare_size = 0;
-@@ -1485,6 +1493,7 @@ KEEP_CONFIG:
- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
- ret = armada370_ecc_init(info, &chip->ecc,
- chip->ecc_strength_ds,
-+ chip->ecc_step_ds,
- mtd->writesize);
- else
- ret = pxa_ecc_init(info, &chip->ecc,
+++ /dev/null
-From 4c6bade4cf80d77decc5ea89fbaadff8b008f5e9 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 25 Nov 2013 12:35:28 -0300
-Subject: [PATCH 155/203] mtd: nand: pxa3xx: Use info->use_dma to release DMA
- resources
-
-After the driver allocates all DMA resources, it sets "info->use_dma".
-Therefore, we need to check that variable to decide which resources
-needs to be freed, instead of the global use_dma variable.
-
-Without this change, when the device probe fails, the driver will try
-to release unallocated DMA resources, with nasty results.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1288,7 +1288,7 @@ static int pxa3xx_nand_init_buff(struct
- static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
- {
- struct platform_device *pdev = info->pdev;
-- if (use_dma) {
-+ if (info->use_dma) {
- pxa_free_dma(info->data_dma_ch);
- dma_free_coherent(&pdev->dev, info->buf_size,
- info->data_buff, info->data_buff_phys);
+++ /dev/null
-From a701d8e1c4c1e31a208dae616ed9067ba4e90191 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 25 Nov 2013 11:02:51 -0300
-Subject: [PATCH 156/203] mtd: nand: pxa3xx: Use extended cmdfunc() only if
- needed
-
-Currently, we have two different cmdfunc's implementations:
-one for PXA3xx SoC variant and one for Armada 370/XP SoC variant.
-
-The former is the legacy one, typically constrained to devices
-with page sizes smaller or equal to the controller's FIFO buffer.
-On the other side, the latter _only_ supports the so-called extended
-command semantics, which allow to handle devices with larger
-page sizes (4 KiB, 8 KiB, ...).
-
-This means we currently don't support devices with smaller pages on the
-A370/XP SoC. Fix it by first renaming the cmdfuncs variants, and then
-make the choice based on device page size (and SoC variant), rather than
-SoC variant alone.
-
-While at it, add a check for page size, to make sure we don't allow larger
-pages sizes on the PXA3xx variant.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 31 +++++++++++++++++++++----------
- 1 file changed, 21 insertions(+), 10 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -900,8 +900,8 @@ static int prepare_set_command(struct px
- return exec_cmd;
- }
-
--static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
-- int column, int page_addr)
-+static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
-+ int column, int page_addr)
- {
- struct pxa3xx_nand_host *host = mtd->priv;
- struct pxa3xx_nand_info *info = host->info_data;
-@@ -948,9 +948,9 @@ static void pxa3xx_nand_cmdfunc(struct m
- info->state = STATE_IDLE;
- }
-
--static void armada370_nand_cmdfunc(struct mtd_info *mtd,
-- const unsigned command,
-- int column, int page_addr)
-+static void nand_cmdfunc_extended(struct mtd_info *mtd,
-+ const unsigned command,
-+ int column, int page_addr)
- {
- struct pxa3xx_nand_host *host = mtd->priv;
- struct pxa3xx_nand_info *info = host->info_data;
-@@ -1490,6 +1490,21 @@ KEEP_CONFIG:
- chip->bbt_md = &bbt_mirror_descr;
- }
-
-+ /*
-+ * If the page size is bigger than the FIFO size, let's check
-+ * we are given the right variant and then switch to the extended
-+ * (aka splitted) command handling,
-+ */
-+ if (mtd->writesize > PAGE_CHUNK_SIZE) {
-+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
-+ chip->cmdfunc = nand_cmdfunc_extended;
-+ } else {
-+ dev_err(&info->pdev->dev,
-+ "unsupported page size on this variant\n");
-+ return -ENODEV;
-+ }
-+ }
-+
- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
- ret = armada370_ecc_init(info, &chip->ecc,
- chip->ecc_strength_ds,
-@@ -1569,11 +1584,7 @@ static int alloc_nand_resource(struct pl
- chip->read_buf = pxa3xx_nand_read_buf;
- chip->write_buf = pxa3xx_nand_write_buf;
- chip->options |= NAND_NO_SUBPAGE_WRITE;
--
-- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
-- chip->cmdfunc = armada370_nand_cmdfunc;
-- else
-- chip->cmdfunc = pxa3xx_nand_cmdfunc;
-+ chip->cmdfunc = nand_cmdfunc;
- }
-
- spin_lock_init(&chip->controller->lock);
+++ /dev/null
-From 70c36de37f357f38b5a56292534133d75e7d8870 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 25 Nov 2013 12:36:18 -0300
-Subject: [PATCH 157/203] mtd: nand: pxa3xx: Consolidate ECC initialization
-
-In order to avoid code duplication, let's consolidate the ECC setting
-for all SoC variants. Such decision is based on page size and ECC
-strength requirements.
-
-Also, provide a default value for the case where such ECC information
-is not provided (non-ONFI devices).
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 40 ++++++++++++++++------------------------
- 1 file changed, 16 insertions(+), 24 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1335,13 +1335,9 @@ static int pxa3xx_nand_sensing(struct px
-
- static int pxa_ecc_init(struct pxa3xx_nand_info *info,
- struct nand_ecc_ctrl *ecc,
-- int strength, int page_size)
-+ int strength, int ecc_stepsize, int page_size)
- {
-- /*
-- * We don't use strength here as the PXA variant
-- * is used with non-ONFI compliant devices.
-- */
-- if (page_size == 2048) {
-+ if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
- info->chunk_size = 2048;
- info->spare_size = 40;
- info->ecc_size = 24;
-@@ -1350,7 +1346,7 @@ static int pxa_ecc_init(struct pxa3xx_na
- ecc->strength = 1;
- return 1;
-
-- } else if (page_size == 512) {
-+ } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
- info->chunk_size = 512;
- info->spare_size = 8;
- info->ecc_size = 8;
-@@ -1358,19 +1354,12 @@ static int pxa_ecc_init(struct pxa3xx_na
- ecc->size = 512;
- ecc->strength = 1;
- return 1;
-- }
-- return 0;
--}
-
--static int armada370_ecc_init(struct pxa3xx_nand_info *info,
-- struct nand_ecc_ctrl *ecc,
-- int strength, int ecc_stepsize, int page_size)
--{
- /*
- * Required ECC: 4-bit correction per 512 bytes
- * Select: 16-bit correction per 2048 bytes
- */
-- if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
-+ } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
- info->ecc_bch = 1;
- info->chunk_size = 2048;
- info->spare_size = 32;
-@@ -1411,6 +1400,7 @@ static int pxa3xx_nand_scan(struct mtd_i
- uint32_t id = -1;
- uint64_t chipsize;
- int i, ret, num;
-+ uint16_t ecc_strength, ecc_step;
-
- if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
- goto KEEP_CONFIG;
-@@ -1505,15 +1495,17 @@ KEEP_CONFIG:
- }
- }
-
-- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
-- ret = armada370_ecc_init(info, &chip->ecc,
-- chip->ecc_strength_ds,
-- chip->ecc_step_ds,
-- mtd->writesize);
-- else
-- ret = pxa_ecc_init(info, &chip->ecc,
-- chip->ecc_strength_ds,
-- mtd->writesize);
-+ ecc_strength = chip->ecc_strength_ds;
-+ ecc_step = chip->ecc_step_ds;
-+
-+ /* Set default ECC strength requirements on non-ONFI devices */
-+ if (ecc_strength < 1 && ecc_step < 1) {
-+ ecc_strength = 1;
-+ ecc_step = 512;
-+ }
-+
-+ ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
-+ ecc_step, mtd->writesize);
- if (!ret) {
- dev_err(&info->pdev->dev,
- "ECC strength %d at page size %d is not supported\n",
+++ /dev/null
-From 933f5de151614aee0f7b1f664f86b04f3773a075 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:59 -0300
-Subject: [PATCH 158/203] mtd: nand: Allow to build pxa3xx_nand on Orion
- platforms
-
-The Armada 370 and Armada XP SoC families, selected by PLAT_ORION,
-have a Nand Flash Controller (NFC) IP very similar to the one present
-in PXA platforms. Therefore, we want to build this driver on PLAT_ORION.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -354,7 +354,7 @@ config MTD_NAND_ATMEL
-
- config MTD_NAND_PXA3xx
- tristate "Support for NAND flash devices on PXA3xx"
-- depends on PXA3xx || ARCH_MMP
-+ depends on PXA3xx || ARCH_MMP || PLAT_ORION
- help
- This enables the driver for the NAND flash device found on
- PXA3xx processors
+++ /dev/null
-From b1abf1e5c6a7531a1a93a0ab6c75607dcb0e9947 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:17:11 -0300
-Subject: [PATCH 159/203] mtd: nand: pxa3xx: Make config menu show supported
- platforms
-
-Since we have now support for the NFCv2 controller found on
-Armada 370/XP platforms.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/mtd/nand/Kconfig | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -353,11 +353,11 @@ config MTD_NAND_ATMEL
- on Atmel AT91 and AVR32 processors.
-
- config MTD_NAND_PXA3xx
-- tristate "Support for NAND flash devices on PXA3xx"
-+ tristate "NAND support on PXA3xx and Armada 370/XP"
- depends on PXA3xx || ARCH_MMP || PLAT_ORION
- help
- This enables the driver for the NAND flash device found on
-- PXA3xx processors
-+ PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
-
- config MTD_NAND_SLC_LPC32XX
- tristate "NXP LPC32xx SLC Controller"
+++ /dev/null
-From a18945a7fd26b83c765b60bcffe306421f7efe80 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 2 Dec 2013 18:44:40 -0300
-Subject: [PATCH 160/203] ARM: mvebu: config: Add NAND support
-
-Enable the pxa3xx-nand driver, which now supports the NAND controller
-in Armada 370/XP SoC.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
----
- arch/arm/configs/mvebu_defconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/configs/mvebu_defconfig
-+++ b/arch/arm/configs/mvebu_defconfig
-@@ -53,6 +53,8 @@ CONFIG_MTD_CFI_INTELEXT=y
- CONFIG_MTD_CFI_AMDSTD=y
- CONFIG_MTD_CFI_STAA=y
- CONFIG_MTD_PHYSMAP_OF=y
-+CONFIG_MTD_NAND=y
-+CONFIG_MTD_NAND_PXA3xx=y
- CONFIG_SERIAL_8250_DW=y
- CONFIG_GPIOLIB=y
- CONFIG_GPIO_SYSFS=y
+++ /dev/null
-From f834da3962eaee5d72f152e9a066c06ec0d9c2c4 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 5 Dec 2013 13:35:37 -0300
-Subject: [PATCH 161/203] net: mvneta: Fix incorrect DMA unmapping size
-
-The current code unmaps the DMA mapping created for rx skb_buff's by
-using the data_size as the the mapping size. This is wrong since the
-correct size to specify should match the size used to create the mapping.
-
-This commit removes the following DMA_API_DEBUG warning:
-
-------------[ cut here ]------------
-WARNING: at lib/dma-debug.c:887 check_unmap+0x3a8/0x860()
-mvneta d0070000.ethernet: DMA-API: device driver frees DMA memory with different size [device address=0x000000002eb80000] [map size=1600 bytes] [unmap size=66 bytes]
-CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.21-01444-ga88ae13-dirty #92
-[<c0013600>] (unwind_backtrace+0x0/0xf8) from [<c0010fb8>] (show_stack+0x10/0x14)
-[<c0010fb8>] (show_stack+0x10/0x14) from [<c001afa0>] (warn_slowpath_common+0x48/0x68)
-[<c001afa0>] (warn_slowpath_common+0x48/0x68) from [<c001b01c>] (warn_slowpath_fmt+0x30/0x40)
-[<c001b01c>] (warn_slowpath_fmt+0x30/0x40) from [<c018d0fc>] (check_unmap+0x3a8/0x860)
-[<c018d0fc>] (check_unmap+0x3a8/0x860) from [<c018d734>] (debug_dma_unmap_page+0x64/0x70)
-[<c018d734>] (debug_dma_unmap_page+0x64/0x70) from [<c0233f78>] (mvneta_rx+0xec/0x468)
-[<c0233f78>] (mvneta_rx+0xec/0x468) from [<c023436c>] (mvneta_poll+0x78/0x16c)
-[<c023436c>] (mvneta_poll+0x78/0x16c) from [<c02db468>] (net_rx_action+0x94/0x160)
-[<c02db468>] (net_rx_action+0x94/0x160) from [<c0021e68>] (__do_softirq+0xe8/0x1d0)
-[<c0021e68>] (__do_softirq+0xe8/0x1d0) from [<c0021ff8>] (do_softirq+0x4c/0x58)
-[<c0021ff8>] (do_softirq+0x4c/0x58) from [<c0022228>] (irq_exit+0x58/0x90)
-[<c0022228>] (irq_exit+0x58/0x90) from [<c000e7c8>] (handle_IRQ+0x3c/0x94)
-[<c000e7c8>] (handle_IRQ+0x3c/0x94) from [<c0008548>] (armada_370_xp_handle_irq+0x4c/0xb4)
-[<c0008548>] (armada_370_xp_handle_irq+0x4c/0xb4) from [<c000dc20>] (__irq_svc+0x40/0x50)
-Exception stack(0xc04f1f70 to 0xc04f1fb8)
-1f60: c1fe46f8 00000000 00001d92 00001d92
-1f80: c04f0000 c04f0000 c04f84a4 c03e081c c05220e7 00000001 c05220e7 c04f0000
-1fa0: 00000000 c04f1fb8 c000eaf8 c004c048 60000113 ffffffff
-[<c000dc20>] (__irq_svc+0x40/0x50) from [<c004c048>] (cpu_startup_entry+0x54/0x128)
-[<c004c048>] (cpu_startup_entry+0x54/0x128) from [<c04c1a14>] (start_kernel+0x29c/0x2f0)
-[<c04c1a14>] (start_kernel+0x29c/0x2f0) from [<00008074>] (0x8074)
----[ end trace d4955f6acd178110 ]---
-Mapped at:
- [<c018d600>] debug_dma_map_page+0x4c/0x11c
- [<c0235d6c>] mvneta_setup_rxqs+0x398/0x598
- [<c0236084>] mvneta_open+0x40/0x17c
- [<c02dbbd4>] __dev_open+0x9c/0x100
- [<c02dbe58>] __dev_change_flags+0x7c/0x134
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
----
- drivers/net/ethernet/marvell/mvneta.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -1341,7 +1341,7 @@ static void mvneta_rxq_drop_pkts(struct
-
- dev_kfree_skb_any(skb);
- dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
-- rx_desc->data_size, DMA_FROM_DEVICE);
-+ MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
- }
-
- if (rx_done)
-@@ -1387,7 +1387,7 @@ static int mvneta_rx(struct mvneta_port
- }
-
- dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
-- rx_desc->data_size, DMA_FROM_DEVICE);
-+ MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
-
- rx_bytes = rx_desc->data_size -
- (ETH_FCS_LEN + MVNETA_MH_SIZE);
+++ /dev/null
-From 7efaa8677ffd07d54d0122b5e92f29b74a36ad39 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 19 Dec 2013 06:08:03 -0300
-Subject: [PATCH 162/203] mtd: nand: pxa3xx: Clear need_wait flag when starting
- a command
-
-Currently the driver assumes all commands will eventually trigger a RnB
-transition, and thus a "device is ready" IRQ.
-
-This assumption means that on every issued command, the dev_ready completion
-handler is init'ed and the need_wait flag is set.
-
-However this is incorrect: some commands (such as NAND_CMD_STATUS) don't
-make the device 'busy' and thus a RnB transition never occurs.
-Given, the NAND core never calls waitfunc() after such commands, this
-is not a problem.
-
-Therefore, it's possible to only clear the need_wait flag on every command
-that is started.
-
-This fixes a current bug that can be reproduced on PXA boards by writing
-blank (all 0xff'ed) to a page:
-
- 1. The kernel issues NAND_CMD_STATUS and sets need_wait=1. The flag
- won't be cleared for this command since no RnB transition is
- involved.
-
- 2. NAND_CMD_PAGEPROG is issued but since the data is blank, the driver
- decides not to execute the command (and no IRQ activity is
- involved).
-
- 3. The NAND core calls waitfunc() and waits for the dev_ready
- completion, which will never end since the device _is_ already ready.
-
-Tested-by: Arnaud Ebalard <arno@natisbad.org>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -694,6 +694,7 @@ static void prepare_start_command(struct
- info->retcode = ERR_NONE;
- info->ecc_err_cnt = 0;
- info->ndcb3 = 0;
-+ info->need_wait = 0;
-
- switch (command) {
- case NAND_CMD_READ0:
+++ /dev/null
-From b340059540cbc90412f3e7159dc57a178e0effd6 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 4 Dec 2013 14:28:59 +0100
-Subject: [PATCH 163/203] ARM: mvebu: move ARMADA_XP_MAX_CPUS to
- armada-370-xp.h
-
-The ARMADA_XP_MAX_CPUS definition was in common.h, which as its name
-says, is common to all mvebu SoCs. It is more logical to have this XP
-specific definition in the already existing armada-370-xp.h header
-file.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
----
- arch/arm/mach-mvebu/armada-370-xp.h | 2 ++
- arch/arm/mach-mvebu/common.h | 2 --
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/mach-mvebu/armada-370-xp.h
-+++ b/arch/arm/mach-mvebu/armada-370-xp.h
-@@ -18,6 +18,8 @@
- #ifdef CONFIG_SMP
- #include <linux/cpumask.h>
-
-+#define ARMADA_XP_MAX_CPUS 4
-+
- void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq);
- void armada_xp_mpic_smp_cpu_init(void);
- #endif
---- a/arch/arm/mach-mvebu/common.h
-+++ b/arch/arm/mach-mvebu/common.h
-@@ -15,8 +15,6 @@
- #ifndef __ARCH_MVEBU_COMMON_H
- #define __ARCH_MVEBU_COMMON_H
-
--#define ARMADA_XP_MAX_CPUS 4
--
- void mvebu_restart(char mode, const char *cmd);
-
- void armada_370_xp_init_irq(void);
+++ /dev/null
-From 10208caf7f0ebfb3d6b546aa2ae66e42462551e0 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Wed, 4 Dec 2013 14:37:52 +0100
-Subject: [PATCH 164/203] ARM: mvebu: fix register length for Armada XP PMSU
-
-The per-CPU PMSU registers documented in the datasheet start at
-0x22100 and the last register for CPU3 is at 0x22428. However, the DT
-informations use <0x22100 0x430>, which makes the region end at
-0x22530 and not 0x22430.
-
-Moreover, looking at the datasheet, we can see that the registers for
-CPU0 start at 0x22100, for CPU1 at 0x22200, for CPU2 at 0x22300 and
-for CPU3 at 0x22400. It seems clear that 0x100 bytes of registers have
-been used per CPU.
-
-Therefore, this commit reduces the length of the PMSU per-CPU register
-area from the incorrect 0x430 bytes to a more logical 0x400 bytes.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
----
- arch/arm/boot/dts/armada-xp.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -48,7 +48,7 @@
-
- armada-370-xp-pmsu@22000 {
- compatible = "marvell,armada-370-xp-pmsu";
-- reg = <0x22100 0x430>, <0x20800 0x20>;
-+ reg = <0x22100 0x400>, <0x20800 0x20>;
- };
-
- serial@12200 {
+++ /dev/null
-From 167c442fb9adf4c2e02663a0291c6cfae31bad72 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Thu, 5 Dec 2013 10:02:25 +0100
-Subject: [PATCH 165/203] ARM: mvebu: make armada_370_xp_pmsu_init() static
-
-The armada_370_xp_pmsu_init() function is called as an
-early_initcall(). Therefore, there is no need to export this function,
-and we can make it static.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
----
- arch/arm/mach-mvebu/common.h | 1 -
- arch/arm/mach-mvebu/pmsu.c | 2 +-
- 2 files changed, 1 insertion(+), 2 deletions(-)
-
---- a/arch/arm/mach-mvebu/common.h
-+++ b/arch/arm/mach-mvebu/common.h
-@@ -22,7 +22,6 @@ void armada_370_xp_handle_irq(struct pt_
-
- void armada_xp_cpu_die(unsigned int cpu);
- int armada_370_xp_coherency_init(void);
--int armada_370_xp_pmsu_init(void);
- void armada_xp_secondary_startup(void);
- extern struct smp_operations armada_xp_smp_ops;
- #endif
---- a/arch/arm/mach-mvebu/pmsu.c
-+++ b/arch/arm/mach-mvebu/pmsu.c
-@@ -58,7 +58,7 @@ int armada_xp_boot_cpu(unsigned int cpu_
- }
- #endif
-
--int __init armada_370_xp_pmsu_init(void)
-+static int __init armada_370_xp_pmsu_init(void)
- {
- struct device_node *np;
-
+++ /dev/null
-From ea331be867c791bca8200e6d707499845d8dfa87 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 13 Aug 2013 11:43:10 -0300
-Subject: [PATCH 166/203] clocksource: armada-370-xp: Use BIT()
-
-This is a purely cosmetic commit: we replace hardcoded values that
-representing bits by BIT(), which is slightly more readable.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
----
- drivers/clocksource/time-armada-370-xp.c | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
---- a/drivers/clocksource/time-armada-370-xp.c
-+++ b/drivers/clocksource/time-armada-370-xp.c
-@@ -35,13 +35,13 @@
- * Timer block registers.
- */
- #define TIMER_CTRL_OFF 0x0000
--#define TIMER0_EN 0x0001
--#define TIMER0_RELOAD_EN 0x0002
--#define TIMER0_25MHZ 0x0800
-+#define TIMER0_EN BIT(0)
-+#define TIMER0_RELOAD_EN BIT(1)
-+#define TIMER0_25MHZ BIT(11)
- #define TIMER0_DIV(div) ((div) << 19)
--#define TIMER1_EN 0x0004
--#define TIMER1_RELOAD_EN 0x0008
--#define TIMER1_25MHZ 0x1000
-+#define TIMER1_EN BIT(2)
-+#define TIMER1_RELOAD_EN BIT(3)
-+#define TIMER1_25MHZ BIT(12)
- #define TIMER1_DIV(div) ((div) << 22)
- #define TIMER_EVENTS_STATUS 0x0004
- #define TIMER0_CLR_MASK (~0x1)
+++ /dev/null
-From 7a5e03909417ccecc85819837d10cbb6ffe1d759 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 13 Aug 2013 11:43:11 -0300
-Subject: [PATCH 167/203] clocksource: armada-370-xp: Simplify TIMER_CTRL
- register access
-
-This commit creates two functions to access the TIMER_CTRL register:
-one for global one for the per-cpu. This makes the code much more
-readable. In addition, since the TIMER_CTRL register is also used for
-watchdog, this is preparation work for future thread-safe improvements.
-
-Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/clocksource/time-armada-370-xp.c | 69 ++++++++++++++------------------
- 1 file changed, 30 insertions(+), 39 deletions(-)
-
---- a/drivers/clocksource/time-armada-370-xp.c
-+++ b/drivers/clocksource/time-armada-370-xp.c
-@@ -71,6 +71,18 @@ static u32 ticks_per_jiffy;
-
- static struct clock_event_device __percpu **percpu_armada_370_xp_evt;
-
-+static void timer_ctrl_clrset(u32 clr, u32 set)
-+{
-+ writel((readl(timer_base + TIMER_CTRL_OFF) & ~clr) | set,
-+ timer_base + TIMER_CTRL_OFF);
-+}
-+
-+static void local_timer_ctrl_clrset(u32 clr, u32 set)
-+{
-+ writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
-+ local_base + TIMER_CTRL_OFF);
-+}
-+
- static u32 notrace armada_370_xp_read_sched_clock(void)
- {
- return ~readl(timer_base + TIMER0_VAL_OFF);
-@@ -83,7 +95,6 @@ static int
- armada_370_xp_clkevt_next_event(unsigned long delta,
- struct clock_event_device *dev)
- {
-- u32 u;
- /*
- * Clear clockevent timer interrupt.
- */
-@@ -97,11 +108,8 @@ armada_370_xp_clkevt_next_event(unsigned
- /*
- * Enable the timer.
- */
-- u = readl(local_base + TIMER_CTRL_OFF);
-- u = ((u & ~TIMER0_RELOAD_EN) | TIMER0_EN |
-- TIMER0_DIV(TIMER_DIVIDER_SHIFT));
-- writel(u, local_base + TIMER_CTRL_OFF);
--
-+ local_timer_ctrl_clrset(TIMER0_RELOAD_EN,
-+ TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT));
- return 0;
- }
-
-@@ -109,8 +117,6 @@ static void
- armada_370_xp_clkevt_mode(enum clock_event_mode mode,
- struct clock_event_device *dev)
- {
-- u32 u;
--
- if (mode == CLOCK_EVT_MODE_PERIODIC) {
-
- /*
-@@ -122,18 +128,14 @@ armada_370_xp_clkevt_mode(enum clock_eve
- /*
- * Enable timer.
- */
--
-- u = readl(local_base + TIMER_CTRL_OFF);
--
-- writel((u | TIMER0_EN | TIMER0_RELOAD_EN |
-- TIMER0_DIV(TIMER_DIVIDER_SHIFT)),
-- local_base + TIMER_CTRL_OFF);
-+ local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN |
-+ TIMER0_EN |
-+ TIMER0_DIV(TIMER_DIVIDER_SHIFT));
- } else {
- /*
- * Disable timer.
- */
-- u = readl(local_base + TIMER_CTRL_OFF);
-- writel(u & ~TIMER0_EN, local_base + TIMER_CTRL_OFF);
-+ local_timer_ctrl_clrset(TIMER0_EN, 0);
-
- /*
- * ACK pending timer interrupt.
-@@ -169,18 +171,18 @@ static irqreturn_t armada_370_xp_timer_i
- */
- static int __cpuinit armada_370_xp_timer_setup(struct clock_event_device *evt)
- {
-- u32 u;
-+ u32 clr = 0, set = 0;
- int cpu = smp_processor_id();
-
- /* Use existing clock_event for cpu 0 */
- if (!smp_processor_id())
- return 0;
-
-- u = readl(local_base + TIMER_CTRL_OFF);
- if (timer25Mhz)
-- writel(u | TIMER0_25MHZ, local_base + TIMER_CTRL_OFF);
-+ set = TIMER0_25MHZ;
- else
-- writel(u & ~TIMER0_25MHZ, local_base + TIMER_CTRL_OFF);
-+ clr = TIMER0_25MHZ;
-+ local_timer_ctrl_clrset(clr, set);
-
- evt->name = armada_370_xp_clkevt.name;
- evt->irq = armada_370_xp_clkevt.irq;
-@@ -212,7 +214,7 @@ static struct local_timer_ops armada_370
-
- static void __init armada_370_xp_timer_init(struct device_node *np)
- {
-- u32 u;
-+ u32 clr = 0, set = 0;
- int res;
-
- timer_base = of_iomap(np, 0);
-@@ -221,29 +223,20 @@ static void __init armada_370_xp_timer_i
-
- if (of_find_property(np, "marvell,timer-25Mhz", NULL)) {
- /* The fixed 25MHz timer is available so let's use it */
-- u = readl(local_base + TIMER_CTRL_OFF);
-- writel(u | TIMER0_25MHZ,
-- local_base + TIMER_CTRL_OFF);
-- u = readl(timer_base + TIMER_CTRL_OFF);
-- writel(u | TIMER0_25MHZ,
-- timer_base + TIMER_CTRL_OFF);
-+ set = TIMER0_25MHZ;
- timer_clk = 25000000;
- } else {
- unsigned long rate = 0;
- struct clk *clk = of_clk_get(np, 0);
- WARN_ON(IS_ERR(clk));
- rate = clk_get_rate(clk);
-- u = readl(local_base + TIMER_CTRL_OFF);
-- writel(u & ~(TIMER0_25MHZ),
-- local_base + TIMER_CTRL_OFF);
--
-- u = readl(timer_base + TIMER_CTRL_OFF);
-- writel(u & ~(TIMER0_25MHZ),
-- timer_base + TIMER_CTRL_OFF);
--
- timer_clk = rate / TIMER_DIVIDER;
-+
-+ clr = TIMER0_25MHZ;
- timer25Mhz = false;
- }
-+ timer_ctrl_clrset(clr, set);
-+ local_timer_ctrl_clrset(clr, set);
-
- /*
- * We use timer 0 as clocksource, and private(local) timer 0
-@@ -265,10 +258,8 @@ static void __init armada_370_xp_timer_i
- writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
- writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
-
-- u = readl(timer_base + TIMER_CTRL_OFF);
--
-- writel((u | TIMER0_EN | TIMER0_RELOAD_EN |
-- TIMER0_DIV(TIMER_DIVIDER_SHIFT)), timer_base + TIMER_CTRL_OFF);
-+ timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN |
-+ TIMER0_DIV(TIMER_DIVIDER_SHIFT));
-
- clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
- "armada_370_xp_clocksource",
+++ /dev/null
-From 9cb47bf175645d15f97e6d964dd4a4f089275ef5 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 13 Aug 2013 11:43:13 -0300
-Subject: [PATCH 168/203] clocksource: armada-370-xp: Introduce new compatibles
-
-The Armada XP SoC clocksource driver cannot work without the 25 MHz
-fixed timer. Therefore it's appropriate to introduce a new compatible
-string and use it to set the 25 MHz fixed timer.
-
-The 'marvell,timer-25MHz' property will be marked as deprecated.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
----
- drivers/clocksource/time-armada-370-xp.c | 54 +++++++++++++++++++++++---------
- 1 file changed, 39 insertions(+), 15 deletions(-)
-
---- a/drivers/clocksource/time-armada-370-xp.c
-+++ b/drivers/clocksource/time-armada-370-xp.c
-@@ -13,6 +13,19 @@
- *
- * Timer 0 is used as free-running clocksource, while timer 1 is
- * used as clock_event_device.
-+ *
-+ * ---
-+ * Clocksource driver for Armada 370 and Armada XP SoC.
-+ * This driver implements one compatible string for each SoC, given
-+ * each has its own characteristics:
-+ *
-+ * * Armada 370 has no 25 MHz fixed timer.
-+ *
-+ * * Armada XP cannot work properly without such 25 MHz fixed timer as
-+ * doing otherwise leads to using a clocksource whose frequency varies
-+ * when doing cpufreq frequency changes.
-+ *
-+ * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
- */
-
- #include <linux/init.h>
-@@ -212,7 +225,7 @@ static struct local_timer_ops armada_370
- .stop = armada_370_xp_timer_stop,
- };
-
--static void __init armada_370_xp_timer_init(struct device_node *np)
-+static void __init armada_370_xp_timer_common_init(struct device_node *np)
- {
- u32 clr = 0, set = 0;
- int res;
-@@ -221,20 +234,10 @@ static void __init armada_370_xp_timer_i
- WARN_ON(!timer_base);
- local_base = of_iomap(np, 1);
-
-- if (of_find_property(np, "marvell,timer-25Mhz", NULL)) {
-- /* The fixed 25MHz timer is available so let's use it */
-+ if (timer25Mhz)
- set = TIMER0_25MHZ;
-- timer_clk = 25000000;
-- } else {
-- unsigned long rate = 0;
-- struct clk *clk = of_clk_get(np, 0);
-- WARN_ON(IS_ERR(clk));
-- rate = clk_get_rate(clk);
-- timer_clk = rate / TIMER_DIVIDER;
--
-+ else
- clr = TIMER0_25MHZ;
-- timer25Mhz = false;
-- }
- timer_ctrl_clrset(clr, set);
- local_timer_ctrl_clrset(clr, set);
-
-@@ -288,5 +291,26 @@ static void __init armada_370_xp_timer_i
- #endif
- }
- }
--CLOCKSOURCE_OF_DECLARE(armada_370_xp, "marvell,armada-370-xp-timer",
-- armada_370_xp_timer_init);
-+
-+static void __init armada_xp_timer_init(struct device_node *np)
-+{
-+ /* The fixed 25MHz timer is required, timer25Mhz is true by default */
-+ timer_clk = 25000000;
-+
-+ armada_370_xp_timer_common_init(np);
-+}
-+CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
-+ armada_xp_timer_init);
-+
-+static void __init armada_370_timer_init(struct device_node *np)
-+{
-+ struct clk *clk = of_clk_get(np, 0);
-+
-+ WARN_ON(IS_ERR(clk));
-+ timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
-+ timer25Mhz = false;
-+
-+ armada_370_xp_timer_common_init(np);
-+}
-+CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
-+ armada_370_timer_init);
+++ /dev/null
-From bcaac3d9265d751f7d20df6ed0ac24241308dff7 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 20 Aug 2013 12:45:52 -0300
-Subject: [PATCH 169/203] clocksource: armada-370-xp: Replace WARN_ON with
- BUG_ON
-
-If the clock fails to be obtained and the timer fails to be properly
-registered, the kernel will freeze real soon. Instead, let's BUG()
-where the actual problem is located.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Acked-by: Jason Cooper <jason@lakedaemon.net>
-Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
----
- drivers/clocksource/time-armada-370-xp.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clocksource/time-armada-370-xp.c
-+++ b/drivers/clocksource/time-armada-370-xp.c
-@@ -306,7 +306,7 @@ static void __init armada_370_timer_init
- {
- struct clk *clk = of_clk_get(np, 0);
-
-- WARN_ON(IS_ERR(clk));
-+ BUG_ON(IS_ERR(clk));
- timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
- timer25Mhz = false;
-
+++ /dev/null
-From 7d7214129f7bde5bb55c0691968407b48f08efb5 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 20 Aug 2013 12:45:53 -0300
-Subject: [PATCH 170/203] clocksource: armada-370-xp: Get reference fixed-clock
- by name
-
-The Armada XP timer has two mandatory clock inputs: nbclk and refclk,
-as specified by the device-tree binding.
-
-This commit fixes the clock selection. Instead of hard-coding the clock
-rate for the 25 MHz reference fixed-clock, obtain the clock by its name.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Acked-by: Jason Cooper <jason@lakedaemon.net>
-Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
----
- drivers/clocksource/time-armada-370-xp.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
---- a/drivers/clocksource/time-armada-370-xp.c
-+++ b/drivers/clocksource/time-armada-370-xp.c
-@@ -294,8 +294,11 @@ static void __init armada_370_xp_timer_c
-
- static void __init armada_xp_timer_init(struct device_node *np)
- {
-- /* The fixed 25MHz timer is required, timer25Mhz is true by default */
-- timer_clk = 25000000;
-+ struct clk *clk = of_clk_get_by_name(np, "fixed");
-+
-+ /* The 25Mhz fixed clock is mandatory, and must always be available */
-+ BUG_ON(IS_ERR(clk));
-+ timer_clk = clk_get_rate(clk);
-
- armada_370_xp_timer_common_init(np);
- }
+++ /dev/null
-From 3d7976bb4a0f34203456cc0e9054b4a6401c9fdb Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 26 Nov 2013 18:20:14 -0300
-Subject: [PATCH 171/203] clocksource: armada-370-xp: Register sched_clock
- after the counter reset
-
-This commit registers the sched_clock _after_ the counter reset
-(instead of before). This removes the timestamp 'jump' in kernel
-log messages.
-
-Before this change:
-
-[ 0.000000] sched_clock: 32 bits at 25MHz, resolution 40ns, wraps every 171798691800ns
-[ 0.000000] Initializing Coherency fabric
-[ 0.000000] Aurora cache controller enabled
-[ 0.000000] l2x0: 16 ways, CACHE_ID 0x00000100, AUX_CTRL 0x1a696b12, Cache size: 1024 kB
-[ 163.507447] Calibrating delay loop... 1325.05 BogoMIPS (lpj=662528)
-[ 163.521419] pid_max: default: 32768 minimum: 301
-[ 163.526185] Mount-cache hash table entries: 512
-[ 163.531095] CPU: Testing write buffer coherency: ok
-
-After this change:
-
-[ 0.000000] sched_clock: 32 bits at 25MHz, resolution 40ns, wraps every 171798691800ns
-[ 0.000000] Initializing Coherency fabric
-[ 0.000000] Aurora cache controller enabled
-[ 0.000000] l2x0: 16 ways, CACHE_ID 0x00000100, AUX_CTRL 0x1a696b12, Cache size: 1024 kB
-[ 0.016849] Calibrating delay loop... 1325.05 BogoMIPS (lpj=662528)
-[ 0.030820] pid_max: default: 32768 minimum: 301
-[ 0.035588] Mount-cache hash table entries: 512
-[ 0.040500] CPU: Testing write buffer coherency: ok
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Acked-by: Jason Cooper <jason@lakedaemon.net>
----
- drivers/clocksource/time-armada-370-xp.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/clocksource/time-armada-370-xp.c
-+++ b/drivers/clocksource/time-armada-370-xp.c
-@@ -250,11 +250,6 @@ static void __init armada_370_xp_timer_c
- ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
-
- /*
-- * Set scale and timer for sched_clock.
-- */
-- setup_sched_clock(armada_370_xp_read_sched_clock, 32, timer_clk);
--
-- /*
- * Setup free-running clocksource timer (interrupts
- * disabled).
- */
-@@ -264,6 +259,11 @@ static void __init armada_370_xp_timer_c
- timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN |
- TIMER0_DIV(TIMER_DIVIDER_SHIFT));
-
-+ /*
-+ * Set scale and timer for sched_clock.
-+ */
-+ setup_sched_clock(armada_370_xp_read_sched_clock, 32, timer_clk);
-+
- clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
- "armada_370_xp_clocksource",
- timer_clk, 300, 32, clocksource_mmio_readl_down);
+++ /dev/null
-From e33103d8d4cfc513467eb30bc4faee5c91c8e6c2 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 13 Aug 2013 11:43:15 -0300
-Subject: [PATCH 172/203] ARM: mvebu: Fix the Armada 370/XP timer compatible
- strings
-
-The "marvell,armada-370-xp-timer" compatible string, together with
-the "marvell,timer-25Mhz" property are deprecated and should be
-removed from current DT.
-
-Instead, the timer DT nodes are now required to have an appropriate
-compatible string, which should be either "marvell,armada-370-timer"
-or "marvell,armada-xp-timer", depending on SoC.
-
-The clock property is now required only for Armada 370 so move it accordingly.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370-xp.dtsi | 2 --
- arch/arm/boot/dts/armada-370.dtsi | 5 +++++
- arch/arm/boot/dts/armada-xp.dtsi | 2 +-
- 3 files changed, 6 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
-@@ -143,10 +143,8 @@
- };
-
- timer@20300 {
-- compatible = "marvell,armada-370-xp-timer";
- reg = <0x20300 0x30>, <0x21040 0x30>;
- interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
-- clocks = <&coreclk 2>;
- };
-
- sata@a0000 {
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -163,6 +163,11 @@
- interrupts = <91>;
- };
-
-+ timer@20300 {
-+ compatible = "marvell,armada-370-timer";
-+ clocks = <&coreclk 2>;
-+ };
-+
- coreclk: mvebu-sar@18230 {
- compatible = "marvell,armada-370-core-clock";
- reg = <0x18230 0x08>;
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -69,7 +69,7 @@
- };
-
- timer@20300 {
-- marvell,timer-25Mhz;
-+ compatible = "marvell,armada-xp-timer";
- };
-
- coreclk: mvebu-sar@18230 {
+++ /dev/null
-From e4011be91332bacc5cf166e1ce92c3678fc7c646 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 20 Aug 2013 12:45:50 -0300
-Subject: [PATCH 173/203] ARM: mvebu: Add the reference 25 MHz fixed-clock to
- Armada XP
-
-The Armada XP SoC has a reference 25 MHz fixed-clock that is used in
-some controllers such as the timer and the watchdog. This commit adds
-a DT representation of this clock through a fixed-clock compatible node.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Reviewed-by: Mike Turquette <mturquette@linaro.org>
-Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-xp.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -169,4 +169,13 @@
- };
- };
- };
-+
-+ clocks {
-+ /* 25 MHz reference crystal */
-+ refclk: oscillator {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <25000000>;
-+ };
-+ };
- };
+++ /dev/null
-From 200b303fc6c2709340996b02ae0c9a7130de7ec3 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 20 Aug 2013 12:45:51 -0300
-Subject: [PATCH 174/203] ARM: mvebu: Add clock properties to Armada XP timer
- node
-
-With the addition of the Armada XP reference clock, we can now model
-accurately the available clock inputs for the timer: namely, nbclk
-and refclk. For each of this clock inputs we assign a name, for the
-driver to select as appropriate.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Reviewed-by: Mike Turquette <mturquette@linaro.org>
-Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-xp.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -70,6 +70,8 @@
-
- timer@20300 {
- compatible = "marvell,armada-xp-timer";
-+ clocks = <&coreclk 2>, <&refclk>;
-+ clock-names = "nbclk", "fixed";
- };
-
- coreclk: mvebu-sar@18230 {
+++ /dev/null
-From 079d1ecae4bd4166a0f89bcb8e0c96bec1b39622 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 8 Aug 2013 18:03:09 -0300
-Subject: [PATCH 175/203] ARM: mvebu: Relocate PCIe node in Armada 370 RD board
-
-The pcie-controller node needs to be relocated according the MBus
-DT binding, since it's now a child of the mbus-compatible node.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-370-rd.dts | 32 ++++++++++++++++----------------
- 1 file changed, 16 insertions(+), 16 deletions(-)
-
---- a/arch/arm/boot/dts/armada-370-rd.dts
-+++ b/arch/arm/boot/dts/armada-370-rd.dts
-@@ -31,6 +31,22 @@
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
-
-+ pcie-controller {
-+ status = "okay";
-+
-+ /* Internal mini-PCIe connector */
-+ pcie@1,0 {
-+ /* Port 0, Lane 0 */
-+ status = "okay";
-+ };
-+
-+ /* Internal mini-PCIe connector */
-+ pcie@2,0 {
-+ /* Port 1, Lane 0 */
-+ status = "okay";
-+ };
-+ };
-+
- internal-regs {
- serial@12000 {
- clock-frequency = <200000000>;
-@@ -88,22 +104,6 @@
- gpios = <&gpio0 6 1>;
- };
- };
--
-- pcie-controller {
-- status = "okay";
--
-- /* Internal mini-PCIe connector */
-- pcie@1,0 {
-- /* Port 0, Lane 0 */
-- status = "okay";
-- };
--
-- /* Internal mini-PCIe connector */
-- pcie@2,0 {
-- /* Port 1, Lane 0 */
-- status = "okay";
-- };
-- };
- };
- };
- };
+++ /dev/null
-From 6dc29d94d92ccc558b946bd57cd8d7cb19d8def1 Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Thu, 19 Dec 2013 09:30:47 -0300
-Subject: [PATCH 176/203] of/irq: create interrupts-extended property
-
-The standard interrupts property in device tree can only handle
-interrupts coming from a single interrupt parent. If a device is wired
-to multiple interrupt controllers, then it needs to be attached to a
-node with an interrupt-map property to demux the interrupt specifiers
-which is confusing. It would be a lot easier if there was a form of the
-interrupts property that allows for a separate interrupt phandle for
-each interrupt specifier.
-
-This patch does exactly that by creating a new interrupts-extended
-property which reuses the phandle+arguments pattern used by GPIOs and
-other core bindings.
-
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
-Acked-by: Tony Lindgren <tony@atomide.com>
-Acked-by: Kumar Gala <galak@codeaurora.org>
-[grant.likely: removed versatile platform hunks into separate patch]
-Cc: Rob Herring <rob.herring@calxeda.com>
-
-Conflicts:
- arch/arm/boot/dts/testcases/tests-interrupts.dtsi
- drivers/of/selftest.c
----
- .../bindings/interrupt-controller/interrupts.txt | 29 +++++++++++++++++-----
- drivers/of/irq.c | 16 ++++++++----
- 2 files changed, 34 insertions(+), 11 deletions(-)
-
---- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-+++ b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-@@ -4,16 +4,33 @@ Specifying interrupt information for dev
- 1) Interrupt client nodes
- -------------------------
-
--Nodes that describe devices which generate interrupts must contain an
--"interrupts" property. This property must contain a list of interrupt
--specifiers, one per output interrupt. The format of the interrupt specifier is
--determined by the interrupt controller to which the interrupts are routed; see
--section 2 below for details.
-+Nodes that describe devices which generate interrupts must contain an either an
-+"interrupts" property or an "interrupts-extended" property. These properties
-+contain a list of interrupt specifiers, one per output interrupt. The format of
-+the interrupt specifier is determined by the interrupt controller to which the
-+interrupts are routed; see section 2 below for details.
-+
-+ Example:
-+ interrupt-parent = <&intc1>;
-+ interrupts = <5 0>, <6 0>;
-
- The "interrupt-parent" property is used to specify the controller to which
- interrupts are routed and contains a single phandle referring to the interrupt
- controller node. This property is inherited, so it may be specified in an
--interrupt client node or in any of its parent nodes.
-+interrupt client node or in any of its parent nodes. Interrupts listed in the
-+"interrupts" property are always in reference to the node's interrupt parent.
-+
-+The "interrupts-extended" property is a special form for use when a node needs
-+to reference multiple interrupt parents. Each entry in this property contains
-+both the parent phandle and the interrupt specifier. "interrupts-extended"
-+should only be used when a device has multiple interrupt parents.
-+
-+ Example:
-+ interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
-+
-+A device node may contain either "interrupts" or "interrupts-extended", but not
-+both. If both properties are present, then the operating system should log an
-+error and use only the data in "interrupts".
-
- 2) Interrupt controller nodes
- -----------------------------
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -293,17 +293,23 @@ int of_irq_map_one(struct device_node *d
- if (of_irq_workarounds & OF_IMAP_OLDWORLD_MAC)
- return of_irq_map_oldworld(device, index, out_irq);
-
-+ /* Get the reg property (if any) */
-+ addr = of_get_property(device, "reg", NULL);
-+
- /* Get the interrupts property */
- intspec = of_get_property(device, "interrupts", &intlen);
-- if (intspec == NULL)
-- return -EINVAL;
-+ if (intspec == NULL) {
-+ /* Try the new-style interrupts-extended */
-+ res = of_parse_phandle_with_args(device, "interrupts-extended",
-+ "#interrupt-cells", index, out_irq);
-+ if (res)
-+ return -EINVAL;
-+ return of_irq_parse_raw(addr, out_irq);
-+ }
- intlen /= sizeof(*intspec);
-
- pr_debug(" intspec=%d intlen=%d\n", be32_to_cpup(intspec), intlen);
-
-- /* Get the reg property (if any) */
-- addr = of_get_property(device, "reg", NULL);
--
- /* Look for the interrupt parent. */
- p = of_irq_find_parent(device);
- if (p == NULL)
+++ /dev/null
-From f159ea8ab3bce09a098d0d56c9e8909f385b87aa Mon Sep 17 00:00:00 2001
-From: Axel Lin <axel.lin@ingics.com>
-Date: Thu, 19 Dec 2013 09:30:48 -0300
-Subject: [PATCH 177/203] of/irq: Avoid calling list_first_entry() for empty
- list
-
-list_first_entry() expects the list is not empty, we need to check if list is
-empty before calling list_first_entry(). Thus use list_first_entry_or_null()
-instead of list_first_entry().
-
-Signed-off-by: Axel Lin <axel.lin@ingics.com>
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
----
- drivers/of/irq.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -488,8 +488,9 @@ void __init of_irq_init(const struct of_
- }
-
- /* Get the next pending parent that might have children */
-- desc = list_first_entry(&intc_parent_list, typeof(*desc), list);
-- if (list_empty(&intc_parent_list) || !desc) {
-+ desc = list_first_entry_or_null(&intc_parent_list,
-+ typeof(*desc), list);
-+ if (!desc) {
- pr_err("of_irq_init: children remain, but no parents\n");
- break;
- }
+++ /dev/null
-From 704f3796c741df558d624078c5094439c0b65d09 Mon Sep 17 00:00:00 2001
-From: Rob Herring <rob.herring@calxeda.com>
-Date: Thu, 19 Dec 2013 09:30:49 -0300
-Subject: [PATCH 178/203] of: clean-up ifdefs in of_irq.h
-
-Much of of_irq.h is needlessly ifdef'ed. Clean this up and minimize the
-amount ifdef'ed code. This fixes some build warnings when CONFIG_OF
-is not enabled (seen on i386 and x86_64):
-
-include/linux/of_irq.h:82:7: warning: 'struct device_node' declared inside parameter list [enabled by default]
-include/linux/of_irq.h:82:7: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]
-include/linux/of_irq.h:87:47: warning: 'struct device_node' declared inside parameter list [enabled by default]
-
-Compile tested on i386, sparc and arm.
-
-Reported-by: Randy Dunlap <rdunlap@infradead.org>
-Cc: Grant Likely <grant.likely@linaro.org>
-Signed-off-by: Rob Herring <rob.herring@calxeda.com>
----
- include/linux/of_irq.h | 20 ++++++++------------
- 1 file changed, 8 insertions(+), 12 deletions(-)
-
---- a/include/linux/of_irq.h
-+++ b/include/linux/of_irq.h
-@@ -1,8 +1,6 @@
- #ifndef __OF_IRQ_H
- #define __OF_IRQ_H
-
--#if defined(CONFIG_OF)
--struct of_irq;
- #include <linux/types.h>
- #include <linux/errno.h>
- #include <linux/irq.h>
-@@ -10,14 +8,6 @@ struct of_irq;
- #include <linux/ioport.h>
- #include <linux/of.h>
-
--/*
-- * irq_of_parse_and_map() is used by all OF enabled platforms; but SPARC
-- * implements it differently. However, the prototype is the same for all,
-- * so declare it here regardless of the CONFIG_OF_IRQ setting.
-- */
--extern unsigned int irq_of_parse_and_map(struct device_node *node, int index);
--
--#if defined(CONFIG_OF_IRQ)
- /**
- * of_irq - container for device_node/irq_specifier pair for an irq controller
- * @controller: pointer to interrupt controller device tree node
-@@ -71,11 +61,17 @@ extern int of_irq_to_resource(struct dev
- extern int of_irq_count(struct device_node *dev);
- extern int of_irq_to_resource_table(struct device_node *dev,
- struct resource *res, int nr_irqs);
--extern struct device_node *of_irq_find_parent(struct device_node *child);
-
- extern void of_irq_init(const struct of_device_id *matches);
-
--#endif /* CONFIG_OF_IRQ */
-+#if defined(CONFIG_OF)
-+/*
-+ * irq_of_parse_and_map() is used by all OF enabled platforms; but SPARC
-+ * implements it differently. However, the prototype is the same for all,
-+ * so declare it here regardless of the CONFIG_OF_IRQ setting.
-+ */
-+extern unsigned int irq_of_parse_and_map(struct device_node *node, int index);
-+extern struct device_node *of_irq_find_parent(struct device_node *child);
-
- #else /* !CONFIG_OF */
- static inline unsigned int irq_of_parse_and_map(struct device_node *dev,
+++ /dev/null
-From 15a2884ede54118137708ccc72f246fe986f8a57 Mon Sep 17 00:00:00 2001
-From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
-Date: Thu, 19 Dec 2013 09:30:50 -0300
-Subject: [PATCH 179/203] of/irq: init struct resource to 0 in
- of_irq_to_resource()
-
-It almost does not matter because most users use only the ->start member
-of the struct. However if this struct is passed to a platform device
-which is then added via platform_device_add() then the ->parent member is
-also used.
-
-Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
----
- drivers/of/irq.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -351,6 +351,7 @@ int of_irq_to_resource(struct device_nod
- if (r && irq) {
- const char *name = NULL;
-
-+ memset(r, 0, sizeof(*r));
- /*
- * Get optional "interrupts-names" property to add a name
- * to the resource.
+++ /dev/null
-From 3d73f7a8db8a7506630174d0e8609138d97c8326 Mon Sep 17 00:00:00 2001
-From: Yijing Wang <wangyijing@huawei.com>
-Date: Thu, 19 Dec 2013 09:30:51 -0300
-Subject: [PATCH 180/203] irq/of: Fix comment typo for irq_of_parse_and_map
-
-Fix trivial comment typo for irq_of_parse_and_map().
-
-Signed-off-by: Yijing Wang <wangyijing@huawei.com>
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
----
- drivers/of/irq.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -28,7 +28,7 @@
-
- /**
- * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
-- * @device: Device node of the device whose interrupt is to be mapped
-+ * @dev: Device node of the device whose interrupt is to be mapped
- * @index: Index of the interrupt to map
- *
- * This function is a wrapper that chains of_irq_map_one() and
+++ /dev/null
-From 02abb20a226a5a1e5c6dfaaf765dd71a90200cf9 Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Thu, 19 Dec 2013 09:30:52 -0300
-Subject: [PATCH 181/203] of: Fix dereferencing node name in debug output to be
- safe
-
-Several locations in the of_address and of_irq code dereference the
-full_name parameter from a device_node pointer without checking if the
-pointer is valid. This patch switches to use of_node_full_name() which
-always checks the pointer.
-
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
----
- drivers/of/address.c | 6 +++---
- drivers/of/irq.c | 8 ++++----
- 2 files changed, 7 insertions(+), 7 deletions(-)
-
---- a/drivers/of/address.c
-+++ b/drivers/of/address.c
-@@ -482,7 +482,7 @@ static u64 __of_translate_address(struct
- int na, ns, pna, pns;
- u64 result = OF_BAD_ADDR;
-
-- pr_debug("OF: ** translation for device %s **\n", dev->full_name);
-+ pr_debug("OF: ** translation for device %s **\n", of_node_full_name(dev));
-
- /* Increase refcount at current level */
- of_node_get(dev);
-@@ -497,13 +497,13 @@ static u64 __of_translate_address(struct
- bus->count_cells(dev, &na, &ns);
- if (!OF_CHECK_COUNTS(na, ns)) {
- printk(KERN_ERR "prom_parse: Bad cell count for %s\n",
-- dev->full_name);
-+ of_node_full_name(dev));
- goto bail;
- }
- memcpy(addr, in_addr, na * 4);
-
- pr_debug("OF: bus is %s (na=%d, ns=%d) on %s\n",
-- bus->name, na, ns, parent->full_name);
-+ bus->name, na, ns, of_node_full_name(parent));
- of_dump_addr("OF: translating address:", addr, na);
-
- /* Translate */
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -102,7 +102,7 @@ int of_irq_map_raw(struct device_node *p
- int imaplen, match, i;
-
- pr_debug("of_irq_map_raw: par=%s,intspec=[0x%08x 0x%08x...],ointsize=%d\n",
-- parent->full_name, be32_to_cpup(intspec),
-+ of_node_full_name(parent), be32_to_cpup(intspec),
- be32_to_cpup(intspec + 1), ointsize);
-
- ipar = of_node_get(parent);
-@@ -126,7 +126,7 @@ int of_irq_map_raw(struct device_node *p
- goto fail;
- }
-
-- pr_debug("of_irq_map_raw: ipar=%s, size=%d\n", ipar->full_name, intsize);
-+ pr_debug("of_irq_map_raw: ipar=%s, size=%d\n", of_node_full_name(ipar), intsize);
-
- if (ointsize != intsize)
- return -EINVAL;
-@@ -287,7 +287,7 @@ int of_irq_map_one(struct device_node *d
- u32 intsize, intlen;
- int res = -EINVAL;
-
-- pr_debug("of_irq_map_one: dev=%s, index=%d\n", device->full_name, index);
-+ pr_debug("of_irq_map_one: dev=%s, index=%d\n", of_node_full_name(device), index);
-
- /* OldWorld mac stuff is "special", handle out of line */
- if (of_irq_workarounds & OF_IMAP_OLDWORLD_MAC)
-@@ -361,7 +361,7 @@ int of_irq_to_resource(struct device_nod
-
- r->start = r->end = irq;
- r->flags = IORESOURCE_IRQ;
-- r->name = name ? name : dev->full_name;
-+ r->name = name ? name : of_node_full_name(dev);
- }
-
- return irq;
+++ /dev/null
-From 4bd60065fb935a5d390c9a442be3a18d2ea18eee Mon Sep 17 00:00:00 2001
-From: Tomasz Figa <tomasz.figa@gmail.com>
-Date: Thu, 19 Dec 2013 09:30:53 -0300
-Subject: [PATCH 182/203] of/irq: Pass trigger type in IRQ resource flags
-
-Some drivers might rely on availability of trigger flags in IRQ
-resource, for example to configure the hardware for particular interrupt
-type. However current code creating IRQ resources from data in device
-tree does not configure trigger flags in resulting resources.
-
-This patch tries to solve the problem, based on the fact that
-irq_of_parse_and_map() configures the trigger based on DT interrupt
-specifier and IRQD_TRIGGER_* flags are consistent with IORESOURCE_IRQ_*,
-and we can get correct trigger flags by calling irqd_get_trigger_type()
-after mapping the interrupt.
-
-Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
-[grant.likely: Merged the two assignments to r->flags]
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
----
- drivers/of/irq.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -360,7 +360,7 @@ int of_irq_to_resource(struct device_nod
- &name);
-
- r->start = r->end = irq;
-- r->flags = IORESOURCE_IRQ;
-+ r->flags = IORESOURCE_IRQ | irqd_get_trigger_type(irq_get_irq_data(irq));
- r->name = name ? name : of_node_full_name(dev);
- }
-
+++ /dev/null
-From fd33285b3dab183df0cea06de9f618886dc0f1c0 Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Thu, 19 Dec 2013 09:30:54 -0300
-Subject: [PATCH 183/203] of/irq: Rename of_irq_map_* functions to
- of_irq_parse_*
-
-The OF irq handling code has been overloading the term 'map' to refer to
-both parsing the data in the device tree and mapping it to the internal
-linux irq system. This is probably because the device tree does have the
-concept of an 'interrupt-map' function for translating interrupt
-references from one node to another, but 'map' is still confusing when
-the primary purpose of some of the functions are to parse the DT data.
-
-This patch renames all the of_irq_map_* functions to of_irq_parse_*
-which makes it clear that there is a difference between the parsing
-phase and the mapping phase. Kernel code can make use of just the
-parsing or just the mapping support as needed by the subsystem.
-
-The patch was generated mechanically with a handful of sed commands.
-
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
-Acked-by: Michal Simek <monstr@monstr.eu>
-Acked-by: Tony Lindgren <tony@atomide.com>
-Cc: Ralf Baechle <ralf@linux-mips.org>
-Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
-Conflicts:
- arch/arm/mach-integrator/pci_v3.c
- arch/mips/pci/pci-rt3883.c
----
- arch/arm/mach-integrator/pci_v3.c | 279 +++++++++++++++++++++++++
- arch/microblaze/pci/pci-common.c | 2 +-
- arch/mips/pci/fixup-lantiq.c | 2 +-
- arch/powerpc/kernel/pci-common.c | 2 +-
- arch/powerpc/platforms/cell/celleb_scc_pciex.c | 2 +-
- arch/powerpc/platforms/cell/celleb_scc_sio.c | 2 +-
- arch/powerpc/platforms/cell/spider-pic.c | 2 +-
- arch/powerpc/platforms/cell/spu_manage.c | 2 +-
- arch/powerpc/platforms/fsl_uli1575.c | 2 +-
- arch/powerpc/platforms/powermac/pic.c | 2 +-
- arch/powerpc/platforms/pseries/event_sources.c | 2 +-
- arch/powerpc/sysdev/mpic_msi.c | 2 +-
- arch/x86/kernel/devicetree.c | 2 +-
- drivers/of/address.c | 4 +-
- drivers/of/irq.c | 28 +--
- drivers/of/of_pci_irq.c | 10 +-
- drivers/pci/host/pci-mvebu.c | 2 +-
- include/linux/of_irq.h | 8 +-
- include/linux/of_pci.h | 2 +-
- 19 files changed, 318 insertions(+), 39 deletions(-)
-
---- a/arch/arm/mach-integrator/pci_v3.c
-+++ b/arch/arm/mach-integrator/pci_v3.c
-@@ -610,3 +610,282 @@ void __init pci_v3_postinit(void)
-
- register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
- }
-+
-+/*
-+ * A small note about bridges and interrupts. The DECchip 21050 (and
-+ * later) adheres to the PCI-PCI bridge specification. This says that
-+ * the interrupts on the other side of a bridge are swizzled in the
-+ * following manner:
-+ *
-+ * Dev Interrupt Interrupt
-+ * Pin on Pin on
-+ * Device Connector
-+ *
-+ * 4 A A
-+ * B B
-+ * C C
-+ * D D
-+ *
-+ * 5 A B
-+ * B C
-+ * C D
-+ * D A
-+ *
-+ * 6 A C
-+ * B D
-+ * C A
-+ * D B
-+ *
-+ * 7 A D
-+ * B A
-+ * C B
-+ * D C
-+ *
-+ * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
-+ * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
-+ */
-+
-+/*
-+ * This routine handles multiple bridges.
-+ */
-+static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
-+{
-+ if (*pinp == 0)
-+ *pinp = 1;
-+
-+ return pci_common_swizzle(dev, pinp);
-+}
-+
-+static int irq_tab[4] __initdata = {
-+ IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
-+};
-+
-+/*
-+ * map the specified device/slot/pin to an IRQ. This works out such
-+ * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
-+ */
-+static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ int intnr = ((slot - 9) + (pin - 1)) & 3;
-+
-+ return irq_tab[intnr];
-+}
-+
-+static struct hw_pci pci_v3 __initdata = {
-+ .swizzle = pci_v3_swizzle,
-+ .setup = pci_v3_setup,
-+ .nr_controllers = 1,
-+ .ops = &pci_v3_ops,
-+ .preinit = pci_v3_preinit,
-+ .postinit = pci_v3_postinit,
-+};
-+
-+#ifdef CONFIG_OF
-+
-+static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ struct of_irq oirq;
-+ int ret;
-+
-+ ret = of_irq_parse_pci(dev, &oirq);
-+ if (ret) {
-+ dev_err(&dev->dev, "of_irq_parse_pci() %d\n", ret);
-+ /* Proper return code 0 == NO_IRQ */
-+ return 0;
-+ }
-+
-+ return irq_create_of_mapping(oirq.controller, oirq.specifier,
-+ oirq.size);
-+}
-+
-+static int __init pci_v3_dtprobe(struct platform_device *pdev,
-+ struct device_node *np)
-+{
-+ struct of_pci_range_parser parser;
-+ struct of_pci_range range;
-+ struct resource *res;
-+ int irq, ret;
-+
-+ if (of_pci_range_parser_init(&parser, np))
-+ return -EINVAL;
-+
-+ /* Get base for bridge registers */
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev, "unable to obtain PCIv3 base\n");
-+ return -ENODEV;
-+ }
-+ pci_v3_base = devm_ioremap(&pdev->dev, res->start,
-+ resource_size(res));
-+ if (!pci_v3_base) {
-+ dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
-+ return -ENODEV;
-+ }
-+
-+ /* Get and request error IRQ resource */
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq <= 0) {
-+ dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n");
-+ return -ENODEV;
-+ }
-+ ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0,
-+ "PCIv3 error", NULL);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret);
-+ return ret;
-+ }
-+
-+ for_each_of_pci_range(&parser, &range) {
-+ if (!range.flags) {
-+ of_pci_range_to_resource(&range, np, &conf_mem);
-+ conf_mem.name = "PCIv3 config";
-+ }
-+ if (range.flags & IORESOURCE_IO) {
-+ of_pci_range_to_resource(&range, np, &io_mem);
-+ io_mem.name = "PCIv3 I/O";
-+ }
-+ if ((range.flags & IORESOURCE_MEM) &&
-+ !(range.flags & IORESOURCE_PREFETCH)) {
-+ non_mem_pci = range.pci_addr;
-+ non_mem_pci_sz = range.size;
-+ of_pci_range_to_resource(&range, np, &non_mem);
-+ non_mem.name = "PCIv3 non-prefetched mem";
-+ }
-+ if ((range.flags & IORESOURCE_MEM) &&
-+ (range.flags & IORESOURCE_PREFETCH)) {
-+ pre_mem_pci = range.pci_addr;
-+ pre_mem_pci_sz = range.size;
-+ of_pci_range_to_resource(&range, np, &pre_mem);
-+ pre_mem.name = "PCIv3 prefetched mem";
-+ }
-+ }
-+
-+ if (!conf_mem.start || !io_mem.start ||
-+ !non_mem.start || !pre_mem.start) {
-+ dev_err(&pdev->dev, "missing ranges in device node\n");
-+ return -EINVAL;
-+ }
-+
-+ pci_v3.map_irq = pci_v3_map_irq_dt;
-+ pci_common_init_dev(&pdev->dev, &pci_v3);
-+
-+ return 0;
-+}
-+
-+#else
-+
-+static inline int pci_v3_dtprobe(struct platform_device *pdev,
-+ struct device_node *np)
-+{
-+ return -EINVAL;
-+}
-+
-+#endif
-+
-+static int __init pci_v3_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ int ret;
-+
-+ /* Remap the Integrator system controller */
-+ ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
-+ if (!ap_syscon_base) {
-+ dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
-+ return -ENODEV;
-+ }
-+
-+ /* Device tree probe path */
-+ if (np)
-+ return pci_v3_dtprobe(pdev, np);
-+
-+ pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K);
-+ if (!pci_v3_base) {
-+ dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
-+ return -ENODEV;
-+ }
-+
-+ ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
-+ if (ret) {
-+ dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n",
-+ ret);
-+ return -ENODEV;
-+ }
-+
-+ conf_mem.name = "PCIv3 config";
-+ conf_mem.start = PHYS_PCI_CONFIG_BASE;
-+ conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1;
-+ conf_mem.flags = IORESOURCE_MEM;
-+
-+ io_mem.name = "PCIv3 I/O";
-+ io_mem.start = PHYS_PCI_IO_BASE;
-+ io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1;
-+ io_mem.flags = IORESOURCE_MEM;
-+
-+ non_mem_pci = 0x00000000;
-+ non_mem_pci_sz = SZ_256M;
-+ non_mem.name = "PCIv3 non-prefetched mem";
-+ non_mem.start = PHYS_PCI_MEM_BASE;
-+ non_mem.end = PHYS_PCI_MEM_BASE + SZ_256M - 1;
-+ non_mem.flags = IORESOURCE_MEM;
-+
-+ pre_mem_pci = 0x10000000;
-+ pre_mem_pci_sz = SZ_256M;
-+ pre_mem.name = "PCIv3 prefetched mem";
-+ pre_mem.start = PHYS_PCI_PRE_BASE + SZ_256M;
-+ pre_mem.end = PHYS_PCI_PRE_BASE + SZ_256M - 1;
-+ pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-+
-+ pci_v3.map_irq = pci_v3_map_irq;
-+
-+ pci_common_init_dev(&pdev->dev, &pci_v3);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id pci_ids[] = {
-+ { .compatible = "v3,v360epc-pci", },
-+ {},
-+};
-+
-+static struct platform_driver pci_v3_driver = {
-+ .driver = {
-+ .name = "pci-v3",
-+ .of_match_table = pci_ids,
-+ },
-+};
-+
-+static int __init pci_v3_init(void)
-+{
-+ return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
-+}
-+
-+subsys_initcall(pci_v3_init);
-+
-+/*
-+ * Static mappings for the PCIv3 bridge
-+ *
-+ * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
-+ * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
-+ * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
-+ */
-+static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = {
-+ {
-+ .virtual = (unsigned long)PCI_MEMORY_VADDR,
-+ .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
-+ .length = SZ_16M,
-+ .type = MT_DEVICE
-+ }, {
-+ .virtual = (unsigned long)PCI_CONFIG_VADDR,
-+ .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
-+ .length = SZ_16M,
-+ .type = MT_DEVICE
-+ }
-+};
-+
-+int __init pci_v3_early_init(void)
-+{
-+ iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc));
-+ vga_base = (unsigned long)PCI_MEMORY_VADDR;
-+ pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
-+ return 0;
-+}
---- a/arch/microblaze/pci/pci-common.c
-+++ b/arch/microblaze/pci/pci-common.c
-@@ -217,7 +217,7 @@ int pci_read_irq_line(struct pci_dev *pc
- memset(&oirq, 0xff, sizeof(oirq));
- #endif
- /* Try to get a mapping from the device-tree */
-- if (of_irq_map_pci(pci_dev, &oirq)) {
-+ if (of_irq_parse_pci(pci_dev, &oirq)) {
- u8 line, pin;
-
- /* If that fails, lets fallback to what is in the config
---- a/arch/mips/pci/fixup-lantiq.c
-+++ b/arch/mips/pci/fixup-lantiq.c
-@@ -28,7 +28,7 @@ int __init pcibios_map_irq(const struct
- struct of_irq dev_irq;
- int irq;
-
-- if (of_irq_map_pci(dev, &dev_irq)) {
-+ if (of_irq_parse_pci(dev, &dev_irq)) {
- dev_err(&dev->dev, "trying to map irq for unknown slot:%d pin:%d\n",
- slot, pin);
- return 0;
---- a/arch/powerpc/kernel/pci-common.c
-+++ b/arch/powerpc/kernel/pci-common.c
-@@ -237,7 +237,7 @@ static int pci_read_irq_line(struct pci_
- memset(&oirq, 0xff, sizeof(oirq));
- #endif
- /* Try to get a mapping from the device-tree */
-- if (of_irq_map_pci(pci_dev, &oirq)) {
-+ if (of_irq_parse_pci(pci_dev, &oirq)) {
- u8 line, pin;
-
- /* If that fails, lets fallback to what is in the config
---- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
-+++ b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
-@@ -507,7 +507,7 @@ static __init int celleb_setup_pciex(str
- phb->ops = &scc_pciex_pci_ops;
-
- /* internal interrupt handler */
-- if (of_irq_map_one(node, 1, &oirq)) {
-+ if (of_irq_parse_one(node, 1, &oirq)) {
- pr_err("PCIEXC:Failed to map irq\n");
- goto error;
- }
---- a/arch/powerpc/platforms/cell/celleb_scc_sio.c
-+++ b/arch/powerpc/platforms/cell/celleb_scc_sio.c
-@@ -53,7 +53,7 @@ static int __init txx9_serial_init(void)
- if (!(txx9_serial_bitmap & (1<<i)))
- continue;
-
-- if (of_irq_map_one(node, i, &irq))
-+ if (of_irq_parse_one(node, i, &irq))
- continue;
- if (of_address_to_resource(node,
- txx9_scc_tab[i].index, &res))
---- a/arch/powerpc/platforms/cell/spider-pic.c
-+++ b/arch/powerpc/platforms/cell/spider-pic.c
-@@ -236,7 +236,7 @@ static unsigned int __init spider_find_c
- * tree in case the device-tree is ever fixed
- */
- struct of_irq oirq;
-- if (of_irq_map_one(pic->host->of_node, 0, &oirq) == 0) {
-+ if (of_irq_parse_one(pic->host->of_node, 0, &oirq) == 0) {
- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
- oirq.size);
- return virq;
---- a/arch/powerpc/platforms/cell/spu_manage.c
-+++ b/arch/powerpc/platforms/cell/spu_manage.c
-@@ -182,7 +182,7 @@ static int __init spu_map_interrupts(str
- int i;
-
- for (i=0; i < 3; i++) {
-- ret = of_irq_map_one(np, i, &oirq);
-+ ret = of_irq_parse_one(np, i, &oirq);
- if (ret) {
- pr_debug("spu_new: failed to get irq %d\n", i);
- goto err;
---- a/arch/powerpc/platforms/fsl_uli1575.c
-+++ b/arch/powerpc/platforms/fsl_uli1575.c
-@@ -333,7 +333,7 @@ static void hpcd_final_uli5288(struct pc
-
- laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
- laddr[1] = laddr[2] = 0;
-- of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
-+ of_irq_parse_raw(hosenode, &pin, 1, laddr, &oirq);
- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
- oirq.size);
- dev->irq = virq;
---- a/arch/powerpc/platforms/powermac/pic.c
-+++ b/arch/powerpc/platforms/powermac/pic.c
-@@ -393,7 +393,7 @@ static void __init pmac_pic_probe_oldsty
- #endif
- }
-
--int of_irq_map_oldworld(struct device_node *device, int index,
-+int of_irq_parse_oldworld(struct device_node *device, int index,
- struct of_irq *out_irq)
- {
- const u32 *ints = NULL;
---- a/arch/powerpc/platforms/pseries/event_sources.c
-+++ b/arch/powerpc/platforms/pseries/event_sources.c
-@@ -55,7 +55,7 @@ void request_event_sources_irqs(struct d
- /* Else use normal interrupt tree parsing */
- else {
- /* First try to do a proper OF tree parsing */
-- for (index = 0; of_irq_map_one(np, index, &oirq) == 0;
-+ for (index = 0; of_irq_parse_one(np, index, &oirq) == 0;
- index++) {
- if (count > 15)
- break;
---- a/arch/powerpc/sysdev/mpic_msi.c
-+++ b/arch/powerpc/sysdev/mpic_msi.c
-@@ -63,7 +63,7 @@ static int mpic_msi_reserve_u3_hwirqs(st
- pr_debug("mpic: mapping hwirqs for %s\n", np->full_name);
-
- index = 0;
-- while (of_irq_map_one(np, index++, &oirq) == 0) {
-+ while (of_irq_parse_one(np, index++, &oirq) == 0) {
- ops->xlate(mpic->irqhost, NULL, oirq.specifier,
- oirq.size, &hwirq, &flags);
- msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, hwirq);
---- a/arch/x86/kernel/devicetree.c
-+++ b/arch/x86/kernel/devicetree.c
-@@ -117,7 +117,7 @@ static int x86_of_pci_irq_enable(struct
- if (!pin)
- return 0;
-
-- ret = of_irq_map_pci(dev, &oirq);
-+ ret = of_irq_parse_pci(dev, &oirq);
- if (ret)
- return ret;
-
---- a/drivers/of/address.c
-+++ b/drivers/of/address.c
-@@ -525,12 +525,12 @@ static u64 __of_translate_address(struct
- pbus->count_cells(dev, &pna, &pns);
- if (!OF_CHECK_COUNTS(pna, pns)) {
- printk(KERN_ERR "prom_parse: Bad cell count for %s\n",
-- dev->full_name);
-+ of_node_full_name(dev));
- break;
- }
-
- pr_debug("OF: parent bus is %s (na=%d, ns=%d) on %s\n",
-- pbus->name, pna, pns, parent->full_name);
-+ pbus->name, pna, pns, of_node_full_name(parent));
-
- /* Apply bus translation */
- if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop))
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -31,14 +31,14 @@
- * @dev: Device node of the device whose interrupt is to be mapped
- * @index: Index of the interrupt to map
- *
-- * This function is a wrapper that chains of_irq_map_one() and
-+ * This function is a wrapper that chains of_irq_parse_one() and
- * irq_create_of_mapping() to make things easier to callers
- */
- unsigned int irq_of_parse_and_map(struct device_node *dev, int index)
- {
- struct of_irq oirq;
-
-- if (of_irq_map_one(dev, index, &oirq))
-+ if (of_irq_parse_one(dev, index, &oirq))
- return 0;
-
- return irq_create_of_mapping(oirq.controller, oirq.specifier,
-@@ -79,7 +79,7 @@ struct device_node *of_irq_find_parent(s
- }
-
- /**
-- * of_irq_map_raw - Low level interrupt tree parsing
-+ * of_irq_parse_raw - Low level interrupt tree parsing
- * @parent: the device interrupt parent
- * @intspec: interrupt specifier ("interrupts" property of the device)
- * @ointsize: size of the passed in interrupt specifier
-@@ -93,7 +93,7 @@ struct device_node *of_irq_find_parent(s
- * properties, for example when resolving PCI interrupts when no device
- * node exist for the parent.
- */
--int of_irq_map_raw(struct device_node *parent, const __be32 *intspec,
-+int of_irq_parse_raw(struct device_node *parent, const __be32 *intspec,
- u32 ointsize, const __be32 *addr, struct of_irq *out_irq)
- {
- struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL;
-@@ -101,7 +101,7 @@ int of_irq_map_raw(struct device_node *p
- u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0;
- int imaplen, match, i;
-
-- pr_debug("of_irq_map_raw: par=%s,intspec=[0x%08x 0x%08x...],ointsize=%d\n",
-+ pr_debug("of_irq_parse_raw: par=%s,intspec=[0x%08x 0x%08x...],ointsize=%d\n",
- of_node_full_name(parent), be32_to_cpup(intspec),
- be32_to_cpup(intspec + 1), ointsize);
-
-@@ -126,7 +126,7 @@ int of_irq_map_raw(struct device_node *p
- goto fail;
- }
-
-- pr_debug("of_irq_map_raw: ipar=%s, size=%d\n", of_node_full_name(ipar), intsize);
-+ pr_debug("of_irq_parse_raw: ipar=%s, size=%d\n", of_node_full_name(ipar), intsize);
-
- if (ointsize != intsize)
- return -EINVAL;
-@@ -269,29 +269,29 @@ int of_irq_map_raw(struct device_node *p
-
- return -EINVAL;
- }
--EXPORT_SYMBOL_GPL(of_irq_map_raw);
-+EXPORT_SYMBOL_GPL(of_irq_parse_raw);
-
- /**
-- * of_irq_map_one - Resolve an interrupt for a device
-+ * of_irq_parse_one - Resolve an interrupt for a device
- * @device: the device whose interrupt is to be resolved
- * @index: index of the interrupt to resolve
- * @out_irq: structure of_irq filled by this function
- *
- * This function resolves an interrupt, walking the tree, for a given
-- * device-tree node. It's the high level pendant to of_irq_map_raw().
-+ * device-tree node. It's the high level pendant to of_irq_parse_raw().
- */
--int of_irq_map_one(struct device_node *device, int index, struct of_irq *out_irq)
-+int of_irq_parse_one(struct device_node *device, int index, struct of_irq *out_irq)
- {
- struct device_node *p;
- const __be32 *intspec, *tmp, *addr;
- u32 intsize, intlen;
- int res = -EINVAL;
-
-- pr_debug("of_irq_map_one: dev=%s, index=%d\n", of_node_full_name(device), index);
-+ pr_debug("of_irq_parse_one: dev=%s, index=%d\n", of_node_full_name(device), index);
-
- /* OldWorld mac stuff is "special", handle out of line */
- if (of_irq_workarounds & OF_IMAP_OLDWORLD_MAC)
-- return of_irq_map_oldworld(device, index, out_irq);
-+ return of_irq_parse_oldworld(device, index, out_irq);
-
- /* Get the reg property (if any) */
- addr = of_get_property(device, "reg", NULL);
-@@ -328,13 +328,13 @@ int of_irq_map_one(struct device_node *d
- goto out;
-
- /* Get new specifier and map it */
-- res = of_irq_map_raw(p, intspec + index * intsize, intsize,
-+ res = of_irq_parse_raw(p, intspec + index * intsize, intsize,
- addr, out_irq);
- out:
- of_node_put(p);
- return res;
- }
--EXPORT_SYMBOL_GPL(of_irq_map_one);
-+EXPORT_SYMBOL_GPL(of_irq_parse_one);
-
- /**
- * of_irq_to_resource - Decode a node's IRQ and return it as a resource
---- a/drivers/of/of_pci_irq.c
-+++ b/drivers/of/of_pci_irq.c
-@@ -5,7 +5,7 @@
- #include <asm/prom.h>
-
- /**
-- * of_irq_map_pci - Resolve the interrupt for a PCI device
-+ * of_irq_parse_pci - Resolve the interrupt for a PCI device
- * @pdev: the device whose interrupt is to be resolved
- * @out_irq: structure of_irq filled by this function
- *
-@@ -15,7 +15,7 @@
- * PCI tree until an device-node is found, at which point it will finish
- * resolving using the OF tree walking.
- */
--int of_irq_map_pci(const struct pci_dev *pdev, struct of_irq *out_irq)
-+int of_irq_parse_pci(const struct pci_dev *pdev, struct of_irq *out_irq)
- {
- struct device_node *dn, *ppnode;
- struct pci_dev *ppdev;
-@@ -30,7 +30,7 @@ int of_irq_map_pci(const struct pci_dev
- */
- dn = pci_device_to_OF_node(pdev);
- if (dn) {
-- rc = of_irq_map_one(dn, 0, out_irq);
-+ rc = of_irq_parse_one(dn, 0, out_irq);
- if (!rc)
- return rc;
- }
-@@ -88,6 +88,6 @@ int of_irq_map_pci(const struct pci_dev
- lspec_be = cpu_to_be32(lspec);
- laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8));
- laddr[1] = laddr[2] = cpu_to_be32(0);
-- return of_irq_map_raw(ppnode, &lspec_be, 1, laddr, out_irq);
-+ return of_irq_parse_raw(ppnode, &lspec_be, 1, laddr, out_irq);
- }
--EXPORT_SYMBOL_GPL(of_irq_map_pci);
-+EXPORT_SYMBOL_GPL(of_irq_parse_pci);
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -652,7 +652,7 @@ static int __init mvebu_pcie_map_irq(con
- struct of_irq oirq;
- int ret;
-
-- ret = of_irq_map_pci(dev, &oirq);
-+ ret = of_irq_parse_pci(dev, &oirq);
- if (ret)
- return ret;
-
---- a/include/linux/of_irq.h
-+++ b/include/linux/of_irq.h
-@@ -35,12 +35,12 @@ typedef int (*of_irq_init_cb_t)(struct d
- #if defined(CONFIG_PPC32) && defined(CONFIG_PPC_PMAC)
- extern unsigned int of_irq_workarounds;
- extern struct device_node *of_irq_dflt_pic;
--extern int of_irq_map_oldworld(struct device_node *device, int index,
-+extern int of_irq_parse_oldworld(struct device_node *device, int index,
- struct of_irq *out_irq);
- #else /* CONFIG_PPC32 && CONFIG_PPC_PMAC */
- #define of_irq_workarounds (0)
- #define of_irq_dflt_pic (NULL)
--static inline int of_irq_map_oldworld(struct device_node *device, int index,
-+static inline int of_irq_parse_oldworld(struct device_node *device, int index,
- struct of_irq *out_irq)
- {
- return -EINVAL;
-@@ -48,10 +48,10 @@ static inline int of_irq_map_oldworld(st
- #endif /* CONFIG_PPC32 && CONFIG_PPC_PMAC */
-
-
--extern int of_irq_map_raw(struct device_node *parent, const __be32 *intspec,
-+extern int of_irq_parse_raw(struct device_node *parent, const __be32 *intspec,
- u32 ointsize, const __be32 *addr,
- struct of_irq *out_irq);
--extern int of_irq_map_one(struct device_node *device, int index,
-+extern int of_irq_parse_one(struct device_node *device, int index,
- struct of_irq *out_irq);
- extern unsigned int irq_create_of_mapping(struct device_node *controller,
- const u32 *intspec,
---- a/include/linux/of_pci.h
-+++ b/include/linux/of_pci.h
-@@ -6,7 +6,7 @@
-
- struct pci_dev;
- struct of_irq;
--int of_irq_map_pci(const struct pci_dev *pdev, struct of_irq *out_irq);
-+int of_irq_parse_pci(const struct pci_dev *pdev, struct of_irq *out_irq);
-
- struct device_node;
- struct device_node *of_pci_find_child_device(struct device_node *parent,
+++ /dev/null
-From 1baf727ee1d863a0eacd249cff6afc99022593c2 Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Thu, 19 Dec 2013 09:30:55 -0300
-Subject: [PATCH 184/203] of/irq: Replace of_irq with of_phandle_args
-
-struct of_irq and struct of_phandle_args are exactly the same structure.
-This patch makes the kernel use of_phandle_args everywhere. This in
-itself isn't a big deal, but it makes some follow-on patches simpler.
-
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
-Acked-by: Michal Simek <monstr@monstr.eu>
-Acked-by: Tony Lindgren <tony@atomide.com>
-Cc: Russell King <linux@arm.linux.org.uk>
-Cc: Ralf Baechle <ralf@linux-mips.org>
-Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
-Conflicts:
- arch/mips/pci/pci-rt3883.c
----
- arch/arm/mach-integrator/pci_v3.c | 5 ++---
- arch/microblaze/pci/pci-common.c | 9 ++++-----
- arch/mips/pci/fixup-lantiq.c | 5 ++---
- arch/powerpc/kernel/pci-common.c | 9 ++++-----
- arch/powerpc/platforms/cell/celleb_scc_pciex.c | 5 ++---
- arch/powerpc/platforms/cell/celleb_scc_sio.c | 5 ++---
- arch/powerpc/platforms/cell/spider-pic.c | 6 +++---
- arch/powerpc/platforms/cell/spu_manage.c | 12 ++++++------
- arch/powerpc/platforms/fsl_uli1575.c | 8 +++-----
- arch/powerpc/platforms/powermac/pic.c | 8 ++++----
- arch/powerpc/platforms/pseries/event_sources.c | 7 +++----
- arch/powerpc/sysdev/mpic_msi.c | 6 +++---
- arch/x86/kernel/devicetree.c | 5 ++---
- drivers/of/irq.c | 15 +++++++--------
- drivers/of/of_pci_irq.c | 2 +-
- drivers/pci/host/pci-mvebu.c | 5 ++---
- include/linux/of_irq.h | 24 ++++--------------------
- include/linux/of_pci.h | 4 ++--
- 18 files changed, 56 insertions(+), 84 deletions(-)
-
---- a/arch/arm/mach-integrator/pci_v3.c
-+++ b/arch/arm/mach-integrator/pci_v3.c
-@@ -684,7 +684,7 @@ static struct hw_pci pci_v3 __initdata =
-
- static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
- {
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
- int ret;
-
- ret = of_irq_parse_pci(dev, &oirq);
-@@ -694,8 +694,7 @@ static int __init pci_v3_map_irq_dt(cons
- return 0;
- }
-
-- return irq_create_of_mapping(oirq.controller, oirq.specifier,
-- oirq.size);
-+ return irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
- }
-
- static int __init pci_v3_dtprobe(struct platform_device *pdev,
---- a/arch/microblaze/pci/pci-common.c
-+++ b/arch/microblaze/pci/pci-common.c
-@@ -199,7 +199,7 @@ void pcibios_set_master(struct pci_dev *
- */
- int pci_read_irq_line(struct pci_dev *pci_dev)
- {
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
- unsigned int virq;
-
- /* The current device-tree that iSeries generates from the HV
-@@ -243,11 +243,10 @@ int pci_read_irq_line(struct pci_dev *pc
- irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
- } else {
- pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
-- oirq.size, oirq.specifier[0], oirq.specifier[1],
-- of_node_full_name(oirq.controller));
-+ oirq.args_count, oirq.args[0], oirq.args[1],
-+ of_node_full_name(oirq.np));
-
-- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
-- oirq.size);
-+ virq = irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
- }
- if (!virq) {
- pr_debug(" Failed to map !\n");
---- a/arch/mips/pci/fixup-lantiq.c
-+++ b/arch/mips/pci/fixup-lantiq.c
-@@ -25,7 +25,7 @@ int pcibios_plat_dev_init(struct pci_dev
-
- int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
- {
-- struct of_irq dev_irq;
-+ struct of_phandle_args dev_irq;
- int irq;
-
- if (of_irq_parse_pci(dev, &dev_irq)) {
-@@ -33,8 +33,7 @@ int __init pcibios_map_irq(const struct
- slot, pin);
- return 0;
- }
-- irq = irq_create_of_mapping(dev_irq.controller, dev_irq.specifier,
-- dev_irq.size);
-+ irq = irq_create_of_mapping(dev_irq.np, dev_irq.args, dev_irq.args_count);
- dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, irq);
- return irq;
- }
---- a/arch/powerpc/kernel/pci-common.c
-+++ b/arch/powerpc/kernel/pci-common.c
-@@ -228,7 +228,7 @@ int pcibios_add_platform_entries(struct
- */
- static int pci_read_irq_line(struct pci_dev *pci_dev)
- {
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
- unsigned int virq;
-
- pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
-@@ -263,11 +263,10 @@ static int pci_read_irq_line(struct pci_
- irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
- } else {
- pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
-- oirq.size, oirq.specifier[0], oirq.specifier[1],
-- of_node_full_name(oirq.controller));
-+ oirq.args_count, oirq.args[0], oirq.args[1],
-+ of_node_full_name(oirq.np));
-
-- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
-- oirq.size);
-+ virq = irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
- }
- if(virq == NO_IRQ) {
- pr_debug(" Failed to map !\n");
---- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
-+++ b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
-@@ -486,7 +486,7 @@ static __init int celleb_setup_pciex(str
- struct pci_controller *phb)
- {
- struct resource r;
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
- int virq;
-
- /* SMMIO registers; used inside this file */
-@@ -511,8 +511,7 @@ static __init int celleb_setup_pciex(str
- pr_err("PCIEXC:Failed to map irq\n");
- goto error;
- }
-- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
-- oirq.size);
-+ virq = irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
- if (request_irq(virq, pciex_handle_internal_irq,
- 0, "pciex", (void *)phb)) {
- pr_err("PCIEXC:Failed to request irq\n");
---- a/arch/powerpc/platforms/cell/celleb_scc_sio.c
-+++ b/arch/powerpc/platforms/cell/celleb_scc_sio.c
-@@ -45,7 +45,7 @@ static int __init txx9_serial_init(void)
- struct device_node *node;
- int i;
- struct uart_port req;
-- struct of_irq irq;
-+ struct of_phandle_args irq;
- struct resource res;
-
- for_each_compatible_node(node, "serial", "toshiba,sio-scc") {
-@@ -66,8 +66,7 @@ static int __init txx9_serial_init(void)
- #ifdef CONFIG_SERIAL_TXX9_CONSOLE
- req.membase = ioremap(req.mapbase, 0x24);
- #endif
-- req.irq = irq_create_of_mapping(irq.controller,
-- irq.specifier, irq.size);
-+ req.irq = irq_create_of_mapping(irq.np, irq.args, irq.args_count);
- req.flags |= UPF_IOREMAP | UPF_BUGGY_UART
- /*HAVE_CTS_LINE*/;
- req.uartclk = 83300000;
---- a/arch/powerpc/platforms/cell/spider-pic.c
-+++ b/arch/powerpc/platforms/cell/spider-pic.c
-@@ -235,10 +235,10 @@ static unsigned int __init spider_find_c
- /* First, we check whether we have a real "interrupts" in the device
- * tree in case the device-tree is ever fixed
- */
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
- if (of_irq_parse_one(pic->host->of_node, 0, &oirq) == 0) {
-- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
-- oirq.size);
-+ virq = irq_create_of_mapping(oirq.np, oirq.args,
-+ oirq.args_count);
- return virq;
- }
-
---- a/arch/powerpc/platforms/cell/spu_manage.c
-+++ b/arch/powerpc/platforms/cell/spu_manage.c
-@@ -177,7 +177,7 @@ out:
-
- static int __init spu_map_interrupts(struct spu *spu, struct device_node *np)
- {
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
- int ret;
- int i;
-
-@@ -188,10 +188,10 @@ static int __init spu_map_interrupts(str
- goto err;
- }
- ret = -EINVAL;
-- pr_debug(" irq %d no 0x%x on %s\n", i, oirq.specifier[0],
-- oirq.controller->full_name);
-- spu->irqs[i] = irq_create_of_mapping(oirq.controller,
-- oirq.specifier, oirq.size);
-+ pr_debug(" irq %d no 0x%x on %s\n", i, oirq.args[0],
-+ oirq.np->full_name);
-+ spu->irqs[i] = irq_create_of_mapping(oirq.np,
-+ oirq.args, oirq.args_count);
- if (spu->irqs[i] == NO_IRQ) {
- pr_debug("spu_new: failed to map it !\n");
- goto err;
-@@ -200,7 +200,7 @@ static int __init spu_map_interrupts(str
- return 0;
-
- err:
-- pr_debug("failed to map irq %x for spu %s\n", *oirq.specifier,
-+ pr_debug("failed to map irq %x for spu %s\n", *oirq.args,
- spu->name);
- for (; i >= 0; i--) {
- if (spu->irqs[i] != NO_IRQ)
---- a/arch/powerpc/platforms/fsl_uli1575.c
-+++ b/arch/powerpc/platforms/fsl_uli1575.c
-@@ -321,8 +321,8 @@ static void hpcd_final_uli5288(struct pc
- {
- struct pci_controller *hose = pci_bus_to_host(dev->bus);
- struct device_node *hosenode = hose ? hose->dn : NULL;
-- struct of_irq oirq;
-- int virq, pin = 2;
-+ struct of_phandle_args oirq;
-+ int pin = 2;
- u32 laddr[3];
-
- if (!machine_is(mpc86xx_hpcd))
-@@ -334,9 +334,7 @@ static void hpcd_final_uli5288(struct pc
- laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
- laddr[1] = laddr[2] = 0;
- of_irq_parse_raw(hosenode, &pin, 1, laddr, &oirq);
-- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
-- oirq.size);
-- dev->irq = virq;
-+ dev->irq = irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
- }
-
- DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575);
---- a/arch/powerpc/platforms/powermac/pic.c
-+++ b/arch/powerpc/platforms/powermac/pic.c
-@@ -394,7 +394,7 @@ static void __init pmac_pic_probe_oldsty
- }
-
- int of_irq_parse_oldworld(struct device_node *device, int index,
-- struct of_irq *out_irq)
-+ struct of_phandle_args *out_irq)
- {
- const u32 *ints = NULL;
- int intlen;
-@@ -422,9 +422,9 @@ int of_irq_parse_oldworld(struct device_
- if (index >= intlen)
- return -EINVAL;
-
-- out_irq->controller = NULL;
-- out_irq->specifier[0] = ints[index];
-- out_irq->size = 1;
-+ out_irq->np = NULL;
-+ out_irq->args[0] = ints[index];
-+ out_irq->args_count = 1;
-
- return 0;
- }
---- a/arch/powerpc/platforms/pseries/event_sources.c
-+++ b/arch/powerpc/platforms/pseries/event_sources.c
-@@ -25,7 +25,7 @@ void request_event_sources_irqs(struct d
- const char *name)
- {
- int i, index, count = 0;
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
- const u32 *opicprop;
- unsigned int opicplen;
- unsigned int virqs[16];
-@@ -59,9 +59,8 @@ void request_event_sources_irqs(struct d
- index++) {
- if (count > 15)
- break;
-- virqs[count] = irq_create_of_mapping(oirq.controller,
-- oirq.specifier,
-- oirq.size);
-+ virqs[count] = irq_create_of_mapping(oirq.np, oirq.args,
-+ oirq.args_count);
- if (virqs[count] == NO_IRQ) {
- pr_err("event-sources: Unable to allocate "
- "interrupt number for %s\n",
---- a/arch/powerpc/sysdev/mpic_msi.c
-+++ b/arch/powerpc/sysdev/mpic_msi.c
-@@ -35,7 +35,7 @@ static int mpic_msi_reserve_u3_hwirqs(st
- const struct irq_domain_ops *ops = mpic->irqhost->ops;
- struct device_node *np;
- int flags, index, i;
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
-
- pr_debug("mpic: found U3, guessing msi allocator setup\n");
-
-@@ -64,8 +64,8 @@ static int mpic_msi_reserve_u3_hwirqs(st
-
- index = 0;
- while (of_irq_parse_one(np, index++, &oirq) == 0) {
-- ops->xlate(mpic->irqhost, NULL, oirq.specifier,
-- oirq.size, &hwirq, &flags);
-+ ops->xlate(mpic->irqhost, NULL, oirq.args,
-+ oirq.args_count, &hwirq, &flags);
- msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, hwirq);
- }
- }
---- a/arch/x86/kernel/devicetree.c
-+++ b/arch/x86/kernel/devicetree.c
-@@ -106,7 +106,7 @@ struct device_node *pcibios_get_phb_of_n
-
- static int x86_of_pci_irq_enable(struct pci_dev *dev)
- {
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
- u32 virq;
- int ret;
- u8 pin;
-@@ -121,8 +121,7 @@ static int x86_of_pci_irq_enable(struct
- if (ret)
- return ret;
-
-- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
-- oirq.size);
-+ virq = irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
- if (virq == 0)
- return -EINVAL;
- dev->irq = virq;
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -36,13 +36,12 @@
- */
- unsigned int irq_of_parse_and_map(struct device_node *dev, int index)
- {
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
-
- if (of_irq_parse_one(dev, index, &oirq))
- return 0;
-
-- return irq_create_of_mapping(oirq.controller, oirq.specifier,
-- oirq.size);
-+ return irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
- }
- EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
-
-@@ -94,7 +93,7 @@ struct device_node *of_irq_find_parent(s
- * node exist for the parent.
- */
- int of_irq_parse_raw(struct device_node *parent, const __be32 *intspec,
-- u32 ointsize, const __be32 *addr, struct of_irq *out_irq)
-+ u32 ointsize, const __be32 *addr, struct of_phandle_args *out_irq)
- {
- struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL;
- const __be32 *tmp, *imap, *imask;
-@@ -156,10 +155,10 @@ int of_irq_parse_raw(struct device_node
- NULL) {
- pr_debug(" -> got it !\n");
- for (i = 0; i < intsize; i++)
-- out_irq->specifier[i] =
-+ out_irq->args[i] =
- of_read_number(intspec +i, 1);
-- out_irq->size = intsize;
-- out_irq->controller = ipar;
-+ out_irq->args_count = intsize;
-+ out_irq->np = ipar;
- of_node_put(old);
- return 0;
- }
-@@ -280,7 +279,7 @@ EXPORT_SYMBOL_GPL(of_irq_parse_raw);
- * This function resolves an interrupt, walking the tree, for a given
- * device-tree node. It's the high level pendant to of_irq_parse_raw().
- */
--int of_irq_parse_one(struct device_node *device, int index, struct of_irq *out_irq)
-+int of_irq_parse_one(struct device_node *device, int index, struct of_phandle_args *out_irq)
- {
- struct device_node *p;
- const __be32 *intspec, *tmp, *addr;
---- a/drivers/of/of_pci_irq.c
-+++ b/drivers/of/of_pci_irq.c
-@@ -15,7 +15,7 @@
- * PCI tree until an device-node is found, at which point it will finish
- * resolving using the OF tree walking.
- */
--int of_irq_parse_pci(const struct pci_dev *pdev, struct of_irq *out_irq)
-+int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
- {
- struct device_node *dn, *ppnode;
- struct pci_dev *ppdev;
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -649,15 +649,14 @@ static int __init mvebu_pcie_setup(int n
-
- static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
- {
-- struct of_irq oirq;
-+ struct of_phandle_args oirq;
- int ret;
-
- ret = of_irq_parse_pci(dev, &oirq);
- if (ret)
- return ret;
-
-- return irq_create_of_mapping(oirq.controller, oirq.specifier,
-- oirq.size);
-+ return irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
- }
-
- static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
---- a/include/linux/of_irq.h
-+++ b/include/linux/of_irq.h
-@@ -8,22 +8,6 @@
- #include <linux/ioport.h>
- #include <linux/of.h>
-
--/**
-- * of_irq - container for device_node/irq_specifier pair for an irq controller
-- * @controller: pointer to interrupt controller device tree node
-- * @size: size of interrupt specifier
-- * @specifier: array of cells @size long specifing the specific interrupt
-- *
-- * This structure is returned when an interrupt is mapped. The controller
-- * field needs to be put() after use
-- */
--#define OF_MAX_IRQ_SPEC 4 /* We handle specifiers of at most 4 cells */
--struct of_irq {
-- struct device_node *controller; /* Interrupt controller node */
-- u32 size; /* Specifier size */
-- u32 specifier[OF_MAX_IRQ_SPEC]; /* Specifier copy */
--};
--
- typedef int (*of_irq_init_cb_t)(struct device_node *, struct device_node *);
-
- /*
-@@ -36,12 +20,12 @@ typedef int (*of_irq_init_cb_t)(struct d
- extern unsigned int of_irq_workarounds;
- extern struct device_node *of_irq_dflt_pic;
- extern int of_irq_parse_oldworld(struct device_node *device, int index,
-- struct of_irq *out_irq);
-+ struct of_phandle_args *out_irq);
- #else /* CONFIG_PPC32 && CONFIG_PPC_PMAC */
- #define of_irq_workarounds (0)
- #define of_irq_dflt_pic (NULL)
- static inline int of_irq_parse_oldworld(struct device_node *device, int index,
-- struct of_irq *out_irq)
-+ struct of_phandle_args *out_irq)
- {
- return -EINVAL;
- }
-@@ -50,9 +34,9 @@ static inline int of_irq_parse_oldworld(
-
- extern int of_irq_parse_raw(struct device_node *parent, const __be32 *intspec,
- u32 ointsize, const __be32 *addr,
-- struct of_irq *out_irq);
-+ struct of_phandle_args *out_irq);
- extern int of_irq_parse_one(struct device_node *device, int index,
-- struct of_irq *out_irq);
-+ struct of_phandle_args *out_irq);
- extern unsigned int irq_create_of_mapping(struct device_node *controller,
- const u32 *intspec,
- unsigned int intsize);
---- a/include/linux/of_pci.h
-+++ b/include/linux/of_pci.h
-@@ -5,8 +5,8 @@
- #include <linux/msi.h>
-
- struct pci_dev;
--struct of_irq;
--int of_irq_parse_pci(const struct pci_dev *pdev, struct of_irq *out_irq);
-+struct of_phandle_args;
-+int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq);
-
- struct device_node;
- struct device_node *of_pci_find_child_device(struct device_node *parent,
+++ /dev/null
-From 5e69ff59f7e51ddfde0b31587beb9e40ea1c85bc Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Thu, 19 Dec 2013 09:30:56 -0300
-Subject: [PATCH 185/203] of/irq: simplify args to irq_create_of_mapping
-
-All the callers of irq_create_of_mapping() pass the contents of a struct
-of_phandle_args structure to the function. Since all the callers already
-have an of_phandle_args pointer, why not pass it directly to
-irq_create_of_mapping()?
-
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
-Acked-by: Michal Simek <monstr@monstr.eu>
-Acked-by: Tony Lindgren <tony@atomide.com>
-Cc: Thomas Gleixner <tglx@linutronix.de>
-Cc: Russell King <linux@arm.linux.org.uk>
-Cc: Ralf Baechle <ralf@linux-mips.org>
-Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-
-Conflicts:
- arch/mips/pci/pci-rt3883.c
- kernel/irq/irqdomain.c
----
- arch/arm/mach-integrator/pci_v3.c | 2 +-
- arch/microblaze/pci/pci-common.c | 2 +-
- arch/mips/pci/fixup-lantiq.c | 2 +-
- arch/powerpc/kernel/pci-common.c | 2 +-
- arch/powerpc/platforms/cell/celleb_scc_pciex.c | 2 +-
- arch/powerpc/platforms/cell/celleb_scc_sio.c | 2 +-
- arch/powerpc/platforms/cell/spider-pic.c | 7 ++-----
- arch/powerpc/platforms/cell/spu_manage.c | 3 +--
- arch/powerpc/platforms/fsl_uli1575.c | 2 +-
- arch/powerpc/platforms/pseries/event_sources.c | 3 +--
- arch/x86/kernel/devicetree.c | 2 +-
- drivers/of/irq.c | 2 +-
- drivers/pci/host/pci-mvebu.c | 2 +-
- include/linux/of_irq.h | 4 +---
- kernel/irq/irqdomain.c | 15 +++++++--------
- 15 files changed, 22 insertions(+), 30 deletions(-)
-
---- a/arch/arm/mach-integrator/pci_v3.c
-+++ b/arch/arm/mach-integrator/pci_v3.c
-@@ -694,7 +694,7 @@ static int __init pci_v3_map_irq_dt(cons
- return 0;
- }
-
-- return irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
-+ return irq_create_of_mapping(&oirq);
- }
-
- static int __init pci_v3_dtprobe(struct platform_device *pdev,
---- a/arch/microblaze/pci/pci-common.c
-+++ b/arch/microblaze/pci/pci-common.c
-@@ -246,7 +246,7 @@ int pci_read_irq_line(struct pci_dev *pc
- oirq.args_count, oirq.args[0], oirq.args[1],
- of_node_full_name(oirq.np));
-
-- virq = irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
-+ virq = irq_create_of_mapping(&oirq);
- }
- if (!virq) {
- pr_debug(" Failed to map !\n");
---- a/arch/mips/pci/fixup-lantiq.c
-+++ b/arch/mips/pci/fixup-lantiq.c
-@@ -33,7 +33,7 @@ int __init pcibios_map_irq(const struct
- slot, pin);
- return 0;
- }
-- irq = irq_create_of_mapping(dev_irq.np, dev_irq.args, dev_irq.args_count);
-+ irq = irq_create_of_mapping(&dev_irq);
- dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, irq);
- return irq;
- }
---- a/arch/powerpc/kernel/pci-common.c
-+++ b/arch/powerpc/kernel/pci-common.c
-@@ -266,7 +266,7 @@ static int pci_read_irq_line(struct pci_
- oirq.args_count, oirq.args[0], oirq.args[1],
- of_node_full_name(oirq.np));
-
-- virq = irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
-+ virq = irq_create_of_mapping(&oirq);
- }
- if(virq == NO_IRQ) {
- pr_debug(" Failed to map !\n");
---- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
-+++ b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
-@@ -511,7 +511,7 @@ static __init int celleb_setup_pciex(str
- pr_err("PCIEXC:Failed to map irq\n");
- goto error;
- }
-- virq = irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
-+ virq = irq_create_of_mapping(&oirq);
- if (request_irq(virq, pciex_handle_internal_irq,
- 0, "pciex", (void *)phb)) {
- pr_err("PCIEXC:Failed to request irq\n");
---- a/arch/powerpc/platforms/cell/celleb_scc_sio.c
-+++ b/arch/powerpc/platforms/cell/celleb_scc_sio.c
-@@ -66,7 +66,7 @@ static int __init txx9_serial_init(void)
- #ifdef CONFIG_SERIAL_TXX9_CONSOLE
- req.membase = ioremap(req.mapbase, 0x24);
- #endif
-- req.irq = irq_create_of_mapping(irq.np, irq.args, irq.args_count);
-+ req.irq = irq_create_of_mapping(&irq);
- req.flags |= UPF_IOREMAP | UPF_BUGGY_UART
- /*HAVE_CTS_LINE*/;
- req.uartclk = 83300000;
---- a/arch/powerpc/platforms/cell/spider-pic.c
-+++ b/arch/powerpc/platforms/cell/spider-pic.c
-@@ -236,11 +236,8 @@ static unsigned int __init spider_find_c
- * tree in case the device-tree is ever fixed
- */
- struct of_phandle_args oirq;
-- if (of_irq_parse_one(pic->host->of_node, 0, &oirq) == 0) {
-- virq = irq_create_of_mapping(oirq.np, oirq.args,
-- oirq.args_count);
-- return virq;
-- }
-+ if (of_irq_parse_one(pic->host->of_node, 0, &oirq) == 0)
-+ return irq_create_of_mapping(&oirq);
-
- /* Now do the horrible hacks */
- tmp = of_get_property(pic->host->of_node, "#interrupt-cells", NULL);
---- a/arch/powerpc/platforms/cell/spu_manage.c
-+++ b/arch/powerpc/platforms/cell/spu_manage.c
-@@ -190,8 +190,7 @@ static int __init spu_map_interrupts(str
- ret = -EINVAL;
- pr_debug(" irq %d no 0x%x on %s\n", i, oirq.args[0],
- oirq.np->full_name);
-- spu->irqs[i] = irq_create_of_mapping(oirq.np,
-- oirq.args, oirq.args_count);
-+ spu->irqs[i] = irq_create_of_mapping(&oirq);
- if (spu->irqs[i] == NO_IRQ) {
- pr_debug("spu_new: failed to map it !\n");
- goto err;
---- a/arch/powerpc/platforms/fsl_uli1575.c
-+++ b/arch/powerpc/platforms/fsl_uli1575.c
-@@ -334,7 +334,7 @@ static void hpcd_final_uli5288(struct pc
- laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
- laddr[1] = laddr[2] = 0;
- of_irq_parse_raw(hosenode, &pin, 1, laddr, &oirq);
-- dev->irq = irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
-+ dev->irq = irq_create_of_mapping(&oirq);
- }
-
- DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575);
---- a/arch/powerpc/platforms/pseries/event_sources.c
-+++ b/arch/powerpc/platforms/pseries/event_sources.c
-@@ -59,8 +59,7 @@ void request_event_sources_irqs(struct d
- index++) {
- if (count > 15)
- break;
-- virqs[count] = irq_create_of_mapping(oirq.np, oirq.args,
-- oirq.args_count);
-+ virqs[count] = irq_create_of_mapping(&oirq);
- if (virqs[count] == NO_IRQ) {
- pr_err("event-sources: Unable to allocate "
- "interrupt number for %s\n",
---- a/arch/x86/kernel/devicetree.c
-+++ b/arch/x86/kernel/devicetree.c
-@@ -121,7 +121,7 @@ static int x86_of_pci_irq_enable(struct
- if (ret)
- return ret;
-
-- virq = irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
-+ virq = irq_create_of_mapping(&oirq);
- if (virq == 0)
- return -EINVAL;
- dev->irq = virq;
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -41,7 +41,7 @@ unsigned int irq_of_parse_and_map(struct
- if (of_irq_parse_one(dev, index, &oirq))
- return 0;
-
-- return irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
-+ return irq_create_of_mapping(&oirq);
- }
- EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
-
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -656,7 +656,7 @@ static int __init mvebu_pcie_map_irq(con
- if (ret)
- return ret;
-
-- return irq_create_of_mapping(oirq.np, oirq.args, oirq.args_count);
-+ return irq_create_of_mapping(&oirq);
- }
-
- static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
---- a/include/linux/of_irq.h
-+++ b/include/linux/of_irq.h
-@@ -37,9 +37,7 @@ extern int of_irq_parse_raw(struct devic
- struct of_phandle_args *out_irq);
- extern int of_irq_parse_one(struct device_node *device, int index,
- struct of_phandle_args *out_irq);
--extern unsigned int irq_create_of_mapping(struct device_node *controller,
-- const u32 *intspec,
-- unsigned int intsize);
-+extern unsigned int irq_create_of_mapping(struct of_phandle_args *irq_data);
- extern int of_irq_to_resource(struct device_node *dev, int index,
- struct resource *r);
- extern int of_irq_count(struct device_node *dev);
---- a/kernel/irq/irqdomain.c
-+++ b/kernel/irq/irqdomain.c
-@@ -655,15 +655,14 @@ int irq_create_strict_mappings(struct ir
- }
- EXPORT_SYMBOL_GPL(irq_create_strict_mappings);
-
--unsigned int irq_create_of_mapping(struct device_node *controller,
-- const u32 *intspec, unsigned int intsize)
-+unsigned int irq_create_of_mapping(struct of_phandle_args *irq_data)
- {
- struct irq_domain *domain;
- irq_hw_number_t hwirq;
- unsigned int type = IRQ_TYPE_NONE;
- unsigned int virq;
-
-- domain = controller ? irq_find_host(controller) : irq_default_domain;
-+ domain = irq_data->np ? irq_find_host(irq_data->np) : irq_default_domain;
- if (!domain) {
- #ifdef CONFIG_MIPS
- /*
-@@ -677,17 +676,17 @@ unsigned int irq_create_of_mapping(struc
- if (intsize > 0)
- return intspec[0];
- #endif
-- pr_warning("no irq domain found for %s !\n",
-- of_node_full_name(controller));
-+ pr_warn("no irq domain found for %s !\n",
-+ of_node_full_name(irq_data->np));
- return 0;
- }
-
- /* If domain has no translation, then we assume interrupt line */
- if (domain->ops->xlate == NULL)
-- hwirq = intspec[0];
-+ hwirq = irq_data->args[0];
- else {
-- if (domain->ops->xlate(domain, controller, intspec, intsize,
-- &hwirq, &type))
-+ if (domain->ops->xlate(domain, irq_data->np, irq_data->args,
-+ irq_data->args_count, &hwirq, &type))
- return 0;
- }
-
+++ /dev/null
-From 44ad702902e9e274f57edce8944e46540b978f9a Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Thu, 19 Dec 2013 09:30:57 -0300
-Subject: [PATCH 186/203] of/irq: Refactor interrupt-map parsing
-
-All the users of of_irq_parse_raw pass in a raw interrupt specifier from
-the device tree and expect it to be returned (possibly modified) in an
-of_phandle_args structure. However, the primary function of
-of_irq_parse_raw() is to check for translations due to the presence of
-one or more interrupt-map properties. The actual placing of the data
-into an of_phandle_args structure is trivial. If it is refactored to
-accept an of_phandle_args structure directly, then it becomes possible
-to consume of_phandle_args from other sources. This is important for an
-upcoming patch that allows a device to be connected to more than one
-interrupt parent. It also simplifies the code a bit.
-
-The biggest complication with this patch is that the old version works
-on the interrupt specifiers in __be32 form, but the of_phandle_args
-structure is intended to carry it in the cpu-native version. A bit of
-churn was required to make this work. In the end it results in tighter
-code, so the churn is worth it.
-
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
-Acked-by: Tony Lindgren <tony@atomide.com>
-Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
----
- arch/powerpc/platforms/fsl_uli1575.c | 6 +-
- drivers/of/irq.c | 108 ++++++++++++++++++-----------------
- drivers/of/of_pci_irq.c | 7 ++-
- include/linux/of_irq.h | 5 +-
- 4 files changed, 67 insertions(+), 59 deletions(-)
-
---- a/arch/powerpc/platforms/fsl_uli1575.c
-+++ b/arch/powerpc/platforms/fsl_uli1575.c
-@@ -322,7 +322,6 @@ static void hpcd_final_uli5288(struct pc
- struct pci_controller *hose = pci_bus_to_host(dev->bus);
- struct device_node *hosenode = hose ? hose->dn : NULL;
- struct of_phandle_args oirq;
-- int pin = 2;
- u32 laddr[3];
-
- if (!machine_is(mpc86xx_hpcd))
-@@ -331,9 +330,12 @@ static void hpcd_final_uli5288(struct pc
- if (!hosenode)
- return;
-
-+ oirq.np = hosenode;
-+ oirq.args[0] = 2;
-+ oirq.args_count = 1;
- laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
- laddr[1] = laddr[2] = 0;
-- of_irq_parse_raw(hosenode, &pin, 1, laddr, &oirq);
-+ of_irq_parse_raw(laddr, &oirq);
- dev->irq = irq_create_of_mapping(&oirq);
- }
-
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -80,31 +80,32 @@ struct device_node *of_irq_find_parent(s
- /**
- * of_irq_parse_raw - Low level interrupt tree parsing
- * @parent: the device interrupt parent
-- * @intspec: interrupt specifier ("interrupts" property of the device)
-- * @ointsize: size of the passed in interrupt specifier
-- * @addr: address specifier (start of "reg" property of the device)
-- * @out_irq: structure of_irq filled by this function
-+ * @addr: address specifier (start of "reg" property of the device) in be32 format
-+ * @out_irq: structure of_irq updated by this function
- *
- * Returns 0 on success and a negative number on error
- *
- * This function is a low-level interrupt tree walking function. It
- * can be used to do a partial walk with synthetized reg and interrupts
- * properties, for example when resolving PCI interrupts when no device
-- * node exist for the parent.
-+ * node exist for the parent. It takes an interrupt specifier structure as
-+ * input, walks the tree looking for any interrupt-map properties, translates
-+ * the specifier for each map, and then returns the translated map.
- */
--int of_irq_parse_raw(struct device_node *parent, const __be32 *intspec,
-- u32 ointsize, const __be32 *addr, struct of_phandle_args *out_irq)
-+int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
- {
- struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL;
-- const __be32 *tmp, *imap, *imask;
-+ __be32 initial_match_array[8];
-+ const __be32 *match_array = initial_match_array;
-+ const __be32 *tmp, *imap, *imask, dummy_imask[] = { ~0, ~0, ~0, ~0, ~0 };
- u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0;
- int imaplen, match, i;
-
- pr_debug("of_irq_parse_raw: par=%s,intspec=[0x%08x 0x%08x...],ointsize=%d\n",
-- of_node_full_name(parent), be32_to_cpup(intspec),
-- be32_to_cpup(intspec + 1), ointsize);
-+ of_node_full_name(out_irq->np), out_irq->args[0], out_irq->args[1],
-+ out_irq->args_count);
-
-- ipar = of_node_get(parent);
-+ ipar = of_node_get(out_irq->np);
-
- /* First get the #interrupt-cells property of the current cursor
- * that tells us how to interpret the passed-in intspec. If there
-@@ -127,7 +128,7 @@ int of_irq_parse_raw(struct device_node
-
- pr_debug("of_irq_parse_raw: ipar=%s, size=%d\n", of_node_full_name(ipar), intsize);
-
-- if (ointsize != intsize)
-+ if (out_irq->args_count != intsize)
- return -EINVAL;
-
- /* Look for this #address-cells. We have to implement the old linux
-@@ -146,6 +147,21 @@ int of_irq_parse_raw(struct device_node
-
- pr_debug(" -> addrsize=%d\n", addrsize);
-
-+ /* If we were passed no "reg" property and we attempt to parse
-+ * an interrupt-map, then #address-cells must be 0.
-+ * Fail if it's not.
-+ */
-+ if (addr == NULL && addrsize != 0) {
-+ pr_debug(" -> no reg passed in when needed !\n");
-+ return -EINVAL;
-+ }
-+
-+ /* Precalculate the match array - this simplifies match loop */
-+ for (i = 0; i < addrsize; i++)
-+ initial_match_array[i] = addr[i];
-+ for (i = 0; i < intsize; i++)
-+ initial_match_array[addrsize + i] = cpu_to_be32(out_irq->args[i]);
-+
- /* Now start the actual "proper" walk of the interrupt tree */
- while (ipar != NULL) {
- /* Now check if cursor is an interrupt-controller and if it is
-@@ -154,11 +170,6 @@ int of_irq_parse_raw(struct device_node
- if (of_get_property(ipar, "interrupt-controller", NULL) !=
- NULL) {
- pr_debug(" -> got it !\n");
-- for (i = 0; i < intsize; i++)
-- out_irq->args[i] =
-- of_read_number(intspec +i, 1);
-- out_irq->args_count = intsize;
-- out_irq->np = ipar;
- of_node_put(old);
- return 0;
- }
-@@ -175,34 +186,16 @@ int of_irq_parse_raw(struct device_node
-
- /* Look for a mask */
- imask = of_get_property(ipar, "interrupt-map-mask", NULL);
--
-- /* If we were passed no "reg" property and we attempt to parse
-- * an interrupt-map, then #address-cells must be 0.
-- * Fail if it's not.
-- */
-- if (addr == NULL && addrsize != 0) {
-- pr_debug(" -> no reg passed in when needed !\n");
-- goto fail;
-- }
-+ if (!imask)
-+ imask = dummy_imask;
-
- /* Parse interrupt-map */
- match = 0;
- while (imaplen > (addrsize + intsize + 1) && !match) {
- /* Compare specifiers */
- match = 1;
-- for (i = 0; i < addrsize && match; ++i) {
-- __be32 mask = imask ? imask[i]
-- : cpu_to_be32(0xffffffffu);
-- match = ((addr[i] ^ imap[i]) & mask) == 0;
-- }
-- for (; i < (addrsize + intsize) && match; ++i) {
-- __be32 mask = imask ? imask[i]
-- : cpu_to_be32(0xffffffffu);
-- match =
-- ((intspec[i-addrsize] ^ imap[i]) & mask) == 0;
-- }
-- imap += addrsize + intsize;
-- imaplen -= addrsize + intsize;
-+ for (i = 0; i < (addrsize + intsize); i++, imaplen--)
-+ match = !((match_array[i] ^ *imap++) & imask[i]);
-
- pr_debug(" -> match=%d (imaplen=%d)\n", match, imaplen);
-
-@@ -247,12 +240,18 @@ int of_irq_parse_raw(struct device_node
- if (!match)
- goto fail;
-
-- of_node_put(old);
-- old = of_node_get(newpar);
-+ /*
-+ * Successfully parsed an interrrupt-map translation; copy new
-+ * interrupt specifier into the out_irq structure
-+ */
-+ of_node_put(out_irq->np);
-+ out_irq->np = of_node_get(newpar);
-+
-+ match_array = imap - newaddrsize - newintsize;
-+ for (i = 0; i < newintsize; i++)
-+ out_irq->args[i] = be32_to_cpup(imap - newintsize + i);
-+ out_irq->args_count = intsize = newintsize;
- addrsize = newaddrsize;
-- intsize = newintsize;
-- intspec = imap - intsize;
-- addr = intspec - addrsize;
-
- skiplevel:
- /* Iterate again with new parent */
-@@ -263,7 +262,7 @@ int of_irq_parse_raw(struct device_node
- }
- fail:
- of_node_put(ipar);
-- of_node_put(old);
-+ of_node_put(out_irq->np);
- of_node_put(newpar);
-
- return -EINVAL;
-@@ -276,15 +275,16 @@ EXPORT_SYMBOL_GPL(of_irq_parse_raw);
- * @index: index of the interrupt to resolve
- * @out_irq: structure of_irq filled by this function
- *
-- * This function resolves an interrupt, walking the tree, for a given
-- * device-tree node. It's the high level pendant to of_irq_parse_raw().
-+ * This function resolves an interrupt for a node by walking the interrupt tree,
-+ * finding which interrupt controller node it is attached to, and returning the
-+ * interrupt specifier that can be used to retrieve a Linux IRQ number.
- */
- int of_irq_parse_one(struct device_node *device, int index, struct of_phandle_args *out_irq)
- {
- struct device_node *p;
- const __be32 *intspec, *tmp, *addr;
- u32 intsize, intlen;
-- int res = -EINVAL;
-+ int i, res = -EINVAL;
-
- pr_debug("of_irq_parse_one: dev=%s, index=%d\n", of_node_full_name(device), index);
-
-@@ -326,9 +326,15 @@ int of_irq_parse_one(struct device_node
- if ((index + 1) * intsize > intlen)
- goto out;
-
-- /* Get new specifier and map it */
-- res = of_irq_parse_raw(p, intspec + index * intsize, intsize,
-- addr, out_irq);
-+ /* Copy intspec into irq structure */
-+ intspec += index * intsize;
-+ out_irq->np = p;
-+ out_irq->args_count = intsize;
-+ for (i = 0; i < intsize; i++)
-+ out_irq->args[i] = be32_to_cpup(intspec++);
-+
-+ /* Check if there are any interrupt-map translations to process */
-+ res = of_irq_parse_raw(addr, out_irq);
- out:
- of_node_put(p);
- return res;
---- a/drivers/of/of_pci_irq.c
-+++ b/drivers/of/of_pci_irq.c
-@@ -85,9 +85,12 @@ int of_irq_parse_pci(const struct pci_de
- pdev = ppdev;
- }
-
-+ out_irq->np = ppnode;
-+ out_irq->args_count = 1;
-+ out_irq->args[0] = lspec;
- lspec_be = cpu_to_be32(lspec);
- laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8));
-- laddr[1] = laddr[2] = cpu_to_be32(0);
-- return of_irq_parse_raw(ppnode, &lspec_be, 1, laddr, out_irq);
-+ laddr[1] = laddr[2] = cpu_to_be32(0);
-+ return of_irq_parse_raw(laddr, out_irq);
- }
- EXPORT_SYMBOL_GPL(of_irq_parse_pci);
---- a/include/linux/of_irq.h
-+++ b/include/linux/of_irq.h
-@@ -31,10 +31,7 @@ static inline int of_irq_parse_oldworld(
- }
- #endif /* CONFIG_PPC32 && CONFIG_PPC_PMAC */
-
--
--extern int of_irq_parse_raw(struct device_node *parent, const __be32 *intspec,
-- u32 ointsize, const __be32 *addr,
-- struct of_phandle_args *out_irq);
-+extern int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq);
- extern int of_irq_parse_one(struct device_node *device, int index,
- struct of_phandle_args *out_irq);
- extern unsigned int irq_create_of_mapping(struct of_phandle_args *irq_data);
+++ /dev/null
-From 061855025b6842debdf6ea2e8bfd86f50700e263 Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Thu, 19 Dec 2013 09:30:58 -0300
-Subject: [PATCH 187/203] of: Add helper for printing an of_phandle_args
- structure
-
-It is sometimes useful for debug to get the contents of an
-of_phandle_args structure out into the kernel log.
-
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
-
-Conflicts:
- drivers/of/base.c
----
- drivers/of/base.c | 9 +++++++++
- drivers/of/irq.c | 6 +++---
- include/linux/of.h | 1 +
- 3 files changed, 13 insertions(+), 3 deletions(-)
-
---- a/drivers/of/base.c
-+++ b/drivers/of/base.c
-@@ -1136,6 +1136,15 @@ EXPORT_SYMBOL(of_parse_phandle);
- * To get a device_node of the `node2' node you may call this:
- * of_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args);
- */
-+void of_print_phandle_args(const char *msg, const struct of_phandle_args *args)
-+{
-+ int i;
-+ printk("%s %s", msg, of_node_full_name(args->np));
-+ for (i = 0; i < args->args_count; i++)
-+ printk(i ? ",%08x" : ":%08x", args->args[i]);
-+ printk("\n");
-+}
-+
- static int __of_parse_phandle_with_args(const struct device_node *np,
- const char *list_name,
- const char *cells_name, int index,
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -101,9 +101,9 @@ int of_irq_parse_raw(const __be32 *addr,
- u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0;
- int imaplen, match, i;
-
-- pr_debug("of_irq_parse_raw: par=%s,intspec=[0x%08x 0x%08x...],ointsize=%d\n",
-- of_node_full_name(out_irq->np), out_irq->args[0], out_irq->args[1],
-- out_irq->args_count);
-+#ifdef DEBUG
-+ of_print_phandle_args("of_irq_parse_raw: ", out_irq);
-+#endif
-
- ipar = of_node_get(out_irq->np);
-
---- a/include/linux/of.h
-+++ b/include/linux/of.h
-@@ -274,6 +274,7 @@ extern int of_n_size_cells(struct device
- extern const struct of_device_id *of_match_node(
- const struct of_device_id *matches, const struct device_node *node);
- extern int of_modalias_node(struct device_node *node, char *modalias, int len);
-+extern void of_print_phandle_args(const char *msg, const struct of_phandle_args *args);
- extern struct device_node *of_parse_phandle(const struct device_node *np,
- const char *phandle_name,
- int index);
+++ /dev/null
-From 3665853921092bb68aa0929efb3a94ecdfc96782 Mon Sep 17 00:00:00 2001
-From: Thierry Reding <thierry.reding@gmail.com>
-Date: Thu, 19 Dec 2013 09:30:59 -0300
-Subject: [PATCH 188/203] of/irq: Rework of_irq_count()
-
-The of_irq_to_resource() helper that is used to implement of_irq_count()
-tries to resolve interrupts and in fact creates a mapping for resolved
-interrupts. That's pretty heavy lifting for something that claims to
-just return the number of interrupts requested by a given device node.
-
-Instead, use the more lightweight of_irq_map_one(), which, despite the
-name, doesn't create an actual mapping. Perhaps a better name would be
-of_irq_translate_one().
-
-Signed-off-by: Thierry Reding <treding@nvidia.com>
-Acked-by: Rob Herring <rob.herring@calxeda.com>
-[grant.likely: fixup s/of_irq_map_one/of_irq_parse_one/]
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
----
- drivers/of/irq.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -379,9 +379,10 @@ EXPORT_SYMBOL_GPL(of_irq_to_resource);
- */
- int of_irq_count(struct device_node *dev)
- {
-+ struct of_phandle_args irq;
- int nr = 0;
-
-- while (of_irq_to_resource(dev, nr, NULL))
-+ while (of_irq_parse_one(dev, nr, &irq) == 0)
- nr++;
-
- return nr;
+++ /dev/null
-From efd4032754a57bc258eafe30fde684ec47dc36e1 Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Thu, 19 Dec 2013 09:31:00 -0300
-Subject: [PATCH 189/203] of/irq: create interrupts-extended property
-
-The standard interrupts property in device tree can only handle
-interrupts coming from a single interrupt parent. If a device is wired
-to multiple interrupt controllers, then it needs to be attached to a
-node with an interrupt-map property to demux the interrupt specifiers
-which is confusing. It would be a lot easier if there was a form of the
-interrupts property that allows for a separate interrupt phandle for
-each interrupt specifier.
-
-This patch does exactly that by creating a new interrupts-extended
-property which reuses the phandle+arguments pattern used by GPIOs and
-other core bindings.
-
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
-Acked-by: Tony Lindgren <tony@atomide.com>
-Acked-by: Kumar Gala <galak@codeaurora.org>
-[grant.likely: removed versatile platform hunks into separate patch]
-Cc: Rob Herring <rob.herring@calxeda.com>
-
-Conflicts:
- arch/arm/boot/dts/testcases/tests-interrupts.dtsi
- drivers/of/selftest.c
----
- drivers/of/selftest.c | 146 +++++++++++++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 145 insertions(+), 1 deletion(-)
-
---- a/drivers/of/selftest.c
-+++ b/drivers/of/selftest.c
-@@ -154,6 +154,147 @@ static void __init of_selftest_property_
- selftest(rc == -EILSEQ, "unterminated string; rc=%i", rc);
- }
-
-+static void __init of_selftest_parse_interrupts(void)
-+{
-+ struct device_node *np;
-+ struct of_phandle_args args;
-+ int i, rc;
-+
-+ np = of_find_node_by_path("/testcase-data/interrupts/interrupts0");
-+ if (!np) {
-+ pr_err("missing testcase data\n");
-+ return;
-+ }
-+
-+ for (i = 0; i < 4; i++) {
-+ bool passed = true;
-+ args.args_count = 0;
-+ rc = of_irq_parse_one(np, i, &args);
-+
-+ passed &= !rc;
-+ passed &= (args.args_count == 1);
-+ passed &= (args.args[0] == (i + 1));
-+
-+ selftest(passed, "index %i - data error on node %s rc=%i\n",
-+ i, args.np->full_name, rc);
-+ }
-+ of_node_put(np);
-+
-+ np = of_find_node_by_path("/testcase-data/interrupts/interrupts1");
-+ if (!np) {
-+ pr_err("missing testcase data\n");
-+ return;
-+ }
-+
-+ for (i = 0; i < 4; i++) {
-+ bool passed = true;
-+ args.args_count = 0;
-+ rc = of_irq_parse_one(np, i, &args);
-+
-+ /* Test the values from tests-phandle.dtsi */
-+ switch (i) {
-+ case 0:
-+ passed &= !rc;
-+ passed &= (args.args_count == 1);
-+ passed &= (args.args[0] == 9);
-+ break;
-+ case 1:
-+ passed &= !rc;
-+ passed &= (args.args_count == 3);
-+ passed &= (args.args[0] == 10);
-+ passed &= (args.args[1] == 11);
-+ passed &= (args.args[2] == 12);
-+ break;
-+ case 2:
-+ passed &= !rc;
-+ passed &= (args.args_count == 2);
-+ passed &= (args.args[0] == 13);
-+ passed &= (args.args[1] == 14);
-+ break;
-+ case 3:
-+ passed &= !rc;
-+ passed &= (args.args_count == 2);
-+ passed &= (args.args[0] == 15);
-+ passed &= (args.args[1] == 16);
-+ break;
-+ default:
-+ passed = false;
-+ }
-+ selftest(passed, "index %i - data error on node %s rc=%i\n",
-+ i, args.np->full_name, rc);
-+ }
-+ of_node_put(np);
-+}
-+
-+static void __init of_selftest_parse_interrupts_extended(void)
-+{
-+ struct device_node *np;
-+ struct of_phandle_args args;
-+ int i, rc;
-+
-+ np = of_find_node_by_path("/testcase-data/interrupts/interrupts-extended0");
-+ if (!np) {
-+ pr_err("missing testcase data\n");
-+ return;
-+ }
-+
-+ for (i = 0; i < 7; i++) {
-+ bool passed = true;
-+ rc = of_irq_parse_one(np, i, &args);
-+
-+ /* Test the values from tests-phandle.dtsi */
-+ switch (i) {
-+ case 0:
-+ passed &= !rc;
-+ passed &= (args.args_count == 1);
-+ passed &= (args.args[0] == 1);
-+ break;
-+ case 1:
-+ passed &= !rc;
-+ passed &= (args.args_count == 3);
-+ passed &= (args.args[0] == 2);
-+ passed &= (args.args[1] == 3);
-+ passed &= (args.args[2] == 4);
-+ break;
-+ case 2:
-+ passed &= !rc;
-+ passed &= (args.args_count == 2);
-+ passed &= (args.args[0] == 5);
-+ passed &= (args.args[1] == 6);
-+ break;
-+ case 3:
-+ passed &= !rc;
-+ passed &= (args.args_count == 1);
-+ passed &= (args.args[0] == 9);
-+ break;
-+ case 4:
-+ passed &= !rc;
-+ passed &= (args.args_count == 3);
-+ passed &= (args.args[0] == 10);
-+ passed &= (args.args[1] == 11);
-+ passed &= (args.args[2] == 12);
-+ break;
-+ case 5:
-+ passed &= !rc;
-+ passed &= (args.args_count == 2);
-+ passed &= (args.args[0] == 13);
-+ passed &= (args.args[1] == 14);
-+ break;
-+ case 6:
-+ passed &= !rc;
-+ passed &= (args.args_count == 1);
-+ passed &= (args.args[0] == 15);
-+ break;
-+ default:
-+ passed = false;
-+ }
-+
-+ selftest(passed, "index %i - data error on node %s rc=%i\n",
-+ i, args.np->full_name, rc);
-+ }
-+ of_node_put(np);
-+}
-+
- static int __init of_selftest(void)
- {
- struct device_node *np;
-@@ -168,7 +309,10 @@ static int __init of_selftest(void)
- pr_info("start of selftest - you will see error messages\n");
- of_selftest_parse_phandle_with_args();
- of_selftest_property_match_string();
-- pr_info("end of selftest - %s\n", selftest_passed ? "PASS" : "FAIL");
-+ of_selftest_parse_interrupts();
-+ of_selftest_parse_interrupts_extended();
-+ pr_info("end of selftest - %i passed, %i failed\n",
-+ selftest_results.passed, selftest_results.failed);
- return 0;
- }
- late_initcall(of_selftest);
+++ /dev/null
-From 1c67d6e7cc30a856e79664e0be3a1f705bad56e4 Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Thu, 19 Dec 2013 09:31:01 -0300
-Subject: [PATCH 190/203] of/irq: Fix bug in interrupt parsing refactor.
-
-Commit 2361613206e6, "of/irq: Refactor interrupt-map parsing" introduced
-a bug. The irq parsing will fail for some nodes that don't have a reg
-property. It is fixed by deferring the check for reg until it is
-actually needed. Also adjust the testcase data to catch the bug.
-
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
-Tested-by: Stephen Warren <swarren@nvidia.com>
-Tested-by: Ming Lei <tom.leiming@gmail.com>
-Tested-by: Stephen Warren <swarren@nvidia.com>
-Cc: Rob Herring <rob.herring@calxeda.com>
-
-Conflicts:
- arch/arm/boot/dts/testcases/tests-interrupts.dtsi
----
- drivers/of/irq.c | 20 ++++++++++----------
- 1 file changed, 10 insertions(+), 10 deletions(-)
-
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -147,18 +147,9 @@ int of_irq_parse_raw(const __be32 *addr,
-
- pr_debug(" -> addrsize=%d\n", addrsize);
-
-- /* If we were passed no "reg" property and we attempt to parse
-- * an interrupt-map, then #address-cells must be 0.
-- * Fail if it's not.
-- */
-- if (addr == NULL && addrsize != 0) {
-- pr_debug(" -> no reg passed in when needed !\n");
-- return -EINVAL;
-- }
--
- /* Precalculate the match array - this simplifies match loop */
- for (i = 0; i < addrsize; i++)
-- initial_match_array[i] = addr[i];
-+ initial_match_array[i] = addr ? addr[i] : 0;
- for (i = 0; i < intsize; i++)
- initial_match_array[addrsize + i] = cpu_to_be32(out_irq->args[i]);
-
-@@ -174,6 +165,15 @@ int of_irq_parse_raw(const __be32 *addr,
- return 0;
- }
-
-+ /*
-+ * interrupt-map parsing does not work without a reg
-+ * property when #address-cells != 0
-+ */
-+ if (addrsize && !addr) {
-+ pr_debug(" -> no reg passed in when needed !\n");
-+ goto fail;
-+ }
-+
- /* Now look for an interrupt-map */
- imap = of_get_property(ipar, "interrupt-map", &imaplen);
- /* No interrupt map, check for an interrupt parent */
+++ /dev/null
-From 5a1bd82f089e19ba049a871a0d5538ed9eb5e5cd Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Thu, 19 Dec 2013 09:31:02 -0300
-Subject: [PATCH 191/203] of/irq: Fix potential buffer overflow
-
-Commit 2361613206e6, "of/irq: Refactor interrupt-map parsing" introduced
-a potential buffer overflow bug because it doesn't do sufficient range
-checking on the input data. This patch adds the appropriate checking and
-buffer size adjustments. If the bounds are out of range then warn
-loudly. MAX_PHANDLE_ARGS should be sufficient. If it is not then the
-value can be increased.
-
-Signed-off-by: Grant Likely <grant.likely@linaro.org>
-Cc: Rob Herring <rob.herring@calxeda.com>
----
- drivers/of/irq.c | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
-
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -95,9 +95,9 @@ struct device_node *of_irq_find_parent(s
- int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
- {
- struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL;
-- __be32 initial_match_array[8];
-+ __be32 initial_match_array[MAX_PHANDLE_ARGS];
- const __be32 *match_array = initial_match_array;
-- const __be32 *tmp, *imap, *imask, dummy_imask[] = { ~0, ~0, ~0, ~0, ~0 };
-+ const __be32 *tmp, *imap, *imask, dummy_imask[] = { [0 ... MAX_PHANDLE_ARGS] = ~0 };
- u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0;
- int imaplen, match, i;
-
-@@ -147,6 +147,10 @@ int of_irq_parse_raw(const __be32 *addr,
-
- pr_debug(" -> addrsize=%d\n", addrsize);
-
-+ /* Range check so that the temporary buffer doesn't overflow */
-+ if (WARN_ON(addrsize + intsize > MAX_PHANDLE_ARGS))
-+ goto fail;
-+
- /* Precalculate the match array - this simplifies match loop */
- for (i = 0; i < addrsize; i++)
- initial_match_array[i] = addr ? addr[i] : 0;
-@@ -229,6 +233,8 @@ int of_irq_parse_raw(const __be32 *addr,
- newintsize, newaddrsize);
-
- /* Check for malformed properties */
-+ if (WARN_ON(newaddrsize + newintsize > MAX_PHANDLE_ARGS))
-+ goto fail;
- if (imaplen < (newaddrsize + newintsize))
- goto fail;
-
+++ /dev/null
-From 8413f9010508998c62969827850a7434a1d5716c Mon Sep 17 00:00:00 2001
-From: Tomasz Figa <t.figa@samsung.com>
-Date: Thu, 19 Dec 2013 09:31:03 -0300
-Subject: [PATCH 192/203] of: irq: Fix interrupt-map entry matching
-
-This patch fixes interrupt-map entry matching code to properly match all
-specifier cells with interrupt map entries.
-
-Signed-off-by: Tomasz Figa <t.figa@samsung.com>
-Tested-by: Sachin Kamat <sachin.kamat@linaro.org>
-Signed-off-by: Rob Herring <rob.herring@calxeda.com>
----
- drivers/of/irq.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -199,7 +199,7 @@ int of_irq_parse_raw(const __be32 *addr,
- /* Compare specifiers */
- match = 1;
- for (i = 0; i < (addrsize + intsize); i++, imaplen--)
-- match = !((match_array[i] ^ *imap++) & imask[i]);
-+ match &= !((match_array[i] ^ *imap++) & imask[i]);
-
- pr_debug(" -> match=%d (imaplen=%d)\n", match, imaplen);
-
+++ /dev/null
-From ba47ab198541f6ed822b3c9691b392d83edba8b4 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 13 Aug 2013 11:43:14 -0300
-Subject: [PATCH 193/203] clocksource: armada-370-xp: Fix device-tree binding
-
-This commit fixes the DT binding for the Armada 370/XP SoC timer.
-The previous "marvell,armada-370-xp-timer" compatible is removed and
-two new compatible strings are introduced: "marvell,armada-xp-timer"
-and "marvell,armada-370-timer".
-
-The rationale behind this change is that the Armada 370 SoC and the
-Armada XP SoC timers are not really compatible:
-
- * Armada 370 has no 25 MHz fixed timer.
-
- * Armada XP cannot work properly without such 25 MHz fixed timer
- as doing otherwise leads to using a clocksource whose frequency
- varies when doing cpufreq frequency changes.
-
-This commit also removes the "marvell,timer-25Mhz" property, given
-it's now meaningless.
-
-Cc: devicetree@vger.kernel.org
-Acked-by: Jason Cooper <jason@lakedaemon.net>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- .../bindings/timer/marvell,armada-370-xp-timer.txt | 27 ++++++++++++++++++----
- 1 file changed, 22 insertions(+), 5 deletions(-)
-
---- a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
-+++ b/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
-@@ -2,14 +2,31 @@ Marvell Armada 370 and Armada XP Timers
- ---------------------------------------
-
- Required properties:
--- compatible: Should be "marvell,armada-370-xp-timer"
-+- compatible: Should be either "marvell,armada-370-timer" or
-+ "marvell,armada-xp-timer" as appropriate.
- - interrupts: Should contain the list of Global Timer interrupts and
- then local timer interrupts
- - reg: Should contain location and length for timers register. First
- pair for the Global Timer registers, second pair for the
- local/private timers.
--- clocks: clock driving the timer hardware
-+- clocks: clock driving the timer hardware, only required for
-+ "marvell,armada-370-timer";
-
--Optional properties:
--- marvell,timer-25Mhz: Tells whether the Global timer supports the 25
-- Mhz fixed mode (available on Armada XP and not on Armada 370)
-+Examples:
-+
-+- Armada 370:
-+
-+ timer {
-+ compatible = "marvell,armada-370-timer";
-+ reg = <0x20300 0x30>, <0x21040 0x30>;
-+ interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
-+ clocks = <&coreclk 2>;
-+ };
-+
-+- Armada XP:
-+
-+ timer {
-+ compatible = "marvell,armada-xp-timer";
-+ reg = <0x20300 0x30>, <0x21040 0x30>;
-+ interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
-+ };
+++ /dev/null
-From d569707433b26bb70f6b595a480bcfb3043a614c Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Tue, 20 Aug 2013 12:45:54 -0300
-Subject: [PATCH 194/203] clocksource: armada-370-xp: Add detailed clock
- requirements in devicetree binding
-
-Specifies the required clock inputs for each supported compatible.
-Armada 370 requires a single clock phandle, and Armada XP requires
-two clock phandles with clock-names "nbclk" and "fixed".
-
-Cc: devicetree@vger.kernel.org
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Acked-by: Jason Cooper <jason@lakedaemon.net>
-Acked-by: Stephen Warren <swarren@nvidia.com>
-Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
----
- .../bindings/timer/marvell,armada-370-xp-timer.txt | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
---- a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
-+++ b/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
-@@ -9,8 +9,15 @@ Required properties:
- - reg: Should contain location and length for timers register. First
- pair for the Global Timer registers, second pair for the
- local/private timers.
--- clocks: clock driving the timer hardware, only required for
-- "marvell,armada-370-timer";
-+
-+Clocks required for compatible = "marvell,armada-370-timer":
-+- clocks : Must contain a single entry describing the clock input
-+
-+Clocks required for compatible = "marvell,armada-xp-timer":
-+- clocks : Must contain an entry for each entry in clock-names.
-+- clock-names : Must include the following entries:
-+ "nbclk" (L2/coherency fabric clock),
-+ "fixed" (Reference 25 MHz fixed-clock).
-
- Examples:
-
-@@ -29,4 +36,6 @@ Examples:
- compatible = "marvell,armada-xp-timer";
- reg = <0x20300 0x30>, <0x21040 0x30>;
- interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
-+ clocks = <&coreclk 2>, <&refclk>;
-+ clock-names = "nbclk", "fixed";
- };
+++ /dev/null
-From 956b857c1fc80164859adbe1147704b1f352e153 Mon Sep 17 00:00:00 2001
-From: Al Cooper <alcooperx@gmail.com>
-Date: Fri, 6 Dec 2013 00:18:25 +0100
-Subject: [PATCH 195/203] usb: Add Device Tree support to XHCI Platform driver
-
-Add Device Tree match table to xhci-plat.c. Add DT bindings document.
-
-Signed-off-by: Al Cooper <alcooperx@gmail.com>
-Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
-Cc: Felipe Balbi <balbi@ti.com>
-Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
-
-Conflicts:
- drivers/usb/host/xhci-plat.c
----
- Documentation/devicetree/bindings/usb/usb-xhci.txt | 14 ++++++++++++++
- drivers/usb/host/xhci-plat.c | 10 ++++++++++
- 2 files changed, 24 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/usb/usb-xhci.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
-@@ -0,0 +1,14 @@
-+USB xHCI controllers
-+
-+Required properties:
-+ - compatible: should be "xhci-platform".
-+ - reg: should contain address and length of the standard XHCI
-+ register set for the device.
-+ - interrupts: one XHCI interrupt should be described here.
-+
-+Example:
-+ usb@f0931000 {
-+ compatible = "xhci-platform";
-+ reg = <0xf0931000 0x8c8>;
-+ interrupts = <0x0 0x4e 0x0>;
-+ };
---- a/drivers/usb/host/xhci-plat.c
-+++ b/drivers/usb/host/xhci-plat.c
-@@ -14,6 +14,7 @@
- #include <linux/platform_device.h>
- #include <linux/module.h>
- #include <linux/slab.h>
-+#include <linux/of.h>
-
- #include "xhci.h"
-
-@@ -186,11 +187,20 @@ static int xhci_plat_remove(struct platf
- return 0;
- }
-
-+#ifdef CONFIG_OF
-+static const struct of_device_id usb_xhci_of_match[] = {
-+ { .compatible = "xhci-platform" },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, usb_xhci_of_match);
-+#endif
-+
- static struct platform_driver usb_xhci_driver = {
- .probe = xhci_plat_probe,
- .remove = xhci_plat_remove,
- .driver = {
- .name = "xhci-hcd",
-+ .of_match_table = of_match_ptr(usb_xhci_of_match),
- },
- };
- MODULE_ALIAS("platform:xhci-hcd");
+++ /dev/null
-From 5cb802766e9cdc9a56e8ce8e4686692ebbcfb5cc Mon Sep 17 00:00:00 2001
-From: Xenia Ragiadakou <burzalodowa@gmail.com>
-Date: Mon, 23 Dec 2013 16:59:02 +0100
-Subject: [PATCH 197/203] xhci: fix dma mask setup in xhci.c
-
-The function dma_set_mask() tests internally whether the dma_mask pointer
-for the device is initialized and fails if the dma_mask pointer is NULL.
-On pci platforms, the device dma_mask pointer is initialized, when pci
-devices are enumerated, to point to the pci_dev->dma_mask which is 0xffffffff.
-However, for non-pci platforms, the dma_mask pointer may not be initialized
-and in that case dma_set_mask() will fail.
-
-This patch initializes the dma_mask and the coherent_dma_mask to 32bits
-in xhci_plat_probe(), before the call to usb_create_hcd() that sets the
-"uses_dma" flag for the usb bus and the call to usb_add_hcd() that creates
-coherent dma pools for the usb hcd.
-
-Moreover, a call to dma_set_mask() does not set the device coherent_dma_mask.
-Since the xhci-hcd driver calls dma_alloc_coherent() and dma_pool_alloc()
-to allocate consistent DMA memory blocks, the coherent DMA address mask
-has to be set explicitly.
-
-This patch sets the coherent_dma_mask to 64bits in xhci_gen_setup() when
-the xHC is capable for 64-bit DMA addressing.
-
-If dma_set_mask() succeeds, for a given bitmask, it is guaranteed that
-the given bitmask is also supported for consistent DMA mappings.
-
-Other changes introduced in this patch are:
-
-- The return value of dma_set_mask() is checked to ensure that the required
- dma bitmask conforms with the host system's addressing capabilities.
-
-- The dma_mask setup code for the non-primary hcd was removed since both
- primary and non-primary hcd refer to the same generic device whose
- dma_mask and coherent_dma_mask are already set during the setup of
- the primary hcd.
-
-- The code for reading the HCCPARAMS register to find out the addressing
- capabilities of xHC was removed since its value is already cached in
- xhci->hccparams.
-
-- hcd->self.controller was replaced with the dev variable since it is
- already available.
-
-Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com>
-Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
-
-Conflicts:
- drivers/usb/host/xhci-plat.c
----
- drivers/usb/host/xhci-plat.c | 10 ++++++++++
- drivers/usb/host/xhci.c | 19 +++++--------------
- 2 files changed, 15 insertions(+), 14 deletions(-)
-
---- a/drivers/usb/host/xhci-plat.c
-+++ b/drivers/usb/host/xhci-plat.c
-@@ -15,6 +15,7 @@
- #include <linux/module.h>
- #include <linux/slab.h>
- #include <linux/of.h>
-+#include <linux/dma-mapping.h>
-
- #include "xhci.h"
-
-@@ -105,6 +106,15 @@ static int xhci_plat_probe(struct platfo
- if (!res)
- return -ENODEV;
-
-+ /* Initialize dma_mask and coherent_dma_mask to 32-bits */
-+ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
-+ if (ret)
-+ return ret;
-+ if (!pdev->dev.dma_mask)
-+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
-+ else
-+ dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
-+
- hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
- if (!hcd)
- return -ENOMEM;
---- a/drivers/usb/host/xhci.c
-+++ b/drivers/usb/host/xhci.c
-@@ -4657,7 +4657,6 @@ int xhci_gen_setup(struct usb_hcd *hcd,
- struct xhci_hcd *xhci;
- struct device *dev = hcd->self.controller;
- int retval;
-- u32 temp;
-
- /* Accept arbitrarily long scatter-gather lists */
- hcd->self.sg_tablesize = ~0;
-@@ -4685,14 +4684,6 @@ int xhci_gen_setup(struct usb_hcd *hcd,
- /* xHCI private pointer was set in xhci_pci_probe for the second
- * registered roothub.
- */
-- xhci = hcd_to_xhci(hcd);
-- temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
-- if (HCC_64BIT_ADDR(temp)) {
-- xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
-- dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
-- } else {
-- dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
-- }
- return 0;
- }
-
-@@ -4731,12 +4722,12 @@ int xhci_gen_setup(struct usb_hcd *hcd,
- goto error;
- xhci_dbg(xhci, "Reset complete\n");
-
-- temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
-- if (HCC_64BIT_ADDR(temp)) {
-+ /* Set dma_mask and coherent_dma_mask to 64-bits,
-+ * if xHC supports 64-bit addressing */
-+ if (HCC_64BIT_ADDR(xhci->hcc_params) &&
-+ !dma_set_mask(dev, DMA_BIT_MASK(64))) {
- xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
-- dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
-- } else {
-- dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
-+ dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
- }
-
- xhci_dbg(xhci, "Calling HCD init\n");
+++ /dev/null
-From 39623dc5cb8814223e9580e22e78dfab10d91783 Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@linaro.org>
-Date: Tue, 24 Dec 2013 11:36:02 +0100
-Subject: [PATCH 198/203] of: Add testcases for interrupt parsing
-
-This patch extends the DT selftest code with some test cases for the
-interrupt parsing functions.
-
-Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
----
- arch/arm/boot/dts/testcases/tests-interrupts.dtsi | 41 +++++++++++++++++++++++
- arch/arm/boot/dts/testcases/tests.dtsi | 1 +
- drivers/of/selftest.c | 15 ++++++---
- 3 files changed, 52 insertions(+), 5 deletions(-)
- create mode 100644 arch/arm/boot/dts/testcases/tests-interrupts.dtsi
-
---- /dev/null
-+++ b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi
-@@ -0,0 +1,41 @@
-+
-+/ {
-+ testcase-data {
-+ interrupts {
-+ #address-cells = <0>;
-+ test_intc0: intc0 {
-+ interrupt-controller;
-+ #interrupt-cells = <1>;
-+ };
-+
-+ test_intc1: intc1 {
-+ interrupt-controller;
-+ #interrupt-cells = <3>;
-+ };
-+
-+ test_intc2: intc2 {
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ test_intmap0: intmap0 {
-+ #interrupt-cells = <1>;
-+ #address-cells = <0>;
-+ interrupt-map = <1 &test_intc0 9>,
-+ <2 &test_intc1 10 11 12>,
-+ <3 &test_intc2 13 14>,
-+ <4 &test_intc2 15 16>;
-+ };
-+
-+ interrupts0 {
-+ interrupt-parent = <&test_intc0>;
-+ interrupts = <1>, <2>, <3>, <4>;
-+ };
-+
-+ interrupts1 {
-+ interrupt-parent = <&test_intmap0>;
-+ interrupts = <1>, <2>, <3>, <4>;
-+ };
-+ };
-+ };
-+};
---- a/arch/arm/boot/dts/testcases/tests.dtsi
-+++ b/arch/arm/boot/dts/testcases/tests.dtsi
-@@ -1 +1,2 @@
- /include/ "tests-phandle.dtsi"
-+/include/ "tests-interrupts.dtsi"
---- a/drivers/of/selftest.c
-+++ b/drivers/of/selftest.c
-@@ -9,18 +9,24 @@
- #include <linux/errno.h>
- #include <linux/module.h>
- #include <linux/of.h>
-+#include <linux/of_irq.h>
- #include <linux/list.h>
- #include <linux/mutex.h>
- #include <linux/slab.h>
- #include <linux/device.h>
-
--static bool selftest_passed = true;
-+static struct selftest_results {
-+ int passed;
-+ int failed;
-+} selftest_results;
-+
- #define selftest(result, fmt, ...) { \
- if (!(result)) { \
-- pr_err("FAIL %s:%i " fmt, __FILE__, __LINE__, ##__VA_ARGS__); \
-- selftest_passed = false; \
-+ selftest_results.failed++; \
-+ pr_err("FAIL %s():%i " fmt, __func__, __LINE__, ##__VA_ARGS__); \
- } else { \
-- pr_info("pass %s:%i\n", __FILE__, __LINE__); \
-+ selftest_results.passed++; \
-+ pr_debug("pass %s():%i\n", __func__, __LINE__); \
- } \
- }
-
-@@ -131,7 +137,6 @@ static void __init of_selftest_property_
- struct device_node *np;
- int rc;
-
-- pr_info("start\n");
- np = of_find_node_by_path("/testcase-data/phandle-tests/consumer-a");
- if (!np) {
- pr_err("No testcase data in device tree\n");
+++ /dev/null
-From 508e3a33ebe14ae4444a45b3f65dff5d5e6a4c73 Mon Sep 17 00:00:00 2001
-From: Tushar Behera <tushar.behera@linaro.org>
-Date: Mon, 17 Jun 2013 14:46:13 +0530
-Subject: [PATCH 199/203] PCI: mvebu: Convert to use devm_ioremap_resource
-
-Commit 75096579c3ac ("lib: devres: Introduce devm_ioremap_resource()")
-introduced devm_ioremap_resource() and deprecated the use of
-devm_request_and_ioremap().
-
-While at it, modify mvebu_pcie_map_registers() to propagate error code.
-
-Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
----
- drivers/pci/host/pci-mvebu.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -736,9 +736,9 @@ mvebu_pcie_map_registers(struct platform
-
- ret = of_address_to_resource(np, 0, ®s);
- if (ret)
-- return NULL;
-+ return ERR_PTR(ret);
-
-- return devm_request_and_ioremap(&pdev->dev, ®s);
-+ return devm_ioremap_resource(&pdev->dev, ®s);
- }
-
- static void __init mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
-@@ -897,9 +897,10 @@ static int __init mvebu_pcie_probe(struc
- }
-
- port->base = mvebu_pcie_map_registers(pdev, child, port);
-- if (!port->base) {
-+ if (IS_ERR(port->base)) {
- dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
- port->port, port->lane);
-+ port->base = NULL;
- continue;
- }
-
+++ /dev/null
-From c524c5790d413b37702013e7e83a845fd3f007ac Mon Sep 17 00:00:00 2001
-From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-Date: Tue, 13 Aug 2013 14:25:20 +0200
-Subject: [PATCH 200/203] PCI: mvebu: move clock enable before register access
-
-The clock passed to PCI controller found on MVEBU SoCs may come from a
-clock gate. This requires the clock to be enabled before any registers
-are accessed. Therefore, move the clock enable before register iomap to
-ensure it is enabled.
-
-Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- drivers/pci/host/pci-mvebu.c | 25 ++++++++++++-------------
- 1 file changed, 12 insertions(+), 13 deletions(-)
-
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -896,11 +896,23 @@ static int __init mvebu_pcie_probe(struc
- continue;
- }
-
-+ port->clk = of_clk_get_by_name(child, NULL);
-+ if (IS_ERR(port->clk)) {
-+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
-+ port->port, port->lane);
-+ continue;
-+ }
-+
-+ ret = clk_prepare_enable(port->clk);
-+ if (ret)
-+ continue;
-+
- port->base = mvebu_pcie_map_registers(pdev, child, port);
- if (IS_ERR(port->base)) {
- dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
- port->port, port->lane);
- port->base = NULL;
-+ clk_disable_unprepare(port->clk);
- continue;
- }
-
-@@ -916,22 +928,9 @@ static int __init mvebu_pcie_probe(struc
- port->port, port->lane);
- }
-
-- port->clk = of_clk_get_by_name(child, NULL);
-- if (!port->clk) {
-- dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
-- port->port, port->lane);
-- iounmap(port->base);
-- port->haslink = 0;
-- continue;
-- }
--
- port->dn = child;
--
-- clk_prepare_enable(port->clk);
- spin_lock_init(&port->conf_lock);
--
- mvebu_sw_pci_bridge_init(port);
--
- i++;
- }
-
+++ /dev/null
-From e619fe9eb65d8064739f16eca2015145ac920f13 Mon Sep 17 00:00:00 2001
-From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-Date: Tue, 13 Aug 2013 14:25:21 +0200
-Subject: [PATCH 201/203] PCI: mvebu: increment nports only for registered
- ports
-
-The number of ports is probed by counting the number of available child nodes.
-Later on, the registration of a port can fail and cause a mismatch between
-the ->nports counter and registered ports. This patch modifies the counting
-strategy, to make ->nports represent the number of registered ports instead
-of the number of available childs.
-
-Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- drivers/pci/host/pci-mvebu.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/drivers/pci/host/pci-mvebu.c
-+++ b/drivers/pci/host/pci-mvebu.c
-@@ -841,13 +841,14 @@ static int __init mvebu_pcie_probe(struc
- return ret;
- }
-
-+ i = 0;
- for_each_child_of_node(pdev->dev.of_node, child) {
- if (!of_device_is_available(child))
- continue;
-- pcie->nports++;
-+ i++;
- }
-
-- pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
-+ pcie->ports = devm_kzalloc(&pdev->dev, i *
- sizeof(struct mvebu_pcie_port),
- GFP_KERNEL);
- if (!pcie->ports)
-@@ -934,8 +935,8 @@ static int __init mvebu_pcie_probe(struc
- i++;
- }
-
-+ pcie->nports = i;
- mvebu_pcie_msi_enable(pcie);
--
- mvebu_pcie_enable(pcie);
-
- return 0;
+++ /dev/null
-From b2ea44bd7bca49fe5696857327a1d1514edd1196 Mon Sep 17 00:00:00 2001
-From: Arnaud Ebalard <arno@natisbad.org>
-Date: Tue, 5 Nov 2013 21:45:48 +0100
-Subject: [PATCH 202/203] ARM: mvebu: second PCIe unit of Armada XP mv78230 is
- only x1 capable
-
-Various Marvell datasheets advertise second PCIe unit of mv78230
-flavour of Armada XP as x4/quad x1 capable. This second unit is in
-fact only x1 capable. This patch fixes current mv78230 .dtsi to
-reflect that, i.e. makes 1.0 the second interface (instead of 2.0
-at the moment). This was successfully tested on a mv78230-based
-ReadyNAS 2120 platform with a x1 device (FL1009 XHCI controller)
-connected to this second interface.
-
-Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
-Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Cc: <stable@vger.kernel.org> # v3.10.x
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 24 ++++++++++++------------
- 1 file changed, 12 insertions(+), 12 deletions(-)
-
---- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-@@ -47,7 +47,7 @@
- /*
- * MV78230 has 2 PCIe units Gen2.0: One unit can be
- * configured as x4 or quad x1 lanes. One unit is
-- * x4/x1.
-+ * x1 only.
- */
- pcie-controller {
- compatible = "marvell,armada-xp-pcie";
-@@ -62,10 +62,10 @@
-
- ranges =
- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
-- 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
- 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
-+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
- 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
-@@ -74,8 +74,8 @@
- 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
- 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
- 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
-- 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
-- 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
-+ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
-+ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
-
- pcie@1,0 {
- device_type = "pci";
-@@ -145,20 +145,20 @@
- status = "disabled";
- };
-
-- pcie@9,0 {
-+ pcie@5,0 {
- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-- reg = <0x4800 0 0 0 0>;
-+ assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
-+ reg = <0x2800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
-- 0x81000000 0 0 0x81000000 0x9 0 1 0>;
-+ ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
-+ 0x81000000 0 0 0x81000000 0x5 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 99>;
-- marvell,pcie-port = <2>;
-+ interrupt-map = <0 0 0 0 &mpic 62>;
-+ marvell,pcie-port = <1>;
- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 26>;
-+ clocks = <&gateclk 9>;
- status = "disabled";
- };
- };
+++ /dev/null
-From 9c2caf4d2d60780182d7754896c41496192b99c2 Mon Sep 17 00:00:00 2001
-From: Arnaud Ebalard <arno@natisbad.org>
-Date: Tue, 5 Nov 2013 21:46:02 +0100
-Subject: [PATCH 203/203] ARM: mvebu: fix second and third PCIe unit of Armada
- XP mv78260
-
-mv78260 flavour of Marvell Armada XP SoC has 3 PCIe units. The
-two first units are both x4 and quad x1 capable. The third unit
-is only x4 capable. This patch fixes mv78260 .dtsi to reflect
-those capabilities.
-
-Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
-Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Cc: <stable@vger.kernel.org> # v3.10.x
-Signed-off-by: Jason Cooper <jason@lakedaemon.net>
----
- arch/arm/boot/dts/armada-xp-mv78260.dtsi | 109 ++++++++++++++++++++++++-------
- 1 file changed, 85 insertions(+), 24 deletions(-)
-
---- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
-@@ -48,7 +48,7 @@
- /*
- * MV78260 has 3 PCIe units Gen2.0: Two units can be
- * configured as x4 or quad x1 lanes. One unit is
-- * x4/x1.
-+ * x4 only.
- */
- pcie-controller {
- compatible = "marvell,armada-xp-pcie";
-@@ -68,7 +68,9 @@
- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
- 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
- 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
-- 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
-+ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
-+ 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
-+ 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
- 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
-@@ -77,10 +79,18 @@
- 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
- 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
- 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
-- 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
-- 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
-- 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
-- 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
-+
-+ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
-+ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
-+ 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
-+ 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
-+ 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
-+ 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
-+ 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
-+ 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
-+
-+ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
-+ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
-
- pcie@1,0 {
- device_type = "pci";
-@@ -106,8 +116,8 @@
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
-- 0x81000000 0 0 0x81000000 0x2 0 1 0>;
-+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
-+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
- marvell,pcie-port = <0>;
-@@ -150,37 +160,88 @@
- status = "disabled";
- };
-
-- pcie@9,0 {
-+ pcie@5,0 {
- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-- reg = <0x4800 0 0 0 0>;
-+ assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
-+ reg = <0x2800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
-- 0x81000000 0 0 0x81000000 0x9 0 1 0>;
-+ ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
-+ 0x81000000 0 0 0x81000000 0x5 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 99>;
-- marvell,pcie-port = <2>;
-+ interrupt-map = <0 0 0 0 &mpic 62>;
-+ marvell,pcie-port = <1>;
- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 26>;
-+ clocks = <&gateclk 9>;
- status = "disabled";
- };
-
-- pcie@10,0 {
-+ pcie@6,0 {
- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
-- reg = <0x5000 0 0 0 0>;
-+ assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
-+ reg = <0x3000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
-- 0x81000000 0 0 0x81000000 0xa 0 1 0>;
-+ ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
-+ 0x81000000 0 0 0x81000000 0x6 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
-- interrupt-map = <0 0 0 0 &mpic 103>;
-- marvell,pcie-port = <3>;
-+ interrupt-map = <0 0 0 0 &mpic 63>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <1>;
-+ clocks = <&gateclk 10>;
-+ status = "disabled";
-+ };
-+
-+ pcie@7,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
-+ reg = <0x3800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
-+ 0x81000000 0 0 0x81000000 0x7 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 64>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <2>;
-+ clocks = <&gateclk 11>;
-+ status = "disabled";
-+ };
-+
-+ pcie@8,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
-+ reg = <0x4000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
-+ 0x81000000 0 0 0x81000000 0x8 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 65>;
-+ marvell,pcie-port = <1>;
-+ marvell,pcie-lane = <3>;
-+ clocks = <&gateclk 12>;
-+ status = "disabled";
-+ };
-+
-+ pcie@9,0 {
-+ device_type = "pci";
-+ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-+ reg = <0x4800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
-+ 0x81000000 0 0 0x81000000 0x9 0 1 0>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0 0 0 0 &mpic 99>;
-+ marvell,pcie-port = <2>;
- marvell,pcie-lane = <0>;
-- clocks = <&gateclk 27>;
-+ clocks = <&gateclk 26>;
- status = "disabled";
- };
- };
+++ /dev/null
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -94,6 +94,7 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.d
- dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
- armada-370-mirabox.dtb \
- armada-370-rd.dtb \
-+ armada-xp-mamba.dtb \
- armada-xp-db.dtb \
- armada-xp-gp.dtb \
- armada-xp-openblocks-ax3-4.dtb
---- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
-@@ -196,8 +196,6 @@
- #interrupt-cells = <2>;
- interrupts = <87>, <88>, <89>;
- };
--
-- /*
- };
- };
- };
projects / openwrt / staging / adrian.git / commitdiff