MIPS: Loongson64: Rename CPU TYPES

CPU_LOONGSON2 -> CPU_LOONGSON2EF
CPU_LOONGSON3 -> CPU_LOONGSON64

As newer loongson-2 products (2G/2H/2K1000) can share kernel
implementation with loongson-3 while 2E/2F are less similar with
other LOONGSON64 products.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: chenhc@lemote.com
Cc: paul.burton@mips.com

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f7ec1505013c2b6dace431bceaa3b8f0c636bc71..a4e8c75bc086014cbb569f6046a677fbff7b3b76 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1377,9 +1377,9 @@ choice
        prompt "CPU type"
        default CPU_R4X00
 
-config CPU_LOONGSON3
-       bool "Loongson 3 CPU"
-       depends on SYS_HAS_CPU_LOONGSON3
+config CPU_LOONGSON64
+       bool "Loongson GSx64 CPU"
+       depends on SYS_HAS_CPU_LOONGSON64
        select ARCH_HAS_PHYS_TO_DMA
        select CPU_SUPPORTS_64BIT_KERNEL
        select CPU_SUPPORTS_HIGHMEM
@@ -1394,19 +1394,19 @@ config CPU_LOONGSON3
        select GPIOLIB
        select SWIOTLB
        help
-               The Loongson 3 processor implements the MIPS64R2 instruction
-               set with many extensions.
+               The Loongson GSx64 series of processor cores implements the
+               MIPS64R2 instruction set with many extensions.
 
-config LOONGSON3_ENHANCEMENT
-       bool "New Loongson 3 CPU Enhancements"
+config LOONGSON64_ENHANCEMENT
+       bool "New Loongson GSx64E CPU Enhancements"
        default n
        select CPU_MIPSR2
        select CPU_HAS_PREFETCH
-       depends on CPU_LOONGSON3
+       depends on CPU_LOONGSON64
        help
-         New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
+         New Loongson GSx64E cores (since Loongson-3A R2, as opposed to Loongson-3A
          R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
-         FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
+         FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
          Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
          Fast TLB refill support, etc.
 
@@ -1418,7 +1418,7 @@ config LOONGSON3_ENHANCEMENT
 config CPU_LOONGSON3_WORKAROUNDS
        bool "Old Loongson 3 LLSC Workarounds"
        default y if SMP
-       depends on CPU_LOONGSON3
+       depends on CPU_LOONGSON64
        help
          Loongson 3 processors have the llsc issues which require workarounds.
          Without workarounds the system may hang unexpectedly.
@@ -1433,7 +1433,7 @@ config CPU_LOONGSON3_WORKAROUNDS
 config CPU_LOONGSON2E
        bool "Loongson 2E"
        depends on SYS_HAS_CPU_LOONGSON2E
-       select CPU_LOONGSON2
+       select CPU_LOONGSON2EF
        help
          The Loongson 2E processor implements the MIPS III instruction set
          with many extensions.
@@ -1444,7 +1444,7 @@ config CPU_LOONGSON2E
 config CPU_LOONGSON2F
        bool "Loongson 2F"
        depends on SYS_HAS_CPU_LOONGSON2F
-       select CPU_LOONGSON2
+       select CPU_LOONGSON2EF
        select GPIOLIB
        help
          The Loongson 2F processor implements the MIPS III instruction set
@@ -1857,7 +1857,7 @@ config SYS_SUPPORTS_ZBOOT_UART_PROM
        bool
        select SYS_SUPPORTS_ZBOOT
 
-config CPU_LOONGSON2
+config CPU_LOONGSON2EF
        bool
        select CPU_SUPPORTS_32BIT_KERNEL
        select CPU_SUPPORTS_64BIT_KERNEL
@@ -1900,7 +1900,7 @@ config CPU_BMIPS5000
        select SYS_SUPPORTS_HOTPLUG_CPU
        select CPU_HAS_RIXI
 
-config SYS_HAS_CPU_LOONGSON3
+config SYS_HAS_CPU_LOONGSON64
        bool
        select CPU_SUPPORTS_CPUFREQ
        select CPU_HAS_RIXI
@@ -2162,7 +2162,7 @@ choice
 
 config PAGE_SIZE_4KB
        bool "4kB"
-       depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
+       depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
        help
          This option select the standard 4kB Linux page size.  On some
          R3000-family processors this is the only available page size.  Using
@@ -2616,7 +2616,7 @@ config CPU_SUPPORTS_MSA
 
 config ARCH_FLATMEM_ENABLE
        def_bool y
-       depends on !NUMA && !CPU_LOONGSON2
+       depends on !NUMA && !CPU_LOONGSON2EF
 
 config ARCH_SPARSEMEM_ENABLE
        bool
@@ -2697,7 +2697,7 @@ config NODES_SHIFT
 
 config HW_PERF_EVENTS
        bool "Enable hardware performance counter support for perf events"
-       depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
+       depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
        default y
        help
          Enable hardware performance counter support for perf events. If

diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 63b3468ede4cb0e1a6de5ee85e3f50271df6f3ec..6b7396a6a1151b0d575557392aca57d732545061 100644 (file)
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -33,7 +33,7 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *);
 #define cop2_present           1
 #define cop2_lazy_restore      0
 
-#elif defined(CONFIG_CPU_LOONGSON3)
+#elif defined(CONFIG_CPU_LOONGSON64)
 
 #define cop2_present           1
 #define cop2_lazy_restore      1

diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 7bbb66760a07c14f7332f05ea250a1d379ffae80..5117e9119b87c9d4102a5a8342454f300c0ff5f2 100644 (file)
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -15,13 +15,12 @@
 static inline int __pure __get_cpu_type(const int cpu_type)
 {
        switch (cpu_type) {
-#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
-    defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
-       case CPU_LOONGSON2:
+#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2EF)
+       case CPU_LOONGSON2EF:
 #endif
 
-#ifdef CONFIG_SYS_HAS_CPU_LOONGSON3
-       case CPU_LOONGSON3:
+#ifdef CONFIG_SYS_HAS_CPU_LOONGSON64
+       case CPU_LOONGSON64:
 #endif
 
 #if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 81ddb575502a96c46a4116da03b52bd9a7e5b744..0e3a8d4de09d182daba85e643088bc01ffe4e79a 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -319,8 +319,8 @@ enum cpu_type_enum {
        /*
         * MIPS64 class processors
         */
-       CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
-       CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+       CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF,
+       CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
        CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
 
        CPU_QEMU_GENERIC,

diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 0fa27446869afbd26c0b64995a02983ecfccaa66..ea6a8c4b49f352ec61136f5847356a49203f7223 100644 (file)
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -23,7 +23,7 @@
  * TLB hazards
  */
 #if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \
-       !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT)
+       !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON64_ENHANCEMENT)
 
 /*
  * MIPSR2 defines ehb for hazard avoidance
@@ -158,7 +158,7 @@ do {                                                                        \
 } while (0)
 
 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
-       defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
+       defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON64_ENHANCEMENT) || \
        defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
 
 /*

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 2b7b5673637278d210f5a817e7d6dcf44b7cea23..3f6ce74335b47982e8d1f8c4b16d9f4638227475 100644 (file)
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -306,7 +306,7 @@ static inline void iounmap(const volatile void __iomem *addr)
 #undef __IS_KSEG1
 }
 
-#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3)
+#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
 #define war_io_reorder_wmb()           wmb()
 #else
 #define war_io_reorder_wmb()           barrier()

diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index f0b862a83816b7f11d9c480bf23edaec17b90ee0..4d742acf2be0cb0c24727c7cb16b90139373ad97 100644 (file)
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -41,7 +41,7 @@ static inline unsigned long arch_local_irq_save(void)
        "       .set    push                                            \n"
        "       .set    reorder                                         \n"
        "       .set    noat                                            \n"
-#if defined(CONFIG_CPU_LOONGSON3) || defined (CONFIG_CPU_LOONGSON1)
+#if defined(CONFIG_CPU_LOONGSON64) || defined (CONFIG_CPU_LOONGSON1)
        "       mfc0    %[flags], $12                                   \n"
        "       di                                                      \n"
 #else

diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
index 4aca25f2ff06c4aeb0d7f78ecdca3c864b0a88d3..83ad90d8005d7bd3c39ee04cd1ddcc87bc14b0cf 100644 (file)
--- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -44,7 +44,7 @@
 #define cpu_has_vtag_icache    0
 #define cpu_has_watch          1
 
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
 #define cpu_has_wsbh           1
 #define cpu_has_ic_fills_f_dc  1
 #define cpu_hwrena_impl_bits   0xc0000000

diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index be9f727a932803d50b4a379f8a8f83372c3b2197..557e069c400c312a4074ce1b1352803401d1638a 100644 (file)
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -4,7 +4,7 @@
 
 #include <boot_param.h>
 
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
 
 /* cpu core interrupt numbers */
 #define MIPS_CPU_IRQ_BASE 56

diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
index b9687320024d98be429d1f0ffe87ebc3f93fa940..28ccb06c8289851ab204850cd7919d89362e947c 100644 (file)
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -17,7 +17,7 @@
  * Override macros used in arch/mips/kernel/head.S.
  */
        .macro  kernel_entry_setup
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
        .set    push
        .set    mips64
        /* Set LPA on LOONGSON3 config3 */
@@ -54,7 +54,7 @@
  * Do SMP slave processor setup.
  */
        .macro  smp_slave_setup
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
        .set    push
        .set    mips64
        /* Set LPA on LOONGSON3 config3 */

diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index 694a58574ec083dc20093f971d673b842cb1eb80..40a24b76b8740d4cbcd049cf31663021ac452e79 100644 (file)
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -109,7 +109,7 @@ static inline void do_perfcnt_IRQ(void)
 #define LOONGSON_PCICFG_SIZE   0x00000800      /* 2K */
 #define LOONGSON_PCICFG_TOP    (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
 
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
 #define LOONGSON_PCIIO_BASE    loongson_sysconf.pci_io_base
 #else
 #define LOONGSON_PCIIO_BASE    0x1fd00000

diff --git a/arch/mips/include/asm/mach-loongson64/pci.h b/arch/mips/include/asm/mach-loongson64/pci.h
index 97f807fb211748aad07515ee192e46f5161ca8f6..05cc9052772f3a9f09045cca637832452b75ef83 100644 (file)
--- a/arch/mips/include/asm/mach-loongson64/pci.h
+++ b/arch/mips/include/asm/mach-loongson64/pci.h
@@ -35,7 +35,7 @@ extern struct pci_ops loongson_pci_ops;
 #else  /* loongson2f/32bit & loongson2e */
 
 /* this pci memory space is mapped by pcimap in pci.c */
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
 #define LOONGSON_PCI_MEM_START 0x40000000UL
 #define LOONGSON_PCI_MEM_END   0x7effffffUL
 #else

diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index ed70994fbbec963b36fe0629e480011029ae09bf..9fe9515204d6ca3d13cb326852b01ce7acf49167 100644 (file)
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -121,10 +121,10 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "SB1 "
 #elif defined CONFIG_CPU_LOONGSON1
 #define MODULE_PROC_FAMILY "LOONGSON1 "
-#elif defined CONFIG_CPU_LOONGSON2
-#define MODULE_PROC_FAMILY "LOONGSON2 "
-#elif defined CONFIG_CPU_LOONGSON3
-#define MODULE_PROC_FAMILY "LOONGSON3 "
+#elif defined CONFIG_CPU_LOONGSON2EF
+#define MODULE_PROC_FAMILY "LOONGSON2EF "
+#elif defined CONFIG_CPU_LOONGSON64
+#define MODULE_PROC_FAMILY "LOONGSON64 "
 #elif defined CONFIG_CPU_CAVIUM_OCTEON
 #define MODULE_PROC_FAMILY "OCTEON "
 #elif defined CONFIG_CPU_XLR

diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index fba18d4a9190990cedf7ab4bb939a5db92bb5641..7619ad319400c7ebe99a44748afc0be0381fe0cc 100644 (file)
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -385,7 +385,7 @@ unsigned long get_wchan(struct task_struct *p);
 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
 
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
 /*
  * Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a
  * tight read loop is executed, because reads take priority over writes & the

diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index e73fc9e899d2723567b92f9621f2b91c30c2b70d..15ab16f99f2858b6fc5eb33422cdd623ef51dd07 100644 (file)
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -72,7 +72,7 @@ static inline void flush_scache_line_indexed(unsigned long addr)
 static inline void flush_icache_line(unsigned long addr)
 {
        switch (boot_cpu_type()) {
-       case CPU_LOONGSON2:
+       case CPU_LOONGSON2EF:
                cache_op(Hit_Invalidate_I_Loongson2, addr);
                break;
 
@@ -154,7 +154,7 @@ static inline void flush_scache_line(unsigned long addr)
 static inline int protected_flush_icache_line(unsigned long addr)
 {
        switch (boot_cpu_type()) {
-       case CPU_LOONGSON2:
+       case CPU_LOONGSON2EF:
                return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
 
        default:

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bbfc954615c8407ffa344fdf97a99344ebf97552..a8d49f111cce196327afe4cadf88e657531d3b20 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -608,7 +608,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
                if (!(flags & FTLB_EN))
                        return 1;
                return 0;
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON64:
                /* Flush ITLB, DTLB, VTLB and FTLB */
                write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
                              LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
@@ -1529,21 +1529,21 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
        case PRID_IMP_LOONGSON_64C:  /* Loongson-2/3 */
                switch (c->processor_id & PRID_REV_MASK) {
                case PRID_REV_LOONGSON2E:
-                       c->cputype = CPU_LOONGSON2;
+                       c->cputype = CPU_LOONGSON2EF;
                        __cpu_name[cpu] = "ICT Loongson-2";
                        set_elf_platform(cpu, "loongson2e");
                        set_isa(c, MIPS_CPU_ISA_III);
                        c->fpu_msk31 |= FPU_CSR_CONDX;
                        break;
                case PRID_REV_LOONGSON2F:
-                       c->cputype = CPU_LOONGSON2;
+                       c->cputype = CPU_LOONGSON2EF;
                        __cpu_name[cpu] = "ICT Loongson-2";
                        set_elf_platform(cpu, "loongson2f");
                        set_isa(c, MIPS_CPU_ISA_III);
                        c->fpu_msk31 |= FPU_CSR_CONDX;
                        break;
                case PRID_REV_LOONGSON3A_R1:
-                       c->cputype = CPU_LOONGSON3;
+                       c->cputype = CPU_LOONGSON64;
                        __cpu_name[cpu] = "ICT Loongson-3";
                        set_elf_platform(cpu, "loongson3a");
                        set_isa(c, MIPS_CPU_ISA_M64R1);
@@ -1552,7 +1552,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                        break;
                case PRID_REV_LOONGSON3B_R1:
                case PRID_REV_LOONGSON3B_R2:
-                       c->cputype = CPU_LOONGSON3;
+                       c->cputype = CPU_LOONGSON64;
                        __cpu_name[cpu] = "ICT Loongson-3";
                        set_elf_platform(cpu, "loongson3b");
                        set_isa(c, MIPS_CPU_ISA_M64R1);
@@ -1908,14 +1908,14 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
                switch (c->processor_id & PRID_REV_MASK) {
                case PRID_REV_LOONGSON3A_R2_0:
                case PRID_REV_LOONGSON3A_R2_1:
-                       c->cputype = CPU_LOONGSON3;
+                       c->cputype = CPU_LOONGSON64;
                        __cpu_name[cpu] = "ICT Loongson-3";
                        set_elf_platform(cpu, "loongson3a");
                        set_isa(c, MIPS_CPU_ISA_M64R2);
                        break;
                case PRID_REV_LOONGSON3A_R3_0:
                case PRID_REV_LOONGSON3A_R3_1:
-                       c->cputype = CPU_LOONGSON3;
+                       c->cputype = CPU_LOONGSON64;
                        __cpu_name[cpu] = "ICT Loongson-3";
                        set_elf_platform(cpu, "loongson3a");
                        set_isa(c, MIPS_CPU_ISA_M64R2);
@@ -1929,7 +1929,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
                        MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
                break;
        case PRID_IMP_LOONGSON_64G:
-               c->cputype = CPU_LOONGSON3;
+               c->cputype = CPU_LOONGSON64;
                __cpu_name[cpu] = "ICT Loongson-3";
                set_elf_platform(cpu, "loongson3a");
                set_isa(c, MIPS_CPU_ISA_M64R2);

diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 980d6c39aab351aa18e7ab264ffb43c13a85709e..57dfa6c9edc52172d846e1d6eef022228280a3a7 100644 (file)
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -178,7 +178,7 @@ void __init check_wait(void)
        case CPU_XLP:
                cpu_wait = r4k_wait;
                break;
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON64:
                if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
                                (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0))
                        cpu_wait = r4k_wait;

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index a3e2da8391eac3382af7f5014f0de03bb7a2b437..0af456a949166754d19c911b620430086d8b9d21 100644 (file)
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1623,7 +1623,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
                        raw_event.cntr_mask =
                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
                break;
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON64:
                raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
        break;
        }
@@ -1769,7 +1769,7 @@ init_hw_perf_events(void)
                mipspmu.general_event_map = &mipsxxcore_event_map;
                mipspmu.cache_event_map = &mipsxxcore_cache_map;
                break;
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON64:
                mipspmu.name = "mips/loongson3";
                mipspmu.general_event_map = &loongson3_event_map;
                mipspmu.cache_event_map = &loongson3_cache_map;

diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 2af05879772fa7158c0d8fbf83a1fd7adc9e1cf5..c3d4212b5f1d4d5732dc9a45fbbc71ede2bdf274 100644 (file)
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -287,7 +287,7 @@ static unsigned long __init init_initrd(void)
  * Initialize the bootmem allocator. It also setup initrd related data
  * if needed.
  */
-#if defined(CONFIG_SGI_IP27) || (defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_NUMA))
+#if defined(CONFIG_SGI_IP27) || (defined(CONFIG_CPU_LOONGSON64) && defined(CONFIG_NUMA))
 
 static void __init bootmem_init(void)
 {

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 342e41de9d64ee5d2fa99d3ac5997f69c62954d5..0c2570e6fcf6b9de08573442284118b0679fd2ca 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2394,7 +2394,7 @@ void __init trap_init(void)
        else {
                if (cpu_has_vtag_icache)
                        set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
-               else if (current_cpu_type() == CPU_LOONGSON3)
+               else if (current_cpu_type() == CPU_LOONGSON64)
                        set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
                else
                        set_except_vector(EXCCODE_RI, handle_ri_rdhwr);

diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 2ff84f4b1717aebc3fa61e9bae5d892f30fd6d2c..fda7b57b826e6c0730538021b5d191efad6644d2 100644 (file)
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -279,7 +279,7 @@ EXPORT_SYMBOL(csum_partial)
 #endif
 
        /* odd buffer alignment? */
-#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3)
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON64)
        .set    push
        .set    arch=mips32r2
        wsbh    v1, sum
@@ -732,7 +732,7 @@ EXPORT_SYMBOL(csum_partial)
        addu    sum, v1
 #endif
 
-#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3)
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON64)
        .set    push
        .set    arch=mips32r2
        wsbh    v1, sum

diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig
index 4c14a11525f414a282b4dbadeaea66e7b583fd77..d08b20ff2b27bf98aff61a10000c11696fa6656a 100644 (file)
--- a/arch/mips/loongson64/Kconfig
+++ b/arch/mips/loongson64/Kconfig
@@ -79,7 +79,7 @@ config LOONGSON_MACH3X
        select I8259
        select IRQ_MIPS_CPU
        select NR_CPUS_DEFAULT_4
-       select SYS_HAS_CPU_LOONGSON3
+       select SYS_HAS_CPU_LOONGSON64
        select SYS_HAS_EARLY_PRINTK
        select SYS_SUPPORTS_SMP
        select SYS_SUPPORTS_HOTPLUG_CPU

diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 1a5df773707d752586bec19e35089ccd73340a4c..c74bc0251e9d6e8b165a53b0d1c5a053ba062202 100644 (file)
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -21,4 +21,4 @@ obj-$(CONFIG_LEMOTE_MACH2F)  += lemote-2f/
 # All Loongson-3 family machines
 #
 
-obj-$(CONFIG_CPU_LOONGSON3)  += loongson-3/
+obj-$(CONFIG_CPU_LOONGSON64)  += loongson-3/

diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform
index 28172500f95ae4e60db55cbaa980179ff8bd6865..4da74eea7de885060f35e49253ab255b09f02db3 100644 (file)
--- a/arch/mips/loongson64/Platform
+++ b/arch/mips/loongson64/Platform
@@ -3,7 +3,7 @@
 #
 
 # Only gcc >= 4.4 have Loongson specific support
-cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2EF)       += -Wa,--trap
 cflags-$(CONFIG_CPU_LOONGSON2E) += \
        $(call cc-option,-march=loongson2e,-march=r4600)
 cflags-$(CONFIG_CPU_LOONGSON2F) += \
@@ -22,7 +22,7 @@ ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
   endif
 endif
 
-cflags-$(CONFIG_CPU_LOONGSON3) += -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON64)        += -Wa,--trap
 
 #
 # Some versions of binutils, not currently mainline as of 2019/02/04, support
@@ -44,7 +44,7 @@ cflags-$(CONFIG_CPU_LOONGSON3)        += -Wa,--trap
 # binutils does not merge support for the flag then we can revisit & remove
 # this later - for now it ensures vendor toolchains don't cause problems.
 #
-cflags-$(CONFIG_CPU_LOONGSON3) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
+cflags-$(CONFIG_CPU_LOONGSON64)        += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
 
 #
 # binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
@@ -55,14 +55,14 @@ cflags-$(CONFIG_CPU_LOONGSON3)      += $(call as-option,-Wa$(comma)-mno-fix-loongson3
 #
 ifeq ($(call cc-ifversion, -ge, 0409, y), y)
   ifeq ($(call ld-ifversion, -ge, 225000000, y), y)
-    cflags-$(CONFIG_CPU_LOONGSON3)  += \
+    cflags-$(CONFIG_CPU_LOONGSON64)  += \
       $(call cc-option,-march=loongson3a -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
   else
-    cflags-$(CONFIG_CPU_LOONGSON3)  += \
+    cflags-$(CONFIG_CPU_LOONGSON64)  += \
       $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
   endif
 else
-    cflags-$(CONFIG_CPU_LOONGSON3)  += \
+    cflags-$(CONFIG_CPU_LOONGSON64)  += \
       $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
 endif
 

diff --git a/arch/mips/loongson64/common/pci.c b/arch/mips/loongson64/common/pci.c
index c47bb7bf3aa4365cadf547af847a1754993e4ebc..2d9755c495246d34e9b3642242b0585847869c27 100644 (file)
--- a/arch/mips/loongson64/common/pci.c
+++ b/arch/mips/loongson64/common/pci.c
@@ -87,7 +87,7 @@ static int __init pcibios_init(void)
 #endif
        register_pci_controller(&loongson_pci_controller);
 
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
        sbx00_acpi_init();
 #endif
 

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 378cbb02dcdd72b4bb7a94c16fde9dd2abb29778..9d82cb9ced55e2a6fd08714602cb1f3a576faec6 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -324,7 +324,7 @@ static void r4k_blast_icache_page_setup(void)
                r4k_blast_icache_page = (void *)cache_noop;
        else if (ic_lsize == 16)
                r4k_blast_icache_page = blast_icache16_page;
-       else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
+       else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF)
                r4k_blast_icache_page = loongson2_blast_icache32_page;
        else if (ic_lsize == 32)
                r4k_blast_icache_page = blast_icache32_page;
@@ -373,7 +373,7 @@ static void r4k_blast_icache_page_indexed_setup(void)
                else if (TX49XX_ICACHE_INDEX_INV_WAR)
                        r4k_blast_icache_page_indexed =
                                tx49_blast_icache32_page_indexed;
-               else if (current_cpu_type() == CPU_LOONGSON2)
+               else if (current_cpu_type() == CPU_LOONGSON2EF)
                        r4k_blast_icache_page_indexed =
                                loongson2_blast_icache32_page_indexed;
                else
@@ -399,7 +399,7 @@ static void r4k_blast_icache_setup(void)
                        r4k_blast_icache = blast_r4600_v1_icache32;
                else if (TX49XX_ICACHE_INDEX_INV_WAR)
                        r4k_blast_icache = tx49_blast_icache32;
-               else if (current_cpu_type() == CPU_LOONGSON2)
+               else if (current_cpu_type() == CPU_LOONGSON2EF)
                        r4k_blast_icache = loongson2_blast_icache32;
                else
                        r4k_blast_icache = blast_icache32;
@@ -469,7 +469,7 @@ static void r4k_blast_scache_node_setup(void)
 {
        unsigned long sc_lsize = cpu_scache_line_size();
 
-       if (current_cpu_type() != CPU_LOONGSON3)
+       if (current_cpu_type() != CPU_LOONGSON64)
                r4k_blast_scache_node = (void *)cache_noop;
        else if (sc_lsize == 16)
                r4k_blast_scache_node = blast_scache16_node;
@@ -484,7 +484,7 @@ static void r4k_blast_scache_node_setup(void)
 static inline void local_r4k___flush_cache_all(void * args)
 {
        switch (current_cpu_type()) {
-       case CPU_LOONGSON2:
+       case CPU_LOONGSON2EF:
        case CPU_R4000SC:
        case CPU_R4000MC:
        case CPU_R4400SC:
@@ -501,7 +501,7 @@ static inline void local_r4k___flush_cache_all(void * args)
                r4k_blast_scache();
                break;
 
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON64:
                /* Use get_ebase_cpunum() for both NUMA=y/n */
                r4k_blast_scache_node(get_ebase_cpunum() >> 2);
                break;
@@ -774,7 +774,7 @@ static inline void __local_r4k_flush_icache_range(unsigned long start,
                r4k_blast_icache();
        else {
                switch (boot_cpu_type()) {
-               case CPU_LOONGSON2:
+               case CPU_LOONGSON2EF:
                        protected_loongson2_blast_icache_range(start, end);
                        break;
 
@@ -867,7 +867,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
        preempt_disable();
        if (cpu_has_inclusive_pcaches) {
                if (size >= scache_size) {
-                       if (current_cpu_type() != CPU_LOONGSON3)
+                       if (current_cpu_type() != CPU_LOONGSON64)
                                r4k_blast_scache();
                        else
                                r4k_blast_scache_node(pa_to_nid(addr));
@@ -908,7 +908,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
        preempt_disable();
        if (cpu_has_inclusive_pcaches) {
                if (size >= scache_size) {
-                       if (current_cpu_type() != CPU_LOONGSON3)
+                       if (current_cpu_type() != CPU_LOONGSON64)
                                r4k_blast_scache();
                        else
                                r4k_blast_scache_node(pa_to_nid(addr));
@@ -1228,7 +1228,7 @@ static void probe_pcache(void)
                c->options |= MIPS_CPU_PREFETCH;
                break;
 
-       case CPU_LOONGSON2:
+       case CPU_LOONGSON2EF:
                icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
                c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                if (prid & 0x3)
@@ -1246,7 +1246,7 @@ static void probe_pcache(void)
                c->dcache.waybit = 0;
                break;
 
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON64:
                config1 = read_c0_config1();
                lsize = (config1 >> 19) & 7;
                if (lsize)
@@ -1457,7 +1457,7 @@ static void probe_pcache(void)
                c->dcache.flags &= ~MIPS_CACHE_ALIASES;
                break;
 
-       case CPU_LOONGSON2:
+       case CPU_LOONGSON2EF:
                /*
                 * LOONGSON2 has 4 way icache, but when using indexed cache op,
                 * one op will act on all 4 ways
@@ -1483,7 +1483,7 @@ static void probe_vcache(void)
        struct cpuinfo_mips *c = &current_cpu_data;
        unsigned int config2, lsize;
 
-       if (current_cpu_type() != CPU_LOONGSON3)
+       if (current_cpu_type() != CPU_LOONGSON64)
                return;
 
        config2 = read_c0_config2();
@@ -1658,11 +1658,11 @@ static void setup_scache(void)
 #endif
                return;
 
-       case CPU_LOONGSON2:
+       case CPU_LOONGSON2EF:
                loongson2_sc_init();
                return;
 
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON64:
                loongson3_sc_init();
                return;
 
@@ -1931,7 +1931,7 @@ void r4k_cache_init(void)
                /* Optimization: an L2 flush implicitly flushes the L1 */
                current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
                break;
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON64:
                /* Loongson-3 maintains cache coherency by hardware */
                __flush_cache_all       = cache_noop;
                __flush_cache_vmap      = cache_noop;

diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 56e4f8bffd4cd96a0439abac031b48d4c57634f6..c5578897a4fadaaa1757adadebb10f828edd6fd8 100644 (file)
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -187,7 +187,7 @@ static void set_prefetch_parameters(void)
                        }
                        break;
 
-               case CPU_LOONGSON3:
+               case CPU_LOONGSON64:
                        /* Loongson-3 only support the Pref_Load/Pref_Store. */
                        pref_bias_clear_store = 128;
                        pref_bias_copy_load = 128;

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index c13e46ced4252d483a580d3364481e5821467f91..83b450ddbbc29287178eea2fa2717a99214a4790 100644 (file)
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -35,10 +35,10 @@ extern void build_tlb_refill_handler(void);
 static inline void flush_micro_tlb(void)
 {
        switch (current_cpu_type()) {
-       case CPU_LOONGSON2:
+       case CPU_LOONGSON2EF:
                write_c0_diag(LOONGSON_DIAG_ITLB);
                break;
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON64:
                write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB);
                break;
        default:

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index e01cb33bfa1a78a67638d5b27fb8fc7e43df3e09..b963209bec0243626260e65a73cc10765ad443f0 100644 (file)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -571,8 +571,8 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l,
        case CPU_BMIPS4350:
        case CPU_BMIPS4380:
        case CPU_BMIPS5000:
-       case CPU_LOONGSON2:
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON2EF:
+       case CPU_LOONGSON64:
        case CPU_R5500:
                if (m4kc_tlbp_war())
                        uasm_i_nop(p);
@@ -1370,7 +1370,7 @@ static void build_r4000_tlb_refill_handler(void)
        switch (boot_cpu_type()) {
        default:
                if (sizeof(long) == 4) {
-       case CPU_LOONGSON2:
+       case CPU_LOONGSON2EF:
                /* Loongson2 ebase is different than r4k, we have more space */
                        if ((p - tlb_handler) > 64)
                                panic("TLB refill handler space exceeded");

diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 011cf9f891e774ec566109e4a2793397cd2d871e..e10f216d04220adc74fb8c6dbd8ca93d9a180134 100644 (file)
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -14,5 +14,5 @@ oprofile-$(CONFIG_CPU_MIPS64)         += op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_R10000)          += op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_SB1)             += op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_XLR)             += op_model_mipsxx.o
-oprofile-$(CONFIG_CPU_LOONGSON2)       += op_model_loongson2.o
-oprofile-$(CONFIG_CPU_LOONGSON3)       += op_model_loongson3.o
+oprofile-$(CONFIG_CPU_LOONGSON2EF)     += op_model_loongson2.o
+oprofile-$(CONFIG_CPU_LOONGSON64)      += op_model_loongson3.o

diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 2f33992f6dff00dbf54321a5f00089e73acd14e5..25cfa70f0ae497f75839b242478ccc3006ad6a6d 100644 (file)
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -104,10 +104,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
                lmodel = &op_model_mipsxx_ops;
                break;
 
-       case CPU_LOONGSON2:
+       case CPU_LOONGSON2EF:
                lmodel = &op_model_loongson2_ops;
                break;
-       case CPU_LOONGSON3:
+       case CPU_LOONGSON64:
                lmodel = &op_model_loongson3_ops;
                break;
        };

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 38e096e6925fa65dfbd95e84bf9081feeba43cd0..92d0ff63b3ea7cb9cf5b74e84217dbb3558a986e 100644 (file)
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -298,7 +298,7 @@ config GPIO_IXP4XX
 
 config GPIO_LOONGSON
        bool "Loongson-2/3 GPIO support"
-       depends on CPU_LOONGSON2 || CPU_LOONGSON3
+       depends on CPU_LOONGSON2EF || CPU_LOONGSON64
        help
          driver for GPIO functionality on Loongson-2F/3A/3B processors.
 

diff --git a/drivers/gpio/gpio-loongson.c b/drivers/gpio/gpio-loongson.c
index 00943170ce369a00ae2727a9576af58557ef4d1f..a42145873cc92ab1628ed11b354cb648f5a09150 100644 (file)
--- a/drivers/gpio/gpio-loongson.c
+++ b/drivers/gpio/gpio-loongson.c
@@ -22,7 +22,7 @@
 #define STLS2F_N_GPIO          4
 #define STLS3A_N_GPIO          16
 
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
 #define LOONGSON_N_GPIO        STLS3A_N_GPIO
 #else
 #define LOONGSON_N_GPIO        STLS2F_N_GPIO

diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index 987ff16b9420c1e34e55444bf7d02dc2ed7a70c2..e9ad4863d91568b4d95047fc98a53284ef93a96b 100644 (file)
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -45,7 +45,7 @@ static inline bool drm_arch_can_wc_memory(void)
 {
 #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
        return false;
-#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3)
+#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64)
        return false;
 #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
        /*