drm/i915/bxt: Add BXT support in gen8_irq functions

This patch adds conditional checks in gen8_irq functions
to support BXT. Most of the checks just look for PCH split
availability, and block the call to PCH interrupt functions if
not available.

v2: (jani)
- drop redundant TODO comment about PCH IRQ flags on BXT
- check HAS_PCH_SPLIT instead of IS_BROXTON when handling PCH specific
  IRQ events in gen8_irq_handler()
- check HAS_PCH_SPLIT before calling the function instead of a
  corresponding early return within the called function for
  ibx_irq_reset(), ibx_irq_pre_postinstall(), ibx_irq_postinstall()
v3: (jani)
- in ironlake_irq_postinstall() and ironlake_irq_reset() HAS_PCH_SPLIT
  is always true, so drop the check for it

Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <ppashank.sharma@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ac68b5bd8f1503a1a90ce5dc319b181148f77740..17a8f8c61753e8c7429574bd94aab353f70445e3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2297,7 +2297,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
                        DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
        }
 
-       if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
+       if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
+           master_ctl & GEN8_DE_PCH_IRQ) {
                /*
                 * FIXME(BDW): Assume for now that the new interrupt handling
                 * scheme also closed the SDE interrupt handling race we've seen
@@ -3133,7 +3134,8 @@ static void gen8_irq_reset(struct drm_device *dev)
        GEN5_IRQ_RESET(GEN8_DE_MISC_);
        GEN5_IRQ_RESET(GEN8_PCU_);
 
-       ibx_irq_reset(dev);
+       if (HAS_PCH_SPLIT(dev))
+               ibx_irq_reset(dev);
 }
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3545,12 +3547,14 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
 
-       ibx_irq_pre_postinstall(dev);
+       if (HAS_PCH_SPLIT(dev))
+               ibx_irq_pre_postinstall(dev);
 
        gen8_gt_irq_postinstall(dev_priv);
        gen8_de_irq_postinstall(dev_priv);
 
-       ibx_irq_postinstall(dev);
+       if (HAS_PCH_SPLIT(dev))
+               ibx_irq_postinstall(dev);
 
        I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
        POSTING_READ(GEN8_MASTER_IRQ);