gma500: Fix incorrect SR issue when disabling CRTC already in disabled state

Currently when trying to call the DPMS off again for one CRTC with DPMS off,
it will firstly disable the SR and can't enable it again because of the
incorrect check/logic. In such case the self refresh is still disabled
although one CRTC pipe is active. This is wrong.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
[Ported to in kernel driver]
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index a68509ba22a8ae705421307e17c6a9c13d08331c..5c3a3121ad188d1108db66e1874bfd40acff3917 100644 (file)
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -791,7 +791,7 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
        case DRM_MODE_DPMS_STANDBY:
        case DRM_MODE_DPMS_SUSPEND:
                if (psb_intel_crtc->active)
-                       return;
+                       break;
 
                psb_intel_crtc->active = true;
 
@@ -835,7 +835,6 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
                REG_WRITE(map->status, temp);
                REG_READ(map->status);
 
-               cdv_intel_update_watermark(dev, crtc);
                cdv_intel_crtc_load_lut(crtc);
 
                /* Give the overlay scaler a chance to enable
@@ -845,7 +844,7 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
                break;
        case DRM_MODE_DPMS_OFF:
                if (!psb_intel_crtc->active)
-                       return;
+                       break;
 
                psb_intel_crtc->active = false;
 
@@ -892,10 +891,10 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
 
                /* Wait for the clocks to turn off. */
                udelay(150);
-               cdv_intel_update_watermark(dev, crtc);
                psb_intel_crtc->crtc_enable = false;
                break;
        }
+       cdv_intel_update_watermark(dev, crtc);
        /*Set FIFO Watermarks*/
        REG_WRITE(DSPARB, 0x3F3E);
 }