ppc/85xx: Fix enabling of L2 cache

We need to flash invalidate the locks in addition to the cache
before we enable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a6d1e999b60c198bd1a73046dffe7e367d71d505..a8d83b1c8a3d73f4c000beee5a8ca2ff981a6a45 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -336,8 +336,8 @@ int cpu_init_r(void)
        u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 
        /* invalidate the L2 cache */
-       mtspr(SPRN_L2CSR0, L2CSR0_L2FI);
-       while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI)
+       mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
+       while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
                ;
 
        /* enable the cache */

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 074b056b7497b2c57cd8a798f12e272e5317401a..ecbd0d585770474704224a422a04d445caca8eff 100644 (file)
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -102,7 +102,8 @@ __secondary_start_page:
 #ifdef CONFIG_BACKSIDE_L2_CACHE
        /* Enable/invalidate the L2 cache */
        msync
-       lis     r3,L2CSR0_L2FI@h
+       lis     r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
+       ori     r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
        mtspr   SPRN_L2CSR0,r3
 1:
        mfspr   r3,SPRN_L2CSR0