Tegra186: trampoline: update "System Suspend" exit criteria

The TZRAM memory loses its state during "System Suspend". This patch
check if TZRAM base address contains valid data, to decide if the system
is exiting from "System Suspend". To enable TZDRAM encryption, the Memory
Controller's TZDRAM base/size registers would be populated by the BPMP
when the system "wakes up".

Change-Id: I5fc8ba1ae3bce12f0ece493f6f9f5f4d92a46344
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
index 7619ed0c9dd640c93863353fe59b3dbb8d1b2ab4..21393d9b966dd210e23f4c8e6bc25cd6da4fcbdd 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
@@ -42,18 +42,14 @@
 /* CPU reset handler routine */
 func tegra186_cpu_reset_handler
        /*
-        * The Memory Controller loses state during System Suspend. We
-        * use this information to decide if the reset handler is running
-        * after a System Suspend. Resume from system suspend requires
-        * restoring the entire state from TZDRAM to TZRAM.
+        * The TZRAM loses state during System Suspend. We use this
+        * information to decide if the reset handler is running after a
+        * System Suspend. Resume from system suspend requires restoring
+        * the entire state from TZDRAM to TZRAM.
         */
-       mov     x1, #TEGRA_MC_BASE
-       ldr     w0, [x1, #MC_SECURITY_CFG3_0]
-       lsl     x0, x0, #32
-       ldr     w0, [x1, #MC_SECURITY_CFG0_0]
-       adr     x1, tegra186_cpu_reset_handler
-       cmp     x0, x1
-       beq     boot_cpu
+       mov     x0, #BL31_BASE
+       ldr     x0, [x0]
+       cbnz    x0, boot_cpu
 
        /* resume from system suspend */
        mov     x0, #BL31_BASE