clk: sunxi-ng: r40: Add minimal rate for video PLLs

According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.

Because of that, set minimal rate to both R40 video PLLs to 192 MHz.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 65ba6455feb790ee4ef944dc1f36c49c5b4a26f2..d52af1785644025602fb8ee71519c059f52f2e9a 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -66,17 +66,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
                                   CLK_SET_RATE_UNGATE);
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
-                                       "osc24M", 0x0010,
-                                       8, 7,           /* N */
-                                       0, 4,           /* M */
-                                       BIT(24),        /* frac enable */
-                                       BIT(25),        /* frac select */
-                                       270000000,      /* frac rate 0 */
-                                       297000000,      /* frac rate 1 */
-                                       BIT(31),        /* gate */
-                                       BIT(28),        /* lock */
-                                       CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
+                                           "osc24M", 0x0010,
+                                           192000000,  /* Minimum rate */
+                                           8, 7,       /* N */
+                                           0, 4,       /* M */
+                                           BIT(24),    /* frac enable */
+                                           BIT(25),    /* frac select */
+                                           270000000,  /* frac rate 0 */
+                                           297000000,  /* frac rate 1 */
+                                           BIT(31),    /* gate */
+                                           BIT(28),    /* lock */
+                                           CLK_SET_RATE_UNGATE);
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
@@ -152,17 +153,18 @@ static struct ccu_nk pll_periph1_clk = {
 };
 
 /* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
-                                       "osc24M", 0x030,
-                                       8, 7,           /* N */
-                                       0, 4,           /* M */
-                                       BIT(24),        /* frac enable */
-                                       BIT(25),        /* frac select */
-                                       270000000,      /* frac rate 0 */
-                                       297000000,      /* frac rate 1 */
-                                       BIT(31),        /* gate */
-                                       BIT(28),        /* lock */
-                                       CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
+                                           "osc24M", 0x030,
+                                           192000000,  /* Minimum rate */
+                                           8, 7,       /* N */
+                                           0, 4,       /* M */
+                                           BIT(24),    /* frac enable */
+                                           BIT(25),    /* frac select */
+                                           270000000,  /* frac rate 0 */
+                                           297000000,  /* frac rate 1 */
+                                           BIT(31),    /* gate */
+                                           BIT(28),    /* lock */
+                                           CLK_SET_RATE_UNGATE);
 
 static struct ccu_nkm pll_sata_clk = {
        .enable         = BIT(31),