drm/amdgpu: rework common ucode handling for vega10

Handle ucode differences in vega10.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 886f105958a5bc93abeb46f00cc273a09195f4b4..f990eecacb112a4d3aeebd981dea5331394bce23 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1181,6 +1181,7 @@ struct amdgpu_firmware {
        enum amdgpu_firmware_load_type load_type;
        struct amdgpu_bo *fw_buf;
        unsigned int fw_size;
+       unsigned int max_ucodes;
 };
 
 /*

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 73c3e664d99a5f202bec25a9b5d3132cc56b1dc1..a1891c93cdbf8780f110c5064ac2332c4b46467c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -260,10 +260,12 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
        return AMDGPU_FW_LOAD_DIRECT;
 }
 
-static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
-                               uint64_t mc_addr, void *kptr)
+static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
+                                      struct amdgpu_firmware_info *ucode,
+                                      uint64_t mc_addr, void *kptr)
 {
        const struct common_firmware_header *header = NULL;
+       const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
 
        if (NULL == ucode->fw)
                return 0;
@@ -276,11 +278,35 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
 
        header = (const struct common_firmware_header *)ucode->fw->data;
 
-       ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
-
-       memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
-              le32_to_cpu(header->ucode_array_offset_bytes)),
-              ucode->ucode_size);
+       cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
+
+       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
+           (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
+            ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
+            ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
+            ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT)) {
+               ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
+
+               memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+                                             le32_to_cpu(header->ucode_array_offset_bytes)),
+                      ucode->ucode_size);
+       } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
+                  ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
+               ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
+                       le32_to_cpu(cp_hdr->jt_size) * 4;
+
+               memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+                                             le32_to_cpu(header->ucode_array_offset_bytes)),
+                      ucode->ucode_size);
+       } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
+                  ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
+               ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
+
+               memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+                                             le32_to_cpu(header->ucode_array_offset_bytes) +
+                                             le32_to_cpu(cp_hdr->jt_offset) * 4),
+                      ucode->ucode_size);
+       }
 
        return 0;
 }
@@ -306,17 +332,18 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
                           (le32_to_cpu(header->jt_offset) * 4);
        memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
 
+       ucode->ucode_size += le32_to_cpu(header->jt_size) * 4;
+
        return 0;
 }
 
-
 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
 {
        struct amdgpu_bo **bo = &adev->firmware.fw_buf;
        uint64_t fw_mc_addr;
        void *fw_buf_ptr = NULL;
        uint64_t fw_offset = 0;
-       int i, err, max;
+       int i, err;
        struct amdgpu_firmware_info *ucode = NULL;
        const struct common_firmware_header *header = NULL;
 
@@ -349,29 +376,32 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
 
        amdgpu_bo_unreserve(*bo);
 
+       memset(fw_buf_ptr, 0, adev->firmware.fw_size);
+
        /*
         * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
         * ucode info here
         */
        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-               max = AMDGPU_UCODE_ID_MAXIMUM - 3;
+               adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
        else
-               max = AMDGPU_UCODE_ID_MAXIMUM;
+               adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
 
-       for (i = 0; i < max; i++) {
+       for (i = 0; i < adev->firmware.max_ucodes; i++) {
                ucode = &adev->firmware.ucode[i];
                if (ucode->fw) {
                        header = (const struct common_firmware_header *)ucode->fw->data;
-                       amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset,
-                                                   fw_buf_ptr + fw_offset);
-                       if (i == AMDGPU_UCODE_ID_CP_MEC1) {
+                       amdgpu_ucode_init_single_fw(adev, ucode, fw_mc_addr + fw_offset,
+                                                   (void *)((uint8_t *)fw_buf_ptr + fw_offset));
+                       if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
+                           adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
                                const struct gfx_firmware_header_v1_0 *cp_hdr;
                                cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
                                amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset,
                                                    fw_buf_ptr + fw_offset);
                                fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
                        }
-                       fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+                       fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
                }
        }
        return 0;
@@ -393,14 +423,8 @@ int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
 {
        int i;
        struct amdgpu_firmware_info *ucode = NULL;
-       int max;
-
-       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-               max = AMDGPU_UCODE_ID_MAXIMUM - 3;
-       else
-               max = AMDGPU_UCODE_ID_MAXIMUM;
 
-       for (i = 0; i < max; i++) {
+       for (i = 0; i < adev->firmware.max_ucodes; i++) {
                ucode = &adev->firmware.ucode[i];
                if (ucode->fw) {
                        ucode->mc_addr = 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 2b212b04ce54a982da70889e46c4cd91ea95c4fe..39a074980c8ce52a219cc78a371fa869343cef23 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -128,9 +128,14 @@ enum AMDGPU_UCODE_ID {
        AMDGPU_UCODE_ID_CP_PFP,
        AMDGPU_UCODE_ID_CP_ME,
        AMDGPU_UCODE_ID_CP_MEC1,
+       AMDGPU_UCODE_ID_CP_MEC1_JT,
        AMDGPU_UCODE_ID_CP_MEC2,
+       AMDGPU_UCODE_ID_CP_MEC2_JT,
        AMDGPU_UCODE_ID_RLC_G,
        AMDGPU_UCODE_ID_STORAGE,
+       AMDGPU_UCODE_ID_SMC,
+       AMDGPU_UCODE_ID_UVD,
+       AMDGPU_UCODE_ID_VCE,
        AMDGPU_UCODE_ID_MAXIMUM,
 };