--- /dev/null
+From f4e6d7cdbfae502788bc468295b232dec76ee57e Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Fri, 12 Mar 2021 13:11:01 -0800
+Subject: [PATCH] net: dsa: bcm_sf2: Fill in BCM4908 CFP entries
+
+The BCM4908 switch has 256 CFP entrie, update that setting so CFP can be
+used.
+
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/bcm_sf2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -1058,7 +1058,7 @@ static const struct bcm_sf2_of_data bcm_
+ .type = BCM4908_DEVICE_ID,
+ .core_reg_align = 0,
+ .reg_offsets = bcm_sf2_4908_reg_offsets,
+- .num_cfp_rules = 0, /* FIXME */
++ .num_cfp_rules = 256,
+ .num_crossbar_int_ports = 2,
+ };
+
--- /dev/null
+From 55cfeb396965c3906a84d09a9c487d065e37773b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 18 Mar 2021 09:01:42 +0100
+Subject: [PATCH 1/2] net: dsa: bcm_sf2: add function finding RGMII register
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Simple macro like REG_RGMII_CNTRL_P() is insufficient as:
+1. It doesn't validate port argument
+2. It doesn't support chipsets with non-lineral RGMII regs layout
+
+Missing port validation could result in getting register offset from out
+of array. Random memory -> random offset -> random reads/writes. It
+affected e.g. BCM4908 for REG_RGMII_CNTRL_P(7).
+
+Fixes: a78e86ed586d ("net: dsa: bcm_sf2: Prepare for different register layouts")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/bcm_sf2.c | 49 +++++++++++++++++++++++++++++-----
+ drivers/net/dsa/bcm_sf2_regs.h | 2 --
+ 2 files changed, 42 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -31,6 +31,31 @@
+ #include "b53/b53_priv.h"
+ #include "b53/b53_regs.h"
+
++static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
++{
++ switch (priv->type) {
++ case BCM4908_DEVICE_ID:
++ /* TODO */
++ break;
++ default:
++ switch (port) {
++ case 0:
++ return REG_RGMII_0_CNTRL;
++ case 1:
++ return REG_RGMII_1_CNTRL;
++ case 2:
++ return REG_RGMII_2_CNTRL;
++ default:
++ break;
++ }
++ }
++
++ WARN_ONCE(1, "Unsupported port %d\n", port);
++
++ /* RO fallback reg */
++ return REG_SWITCH_STATUS;
++}
++
+ static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
+ {
+ struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
+@@ -586,6 +611,7 @@ static void bcm_sf2_sw_mac_config(struct
+ {
+ struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
+ u32 id_mode_dis = 0, port_mode;
++ u32 reg_rgmii_ctrl;
+ u32 reg, offset;
+
+ if (port == core_readl(priv, CORE_IMP0_PRT_ID))
+@@ -615,10 +641,12 @@ static void bcm_sf2_sw_mac_config(struct
+ goto force_link;
+ }
+
++ reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
++
+ /* Clear id_mode_dis bit, and the existing port mode, let
+ * RGMII_MODE_EN bet set by mac_link_{up,down}
+ */
+- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
++ reg = reg_readl(priv, reg_rgmii_ctrl);
+ reg &= ~ID_MODE_DIS;
+ reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
+ reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
+@@ -633,7 +661,7 @@ static void bcm_sf2_sw_mac_config(struct
+ reg |= RX_PAUSE_EN;
+ }
+
+- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
++ reg_writel(priv, reg, reg_rgmii_ctrl);
+
+ force_link:
+ /* Force link settings detected from the PHY */
+@@ -659,6 +687,7 @@ static void bcm_sf2_sw_mac_link_set(stru
+ phy_interface_t interface, bool link)
+ {
+ struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
++ u32 reg_rgmii_ctrl;
+ u32 reg;
+
+ if (!phy_interface_mode_is_rgmii(interface) &&
+@@ -666,13 +695,15 @@ static void bcm_sf2_sw_mac_link_set(stru
+ interface != PHY_INTERFACE_MODE_REVMII)
+ return;
+
++ reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
++
+ /* If the link is down, just disable the interface to conserve power */
+- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
++ reg = reg_readl(priv, reg_rgmii_ctrl);
+ if (link)
+ reg |= RGMII_MODE_EN;
+ else
+ reg &= ~RGMII_MODE_EN;
+- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
++ reg_writel(priv, reg, reg_rgmii_ctrl);
+ }
+
+ static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
+--- a/drivers/net/dsa/bcm_sf2_regs.h
++++ b/drivers/net/dsa/bcm_sf2_regs.h
+@@ -55,8 +55,6 @@ enum bcm_sf2_reg_offs {
+ #define CROSSBAR_BCM4908_EXT_GPHY4 1
+ #define CROSSBAR_BCM4908_EXT_RGMII 2
+
+-#define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x))
+-
+ /* Relative to REG_RGMII_CNTRL */
+ #define RGMII_MODE_EN (1 << 0)
+ #define ID_MODE_DIS (1 << 1)
--- /dev/null
+From 6859d91549341c2ad769d482de58129f080c0f04 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 18 Mar 2021 09:01:43 +0100
+Subject: [PATCH 2/2] net: dsa: bcm_sf2: fix BCM4908 RGMII reg(s)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 has only 1 RGMII reg for controlling port 7.
+
+Fixes: 73b7a6047971 ("net: dsa: bcm_sf2: support BCM4908's integrated switch")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/bcm_sf2.c | 11 +++++++----
+ drivers/net/dsa/bcm_sf2_regs.h | 1 +
+ 2 files changed, 8 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -35,7 +35,12 @@ static u16 bcm_sf2_reg_rgmii_cntrl(struc
+ {
+ switch (priv->type) {
+ case BCM4908_DEVICE_ID:
+- /* TODO */
++ switch (port) {
++ case 7:
++ return REG_RGMII_11_CNTRL;
++ default:
++ break;
++ }
+ break;
+ default:
+ switch (port) {
+@@ -1077,9 +1082,7 @@ static const u16 bcm_sf2_4908_reg_offset
+ [REG_PHY_REVISION] = 0x14,
+ [REG_SPHY_CNTRL] = 0x24,
+ [REG_CROSSBAR] = 0xc8,
+- [REG_RGMII_0_CNTRL] = 0xe0,
+- [REG_RGMII_1_CNTRL] = 0xec,
+- [REG_RGMII_2_CNTRL] = 0xf8,
++ [REG_RGMII_11_CNTRL] = 0x014c,
+ [REG_LED_0_CNTRL] = 0x40,
+ [REG_LED_1_CNTRL] = 0x4c,
+ [REG_LED_2_CNTRL] = 0x58,
+--- a/drivers/net/dsa/bcm_sf2_regs.h
++++ b/drivers/net/dsa/bcm_sf2_regs.h
+@@ -21,6 +21,7 @@ enum bcm_sf2_reg_offs {
+ REG_RGMII_0_CNTRL,
+ REG_RGMII_1_CNTRL,
+ REG_RGMII_2_CNTRL,
++ REG_RGMII_11_CNTRL,
+ REG_LED_0_CNTRL,
+ REG_LED_1_CNTRL,
+ REG_LED_2_CNTRL,
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1285,10 +1285,14 @@ static int bcm_sf2_sw_probe(struct platf
+@@ -1319,10 +1319,14 @@ static int bcm_sf2_sw_probe(struct platf
rev = reg_readl(priv, REG_PHY_REVISION);
priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1299,6 +1299,12 @@ static int bcm_sf2_sw_probe(struct platf
+@@ -1333,6 +1333,12 @@ static int bcm_sf2_sw_probe(struct platf
priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
priv->irq0, priv->irq1);
+++ /dev/null
-From 7e2dc41c745f6d9c571919d98abed2d783fce8fb Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Sun, 14 Mar 2021 22:43:32 +0100
-Subject: [PATCH] net: dsa: bcm_sf2: quick fix for RGMII reg access on BCM4908
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 has only 1 RGMII register and it's used for port 7.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/net/dsa/bcm_sf2.c | 30 +++++++++++++++++++++++-------
- drivers/net/dsa/bcm_sf2_regs.h | 1 +
- 2 files changed, 24 insertions(+), 7 deletions(-)
-
---- a/drivers/net/dsa/bcm_sf2.c
-+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -587,10 +587,19 @@ static void bcm_sf2_sw_mac_config(struct
- struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
- u32 id_mode_dis = 0, port_mode;
- u32 reg, offset;
-+ u32 rgmii_ctrl;
-
- if (port == core_readl(priv, CORE_IMP0_PRT_ID))
- return;
-
-+ if (priv->type == BCM4908_DEVICE_ID) {
-+ if (port != 7)
-+ return;
-+ rgmii_ctrl = REG_RGMII_11_CNTRL;
-+ } else {
-+ rgmii_ctrl = REG_RGMII_CNTRL_P(port);
-+ }
-+
- if (priv->type == BCM4908_DEVICE_ID ||
- priv->type == BCM7445_DEVICE_ID)
- offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
-@@ -618,7 +627,7 @@ static void bcm_sf2_sw_mac_config(struct
- /* Clear id_mode_dis bit, and the existing port mode, let
- * RGMII_MODE_EN bet set by mac_link_{up,down}
- */
-- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
-+ reg = reg_readl(priv, rgmii_ctrl);
- reg &= ~ID_MODE_DIS;
- reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
- reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
-@@ -633,7 +642,7 @@ static void bcm_sf2_sw_mac_config(struct
- reg |= RX_PAUSE_EN;
- }
-
-- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
-+ reg_writel(priv, reg, rgmii_ctrl);
-
- force_link:
- /* Force link settings detected from the PHY */
-@@ -659,6 +668,7 @@ static void bcm_sf2_sw_mac_link_set(stru
- phy_interface_t interface, bool link)
- {
- struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
-+ u32 rgmii_ctrl;
- u32 reg;
-
- if (!phy_interface_mode_is_rgmii(interface) &&
-@@ -666,13 +676,21 @@ static void bcm_sf2_sw_mac_link_set(stru
- interface != PHY_INTERFACE_MODE_REVMII)
- return;
-
-+ if (priv->type == BCM4908_DEVICE_ID) {
-+ if (port != 7)
-+ return;
-+ rgmii_ctrl = REG_RGMII_11_CNTRL;
-+ } else {
-+ rgmii_ctrl = REG_RGMII_CNTRL_P(port);
-+ }
-+
- /* If the link is down, just disable the interface to conserve power */
-- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
-+ reg = reg_readl(priv, rgmii_ctrl);
- if (link)
- reg |= RGMII_MODE_EN;
- else
- reg &= ~RGMII_MODE_EN;
-- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
-+ reg_writel(priv, reg, rgmii_ctrl);
- }
-
- static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
-@@ -1046,9 +1064,7 @@ static const u16 bcm_sf2_4908_reg_offset
- [REG_PHY_REVISION] = 0x14,
- [REG_SPHY_CNTRL] = 0x24,
- [REG_CROSSBAR] = 0xc8,
-- [REG_RGMII_0_CNTRL] = 0xe0,
-- [REG_RGMII_1_CNTRL] = 0xec,
-- [REG_RGMII_2_CNTRL] = 0xf8,
-+ [REG_RGMII_11_CNTRL] = 0x014c,
- [REG_LED_0_CNTRL] = 0x40,
- [REG_LED_1_CNTRL] = 0x4c,
- [REG_LED_2_CNTRL] = 0x58,
---- a/drivers/net/dsa/bcm_sf2_regs.h
-+++ b/drivers/net/dsa/bcm_sf2_regs.h
-@@ -21,6 +21,7 @@ enum bcm_sf2_reg_offs {
- REG_RGMII_0_CNTRL,
- REG_RGMII_1_CNTRL,
- REG_RGMII_2_CNTRL,
-+ REG_RGMII_11_CNTRL,
- REG_LED_0_CNTRL,
- REG_LED_1_CNTRL,
- REG_LED_2_CNTRL,
projects / openwrt / staging / hauke.git / commitdiff