83xx: UEC: Added support for bitBang MII driver access to PHYs

This patch enabled support for having PHYs on bitBang MII and uec MII
operating at the same time. Modeled after the MPC8360ADS implementation.

Added the ability to specify which ethernet interfaces have bitbang SMI
on the board header file.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 27dc5009c80080951ce373f26c895f509b49318e..ccbf27d0be9cb400196845592a27ab2ac8306df7 100644 (file)
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -595,8 +595,7 @@ static void phy_change(struct eth_device *dev)
        adjust_link(dev);
 }
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
-       && !defined(BITBANGMII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 
 /*
  * Find a device index from the devlist by name
@@ -1388,8 +1387,7 @@ int uec_initialize(bd_t *bis, uec_info_t *uec_info)
                return err;
        }
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
-       && !defined(BITBANGMII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
        miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
 #endif
 

diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index fa48feaf04252c0c50167898b99ddf84efcfaf37..3baffe42fbcb37632cb80bb08c39cf44a965eb5e 100644 (file)
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -93,6 +93,27 @@ static const struct fixed_phy_port fixed_phy_port[] = {
        CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
 };
 
+/*--------------------------------------------------------------------+
+ * BitBang MII support for ethernet ports
+ *
+ * Based from MPC8560ADS implementation
+ *--------------------------------------------------------------------*/
+/*
+ * Example board header file to define bitbang ethernet ports:
+ *
+ * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
+ * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("FSL UEC0")
+*/
+#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
+#define CONFIG_SYS_BITBANG_PHY_PORTS   /* default is an empty array */
+#endif
+
+#if defined(CONFIG_BITBANGMII)
+static const char *bitbang_phy_port[] = {
+       CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
+};
+#endif /* CONFIG_BITBANGMII */
+
 static void config_genmii_advert (struct uec_mii_info *mii_info);
 static void genmii_setup_forced (struct uec_mii_info *mii_info);
 static void genmii_restart_aneg (struct uec_mii_info *mii_info);
@@ -113,6 +134,19 @@ void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int valu
        enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
        u32 tmp_reg;
 
+
+#if defined(CONFIG_BITBANGMII)
+       u32 i = 0;
+
+       for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
+               if (strncmp(dev->name, bitbang_phy_port[i],
+                       sizeof(dev->name)) == 0) {
+                       (void)bb_miiphy_write(NULL, mii_id, regnum, value);
+                       return;
+               }
+       }
+#endif /* CONFIG_BITBANGMII */
+
        ug_regs = ugeth->uec_mii_regs;
 
        /* Stop the MII management read cycle */
@@ -140,6 +174,19 @@ int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
        u32 tmp_reg;
        u16 value;
 
+
+#if defined(CONFIG_BITBANGMII)
+       u32 i = 0;
+
+       for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
+               if (strncmp(dev->name, bitbang_phy_port[i],
+                       sizeof(dev->name)) == 0) {
+                       (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
+                       return (value);
+               }
+       }
+#endif /* CONFIG_BITBANGMII */
+
        ug_regs = ugeth->uec_mii_regs;
 
        /* Setting up the MII Mangement Address Register */