arm: rmobile: r8a7791: Fix initialize L2 cache

rmobile/lowlevel_init_ca15.S are common in r8a7790 and r8a7791 of
rmobile SoC. But L2 cache of r8a7791 does not use L2CTLR[5].
This adds fix to set L2CTLR [5] only when the r8a7790.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index dbb96ed194af287609513bb17c30b9affc2281d3..5820e1a37a45a10b428cbc6409d074c61890413e 100644 (file)
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -53,7 +53,15 @@ do_lowlevel_init:
        cmp r1, #3                      /* has already been set up */
        bicne r0, r0, #0xe7
        orrne r0, r0, #0x83             /* L2CTLR[7:6] + L2CTLR[2:0] */
-       orrne r0, r0, #0x20             /* L2CTLR[5] */
+
+       ldr     r2, =0xFF000044         /* PRR */
+       ldr     r1, [r2]
+       and     r1, r1, #0x7F00
+       lsrs    r1, r1, #8
+       cmp     r1, #0x45               /* 0x45 is ID of r8a7790 */
+       bne     L2CTLR_5_SKIP
+       orrne r0, r0, #0x20             /* L2CTLR[5] */
+L2CTLR_5_SKIP:
        mcrne p15, 1, r0, c9, c0, 2
 
 _exit_init_l2_a15: