net/mlx5: Update enable HCA dependency
authorBodong Wang <bodong@mellanox.com>
Wed, 13 Feb 2019 06:55:36 +0000 (22:55 -0800)
committerSaeed Mahameed <saeedm@mellanox.com>
Thu, 14 Feb 2019 20:14:41 +0000 (12:14 -0800)
With the introduction of ECPF, we require that the ECPF driver will
aways call enable/disable HCA for that PF in the same way a PF does
this for its VFs. The PF is still responsible for calling enable and
disable HCA for its VFs.

To distinguish between the ECPF executing enable/disable HCA for
itself or for the PF, it sets the embedded CPU function bit in the
input params struct of these commands. When the bit is cleared and
function ID is zero, it refers to the peer PF.

Signed-off-by: Bodong Wang <bodong@mellanox.com>
Signed-off-by: Eli Cohen <eli@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/ecpf.c
drivers/net/ethernet/mellanox/mlx5/core/ecpf.h
drivers/net/ethernet/mellanox/mlx5/core/main.c
include/linux/mlx5/mlx5_ifc.h

index 28b8c5c5c8c7b2aa0691402e8e366cd1343d841a..1bcf8b8f97133b13707ab6f8c4c112016e4b5b4f 100644 (file)
@@ -7,3 +7,79 @@ bool mlx5_read_embedded_cpu(struct mlx5_core_dev *dev)
 {
        return (ioread32be(&dev->iseg->initializing) >> MLX5_ECPU_BIT_NUM) & 1;
 }
+
+static int mlx5_peer_pf_enable_hca(struct mlx5_core_dev *dev)
+{
+       u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {};
+       u32 in[MLX5_ST_SZ_DW(enable_hca_in)]   = {};
+
+       MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
+       MLX5_SET(enable_hca_in, in, function_id, 0);
+       MLX5_SET(enable_hca_in, in, embedded_cpu_function, 0);
+       return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
+}
+
+static int mlx5_peer_pf_disable_hca(struct mlx5_core_dev *dev)
+{
+       u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {};
+       u32 in[MLX5_ST_SZ_DW(disable_hca_in)]   = {};
+
+       MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
+       MLX5_SET(disable_hca_in, in, function_id, 0);
+       MLX5_SET(enable_hca_in, in, embedded_cpu_function, 0);
+       return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
+}
+
+static int mlx5_peer_pf_init(struct mlx5_core_dev *dev)
+{
+       int err;
+
+       err = mlx5_peer_pf_enable_hca(dev);
+       if (err)
+               mlx5_core_err(dev, "Failed to enable peer PF HCA err(%d)\n",
+                             err);
+
+       return err;
+}
+
+static void mlx5_peer_pf_cleanup(struct mlx5_core_dev *dev)
+{
+       int err;
+
+       err = mlx5_peer_pf_disable_hca(dev);
+       if (err) {
+               mlx5_core_err(dev, "Failed to disable peer PF HCA err(%d)\n",
+                             err);
+               return;
+       }
+
+       err = mlx5_wait_for_pages(dev, &dev->priv.peer_pf_pages);
+       if (err)
+               mlx5_core_warn(dev, "Timeout reclaiming peer PF pages err(%d)\n",
+                              err);
+}
+
+int mlx5_ec_init(struct mlx5_core_dev *dev)
+{
+       int err = 0;
+
+       if (!mlx5_core_is_ecpf(dev))
+               return 0;
+
+       /* ECPF shall enable HCA for peer PF in the same way a PF
+        * does this for its VFs.
+        */
+       err = mlx5_peer_pf_init(dev);
+       if (err)
+               return err;
+
+       return 0;
+}
+
+void mlx5_ec_cleanup(struct mlx5_core_dev *dev)
+{
+       if (!mlx5_core_is_ecpf(dev))
+               return;
+
+       mlx5_peer_pf_cleanup(dev);
+}
index 8b684f0ab48fa4c371c6227b904991348e2736b2..d3d7a00a02acdd2ffea2de899b4ef97639e2b6aa 100644 (file)
@@ -14,11 +14,15 @@ enum {
 };
 
 bool mlx5_read_embedded_cpu(struct mlx5_core_dev *dev);
+int mlx5_ec_init(struct mlx5_core_dev *dev);
+void mlx5_ec_cleanup(struct mlx5_core_dev *dev);
 
 #else  /* CONFIG_MLX5_ESWITCH */
 
 static inline bool
 mlx5_read_embedded_cpu(struct mlx5_core_dev *dev) { return false; }
+static inline int mlx5_ec_init(struct mlx5_core_dev *dev) { return 0; }
+static inline void mlx5_ec_cleanup(struct mlx5_core_dev *dev) {}
 
 #endif /* CONFIG_MLX5_ESWITCH */
 
index 08a3da2a8358812876af7753efca4dc30e664843..40d591c8e76ce793f7a3e7a8e318128c8bc8b8c1 100644 (file)
@@ -612,6 +612,8 @@ int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
 
        MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
        MLX5_SET(enable_hca_in, in, function_id, func_id);
+       MLX5_SET(enable_hca_in, in, embedded_cpu_function,
+                dev->caps.embedded_cpu);
        return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 }
 
@@ -622,6 +624,8 @@ int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
 
        MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
        MLX5_SET(disable_hca_in, in, function_id, func_id);
+       MLX5_SET(enable_hca_in, in, embedded_cpu_function,
+                dev->caps.embedded_cpu);
        return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 }
 
@@ -1071,6 +1075,12 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
                goto err_sriov;
        }
 
+       err = mlx5_ec_init(dev);
+       if (err) {
+               dev_err(&pdev->dev, "Failed to init embedded CPU\n");
+               goto err_ec;
+       }
+
        if (mlx5_device_registered(dev)) {
                mlx5_attach_device(dev);
        } else {
@@ -1088,6 +1098,9 @@ out:
        return 0;
 
 err_reg_dev:
+       mlx5_ec_cleanup(dev);
+
+err_ec:
        mlx5_sriov_detach(dev);
 
 err_sriov:
@@ -1162,6 +1175,7 @@ static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
        if (mlx5_device_registered(dev))
                mlx5_detach_device(dev);
 
+       mlx5_ec_cleanup(dev);
        mlx5_sriov_detach(dev);
        mlx5_cleanup_fs(dev);
        mlx5_accel_ipsec_cleanup(dev);
index 46799b4c8859e2dd945a795309fc2cc29bdf6c50..1b6d5a563a3aec6989460eca0b54ccac5be2dce7 100644 (file)
@@ -6061,7 +6061,8 @@ struct mlx5_ifc_enable_hca_in_bits {
        u8         reserved_at_20[0x10];
        u8         op_mod[0x10];
 
-       u8         reserved_at_40[0x10];
+       u8         embedded_cpu_function[0x1];
+       u8         reserved_at_41[0xf];
        u8         function_id[0x10];
 
        u8         reserved_at_60[0x20];
@@ -6105,7 +6106,8 @@ struct mlx5_ifc_disable_hca_in_bits {
        u8         reserved_at_20[0x10];
        u8         op_mod[0x10];
 
-       u8         reserved_at_40[0x10];
+       u8         embedded_cpu_function[0x1];
+       u8         reserved_at_41[0xf];
        u8         function_id[0x10];
 
        u8         reserved_at_60[0x20];